vc4_irq.c 8.5 KB

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  1. /*
  2. * Copyright © 2014 Broadcom
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. */
  23. /**
  24. * DOC: Interrupt management for the V3D engine
  25. *
  26. * We have an interrupt status register (V3D_INTCTL) which reports
  27. * interrupts, and where writing 1 bits clears those interrupts.
  28. * There are also a pair of interrupt registers
  29. * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
  30. * disables that specific interrupt, and 0s written are ignored
  31. * (reading either one returns the set of enabled interrupts).
  32. *
  33. * When we take a binning flush done interrupt, we need to submit the
  34. * next frame for binning and move the finished frame to the render
  35. * thread.
  36. *
  37. * When we take a render frame interrupt, we need to wake the
  38. * processes waiting for some frame to be done, and get the next frame
  39. * submitted ASAP (so the hardware doesn't sit idle when there's work
  40. * to do).
  41. *
  42. * When we take the binner out of memory interrupt, we need to
  43. * allocate some new memory and pass it to the binner so that the
  44. * current job can make progress.
  45. */
  46. #include "vc4_drv.h"
  47. #include "vc4_regs.h"
  48. #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
  49. V3D_INT_FLDONE | \
  50. V3D_INT_FRDONE)
  51. DECLARE_WAIT_QUEUE_HEAD(render_wait);
  52. static void
  53. vc4_overflow_mem_work(struct work_struct *work)
  54. {
  55. struct vc4_dev *vc4 =
  56. container_of(work, struct vc4_dev, overflow_mem_work);
  57. struct vc4_bo *bo;
  58. int bin_bo_slot;
  59. struct vc4_exec_info *exec;
  60. unsigned long irqflags;
  61. mutex_lock(&vc4->bin_bo_lock);
  62. if (!vc4->bin_bo)
  63. goto complete;
  64. bo = vc4->bin_bo;
  65. bin_bo_slot = vc4_v3d_get_bin_slot(vc4);
  66. if (bin_bo_slot < 0) {
  67. DRM_ERROR("Couldn't allocate binner overflow mem\n");
  68. goto complete;
  69. }
  70. spin_lock_irqsave(&vc4->job_lock, irqflags);
  71. if (vc4->bin_alloc_overflow) {
  72. /* If we had overflow memory allocated previously,
  73. * then that chunk will free when the current bin job
  74. * is done. If we don't have a bin job running, then
  75. * the chunk will be done whenever the list of render
  76. * jobs has drained.
  77. */
  78. exec = vc4_first_bin_job(vc4);
  79. if (!exec)
  80. exec = vc4_last_render_job(vc4);
  81. if (exec) {
  82. exec->bin_slots |= vc4->bin_alloc_overflow;
  83. } else {
  84. /* There's nothing queued in the hardware, so
  85. * the old slot is free immediately.
  86. */
  87. vc4->bin_alloc_used &= ~vc4->bin_alloc_overflow;
  88. }
  89. }
  90. vc4->bin_alloc_overflow = BIT(bin_bo_slot);
  91. V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size);
  92. V3D_WRITE(V3D_BPOS, bo->base.base.size);
  93. V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
  94. V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
  95. spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  96. complete:
  97. mutex_unlock(&vc4->bin_bo_lock);
  98. }
  99. static void
  100. vc4_irq_finish_bin_job(struct drm_device *dev)
  101. {
  102. struct vc4_dev *vc4 = to_vc4_dev(dev);
  103. struct vc4_exec_info *next, *exec = vc4_first_bin_job(vc4);
  104. if (!exec)
  105. return;
  106. vc4_move_job_to_render(dev, exec);
  107. next = vc4_first_bin_job(vc4);
  108. /* Only submit the next job in the bin list if it matches the perfmon
  109. * attached to the one that just finished (or if both jobs don't have
  110. * perfmon attached to them).
  111. */
  112. if (next && next->perfmon == exec->perfmon)
  113. vc4_submit_next_bin_job(dev);
  114. }
  115. static void
  116. vc4_cancel_bin_job(struct drm_device *dev)
  117. {
  118. struct vc4_dev *vc4 = to_vc4_dev(dev);
  119. struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
  120. if (!exec)
  121. return;
  122. /* Stop the perfmon so that the next bin job can be started. */
  123. if (exec->perfmon)
  124. vc4_perfmon_stop(vc4, exec->perfmon, false);
  125. list_move_tail(&exec->head, &vc4->bin_job_list);
  126. vc4_submit_next_bin_job(dev);
  127. }
  128. static void
  129. vc4_irq_finish_render_job(struct drm_device *dev)
  130. {
  131. struct vc4_dev *vc4 = to_vc4_dev(dev);
  132. struct vc4_exec_info *exec = vc4_first_render_job(vc4);
  133. struct vc4_exec_info *nextbin, *nextrender;
  134. if (!exec)
  135. return;
  136. vc4->finished_seqno++;
  137. list_move_tail(&exec->head, &vc4->job_done_list);
  138. nextbin = vc4_first_bin_job(vc4);
  139. nextrender = vc4_first_render_job(vc4);
  140. /* Only stop the perfmon if following jobs in the queue don't expect it
  141. * to be enabled.
  142. */
  143. if (exec->perfmon && !nextrender &&
  144. (!nextbin || nextbin->perfmon != exec->perfmon))
  145. vc4_perfmon_stop(vc4, exec->perfmon, true);
  146. /* If there's a render job waiting, start it. If this is not the case
  147. * we may have to unblock the binner if it's been stalled because of
  148. * perfmon (this can be checked by comparing the perfmon attached to
  149. * the finished renderjob to the one attached to the next bin job: if
  150. * they don't match, this means the binner is stalled and should be
  151. * restarted).
  152. */
  153. if (nextrender)
  154. vc4_submit_next_render_job(dev);
  155. else if (nextbin && nextbin->perfmon != exec->perfmon)
  156. vc4_submit_next_bin_job(dev);
  157. if (exec->fence) {
  158. dma_fence_signal_locked(exec->fence);
  159. dma_fence_put(exec->fence);
  160. exec->fence = NULL;
  161. }
  162. wake_up_all(&vc4->job_wait_queue);
  163. schedule_work(&vc4->job_done_work);
  164. }
  165. irqreturn_t
  166. vc4_irq(int irq, void *arg)
  167. {
  168. struct drm_device *dev = arg;
  169. struct vc4_dev *vc4 = to_vc4_dev(dev);
  170. uint32_t intctl;
  171. irqreturn_t status = IRQ_NONE;
  172. barrier();
  173. intctl = V3D_READ(V3D_INTCTL);
  174. /* Acknowledge the interrupts we're handling here. The binner
  175. * last flush / render frame done interrupt will be cleared,
  176. * while OUTOMEM will stay high until the underlying cause is
  177. * cleared.
  178. */
  179. V3D_WRITE(V3D_INTCTL, intctl);
  180. if (intctl & V3D_INT_OUTOMEM) {
  181. /* Disable OUTOMEM until the work is done. */
  182. V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
  183. schedule_work(&vc4->overflow_mem_work);
  184. status = IRQ_HANDLED;
  185. }
  186. if (intctl & V3D_INT_FLDONE) {
  187. spin_lock(&vc4->job_lock);
  188. vc4_irq_finish_bin_job(dev);
  189. spin_unlock(&vc4->job_lock);
  190. status = IRQ_HANDLED;
  191. }
  192. if (intctl & V3D_INT_FRDONE) {
  193. spin_lock(&vc4->job_lock);
  194. vc4_irq_finish_render_job(dev);
  195. spin_unlock(&vc4->job_lock);
  196. status = IRQ_HANDLED;
  197. }
  198. return status;
  199. }
  200. void
  201. vc4_irq_preinstall(struct drm_device *dev)
  202. {
  203. struct vc4_dev *vc4 = to_vc4_dev(dev);
  204. if (!vc4->v3d)
  205. return;
  206. init_waitqueue_head(&vc4->job_wait_queue);
  207. INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
  208. /* Clear any pending interrupts someone might have left around
  209. * for us.
  210. */
  211. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  212. }
  213. int
  214. vc4_irq_postinstall(struct drm_device *dev)
  215. {
  216. struct vc4_dev *vc4 = to_vc4_dev(dev);
  217. if (!vc4->v3d)
  218. return 0;
  219. /* Enable the render done interrupts. The out-of-memory interrupt is
  220. * enabled as soon as we have a binner BO allocated.
  221. */
  222. V3D_WRITE(V3D_INTENA, V3D_INT_FLDONE | V3D_INT_FRDONE);
  223. return 0;
  224. }
  225. void
  226. vc4_irq_uninstall(struct drm_device *dev)
  227. {
  228. struct vc4_dev *vc4 = to_vc4_dev(dev);
  229. if (!vc4->v3d)
  230. return;
  231. /* Disable sending interrupts for our driver's IRQs. */
  232. V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
  233. /* Clear any pending interrupts we might have left. */
  234. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  235. /* Finish any interrupt handler still in flight. */
  236. disable_irq(dev->irq);
  237. cancel_work_sync(&vc4->overflow_mem_work);
  238. }
  239. /** Reinitializes interrupt registers when a GPU reset is performed. */
  240. void vc4_irq_reset(struct drm_device *dev)
  241. {
  242. struct vc4_dev *vc4 = to_vc4_dev(dev);
  243. unsigned long irqflags;
  244. /* Acknowledge any stale IRQs. */
  245. V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
  246. /*
  247. * Turn all our interrupts on. Binner out of memory is the
  248. * only one we expect to trigger at this point, since we've
  249. * just come from poweron and haven't supplied any overflow
  250. * memory yet.
  251. */
  252. V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
  253. spin_lock_irqsave(&vc4->job_lock, irqflags);
  254. vc4_cancel_bin_job(dev);
  255. vc4_irq_finish_render_job(dev);
  256. spin_unlock_irqrestore(&vc4->job_lock, irqflags);
  257. }