vc4_hvs.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Broadcom
  4. */
  5. /**
  6. * DOC: VC4 HVS module.
  7. *
  8. * The Hardware Video Scaler (HVS) is the piece of hardware that does
  9. * translation, scaling, colorspace conversion, and compositing of
  10. * pixels stored in framebuffers into a FIFO of pixels going out to
  11. * the Pixel Valve (CRTC). It operates at the system clock rate (the
  12. * system audio clock gate, specifically), which is much higher than
  13. * the pixel clock rate.
  14. *
  15. * There is a single global HVS, with multiple output FIFOs that can
  16. * be consumed by the PVs. This file just manages the resources for
  17. * the HVS, while the vc4_crtc.c code actually drives HVS setup for
  18. * each CRTC.
  19. */
  20. #include <linux/bitfield.h>
  21. #include <linux/clk.h>
  22. #include <linux/component.h>
  23. #include <linux/platform_device.h>
  24. #include <drm/drm_atomic_helper.h>
  25. #include <drm/drm_vblank.h>
  26. #include "vc4_drv.h"
  27. #include "vc4_regs.h"
  28. static const struct debugfs_reg32 hvs_regs[] = {
  29. VC4_REG32(SCALER_DISPCTRL),
  30. VC4_REG32(SCALER_DISPSTAT),
  31. VC4_REG32(SCALER_DISPID),
  32. VC4_REG32(SCALER_DISPECTRL),
  33. VC4_REG32(SCALER_DISPPROF),
  34. VC4_REG32(SCALER_DISPDITHER),
  35. VC4_REG32(SCALER_DISPEOLN),
  36. VC4_REG32(SCALER_DISPLIST0),
  37. VC4_REG32(SCALER_DISPLIST1),
  38. VC4_REG32(SCALER_DISPLIST2),
  39. VC4_REG32(SCALER_DISPLSTAT),
  40. VC4_REG32(SCALER_DISPLACT0),
  41. VC4_REG32(SCALER_DISPLACT1),
  42. VC4_REG32(SCALER_DISPLACT2),
  43. VC4_REG32(SCALER_DISPCTRL0),
  44. VC4_REG32(SCALER_DISPBKGND0),
  45. VC4_REG32(SCALER_DISPSTAT0),
  46. VC4_REG32(SCALER_DISPBASE0),
  47. VC4_REG32(SCALER_DISPCTRL1),
  48. VC4_REG32(SCALER_DISPBKGND1),
  49. VC4_REG32(SCALER_DISPSTAT1),
  50. VC4_REG32(SCALER_DISPBASE1),
  51. VC4_REG32(SCALER_DISPCTRL2),
  52. VC4_REG32(SCALER_DISPBKGND2),
  53. VC4_REG32(SCALER_DISPSTAT2),
  54. VC4_REG32(SCALER_DISPBASE2),
  55. VC4_REG32(SCALER_DISPALPHA2),
  56. VC4_REG32(SCALER_OLEDOFFS),
  57. VC4_REG32(SCALER_OLEDCOEF0),
  58. VC4_REG32(SCALER_OLEDCOEF1),
  59. VC4_REG32(SCALER_OLEDCOEF2),
  60. };
  61. void vc4_hvs_dump_state(struct drm_device *dev)
  62. {
  63. struct vc4_dev *vc4 = to_vc4_dev(dev);
  64. struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
  65. int i;
  66. drm_print_regset32(&p, &vc4->hvs->regset);
  67. DRM_INFO("HVS ctx:\n");
  68. for (i = 0; i < 64; i += 4) {
  69. DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
  70. i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
  71. readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
  72. readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
  73. readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
  74. readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
  75. }
  76. }
  77. static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
  78. {
  79. struct drm_info_node *node = m->private;
  80. struct drm_device *dev = node->minor->dev;
  81. struct vc4_dev *vc4 = to_vc4_dev(dev);
  82. struct drm_printer p = drm_seq_file_printer(m);
  83. drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
  84. return 0;
  85. }
  86. /* The filter kernel is composed of dwords each containing 3 9-bit
  87. * signed integers packed next to each other.
  88. */
  89. #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
  90. #define VC4_PPF_FILTER_WORD(c0, c1, c2) \
  91. ((((c0) & 0x1ff) << 0) | \
  92. (((c1) & 0x1ff) << 9) | \
  93. (((c2) & 0x1ff) << 18))
  94. /* The whole filter kernel is arranged as the coefficients 0-16 going
  95. * up, then a pad, then 17-31 going down and reversed within the
  96. * dwords. This means that a linear phase kernel (where it's
  97. * symmetrical at the boundary between 15 and 16) has the last 5
  98. * dwords matching the first 5, but reversed.
  99. */
  100. #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \
  101. c9, c10, c11, c12, c13, c14, c15) \
  102. {VC4_PPF_FILTER_WORD(c0, c1, c2), \
  103. VC4_PPF_FILTER_WORD(c3, c4, c5), \
  104. VC4_PPF_FILTER_WORD(c6, c7, c8), \
  105. VC4_PPF_FILTER_WORD(c9, c10, c11), \
  106. VC4_PPF_FILTER_WORD(c12, c13, c14), \
  107. VC4_PPF_FILTER_WORD(c15, c15, 0)}
  108. #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
  109. #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
  110. /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
  111. * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
  112. */
  113. static const u32 mitchell_netravali_1_3_1_3_kernel[] =
  114. VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
  115. 50, 82, 119, 155, 187, 213, 227);
  116. static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
  117. struct drm_mm_node *space,
  118. const u32 *kernel)
  119. {
  120. int ret, i;
  121. u32 __iomem *dst_kernel;
  122. ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
  123. if (ret) {
  124. DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
  125. ret);
  126. return ret;
  127. }
  128. dst_kernel = hvs->dlist + space->start;
  129. for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
  130. if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
  131. writel(kernel[i], &dst_kernel[i]);
  132. else {
  133. writel(kernel[VC4_KERNEL_DWORDS - i - 1],
  134. &dst_kernel[i]);
  135. }
  136. }
  137. return 0;
  138. }
  139. static void vc4_hvs_lut_load(struct drm_crtc *crtc)
  140. {
  141. struct drm_device *dev = crtc->dev;
  142. struct vc4_dev *vc4 = to_vc4_dev(dev);
  143. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  144. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
  145. u32 i;
  146. /* The LUT memory is laid out with each HVS channel in order,
  147. * each of which takes 256 writes for R, 256 for G, then 256
  148. * for B.
  149. */
  150. HVS_WRITE(SCALER_GAMADDR,
  151. SCALER_GAMADDR_AUTOINC |
  152. (vc4_state->assigned_channel * 3 * crtc->gamma_size));
  153. for (i = 0; i < crtc->gamma_size; i++)
  154. HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
  155. for (i = 0; i < crtc->gamma_size; i++)
  156. HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
  157. for (i = 0; i < crtc->gamma_size; i++)
  158. HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
  159. }
  160. static void vc4_hvs_update_gamma_lut(struct drm_crtc *crtc)
  161. {
  162. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  163. struct drm_color_lut *lut = crtc->state->gamma_lut->data;
  164. u32 length = drm_color_lut_size(crtc->state->gamma_lut);
  165. u32 i;
  166. for (i = 0; i < length; i++) {
  167. vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
  168. vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
  169. vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
  170. }
  171. vc4_hvs_lut_load(crtc);
  172. }
  173. int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output)
  174. {
  175. struct vc4_dev *vc4 = to_vc4_dev(dev);
  176. u32 reg;
  177. int ret;
  178. if (!vc4->hvs->hvs5)
  179. return output;
  180. switch (output) {
  181. case 0:
  182. return 0;
  183. case 1:
  184. return 1;
  185. case 2:
  186. reg = HVS_READ(SCALER_DISPECTRL);
  187. ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
  188. if (ret == 0)
  189. return 2;
  190. return 0;
  191. case 3:
  192. reg = HVS_READ(SCALER_DISPCTRL);
  193. ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
  194. if (ret == 3)
  195. return -EPIPE;
  196. return ret;
  197. case 4:
  198. reg = HVS_READ(SCALER_DISPEOLN);
  199. ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
  200. if (ret == 3)
  201. return -EPIPE;
  202. return ret;
  203. case 5:
  204. reg = HVS_READ(SCALER_DISPDITHER);
  205. ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
  206. if (ret == 3)
  207. return -EPIPE;
  208. return ret;
  209. default:
  210. return -EPIPE;
  211. }
  212. }
  213. static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
  214. struct drm_display_mode *mode, bool oneshot)
  215. {
  216. struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  217. unsigned int chan = vc4_crtc_state->assigned_channel;
  218. bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
  219. u32 dispbkgndx;
  220. u32 dispctrl;
  221. HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
  222. HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
  223. HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
  224. /* Turn on the scaler, which will wait for vstart to start
  225. * compositing.
  226. * When feeding the transposer, we should operate in oneshot
  227. * mode.
  228. */
  229. dispctrl = SCALER_DISPCTRLX_ENABLE;
  230. if (!vc4->hvs->hvs5)
  231. dispctrl |= VC4_SET_FIELD(mode->hdisplay,
  232. SCALER_DISPCTRLX_WIDTH) |
  233. VC4_SET_FIELD(mode->vdisplay,
  234. SCALER_DISPCTRLX_HEIGHT) |
  235. (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
  236. else
  237. dispctrl |= VC4_SET_FIELD(mode->hdisplay,
  238. SCALER5_DISPCTRLX_WIDTH) |
  239. VC4_SET_FIELD(mode->vdisplay,
  240. SCALER5_DISPCTRLX_HEIGHT) |
  241. (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
  242. HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl);
  243. dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
  244. dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
  245. dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE;
  246. HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx |
  247. SCALER_DISPBKGND_AUTOHS |
  248. ((!vc4->hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) |
  249. (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
  250. /* Reload the LUT, since the SRAMs would have been disabled if
  251. * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
  252. */
  253. vc4_hvs_lut_load(crtc);
  254. return 0;
  255. }
  256. void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
  257. {
  258. struct vc4_dev *vc4 = to_vc4_dev(dev);
  259. if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)
  260. return;
  261. HVS_WRITE(SCALER_DISPCTRLX(chan),
  262. HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET);
  263. HVS_WRITE(SCALER_DISPCTRLX(chan),
  264. HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE);
  265. /* Once we leave, the scaler should be disabled and its fifo empty. */
  266. WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
  267. WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
  268. SCALER_DISPSTATX_MODE) !=
  269. SCALER_DISPSTATX_MODE_DISABLED);
  270. WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
  271. (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
  272. SCALER_DISPSTATX_EMPTY);
  273. }
  274. int vc4_hvs_atomic_check(struct drm_crtc *crtc,
  275. struct drm_crtc_state *state)
  276. {
  277. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
  278. struct drm_device *dev = crtc->dev;
  279. struct vc4_dev *vc4 = to_vc4_dev(dev);
  280. struct drm_plane *plane;
  281. unsigned long flags;
  282. const struct drm_plane_state *plane_state;
  283. u32 dlist_count = 0;
  284. int ret;
  285. /* The pixelvalve can only feed one encoder (and encoders are
  286. * 1:1 with connectors.)
  287. */
  288. if (hweight32(state->connector_mask) > 1)
  289. return -EINVAL;
  290. drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
  291. dlist_count += vc4_plane_dlist_size(plane_state);
  292. dlist_count++; /* Account for SCALER_CTL0_END. */
  293. spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
  294. ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
  295. dlist_count);
  296. spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
  297. if (ret)
  298. return ret;
  299. return 0;
  300. }
  301. static void vc4_hvs_update_dlist(struct drm_crtc *crtc)
  302. {
  303. struct drm_device *dev = crtc->dev;
  304. struct vc4_dev *vc4 = to_vc4_dev(dev);
  305. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  306. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
  307. if (crtc->state->event) {
  308. unsigned long flags;
  309. crtc->state->event->pipe = drm_crtc_index(crtc);
  310. WARN_ON(drm_crtc_vblank_get(crtc) != 0);
  311. spin_lock_irqsave(&dev->event_lock, flags);
  312. if (!vc4_state->feed_txp || vc4_state->txp_armed) {
  313. vc4_crtc->event = crtc->state->event;
  314. crtc->state->event = NULL;
  315. }
  316. HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
  317. vc4_state->mm.start);
  318. spin_unlock_irqrestore(&dev->event_lock, flags);
  319. } else {
  320. HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel),
  321. vc4_state->mm.start);
  322. }
  323. }
  324. void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
  325. struct drm_crtc_state *old_state)
  326. {
  327. struct drm_device *dev = crtc->dev;
  328. struct vc4_dev *vc4 = to_vc4_dev(dev);
  329. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
  330. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  331. bool oneshot = vc4_state->feed_txp;
  332. vc4_hvs_update_dlist(crtc);
  333. vc4_hvs_init_channel(vc4, crtc, mode, oneshot);
  334. }
  335. void vc4_hvs_atomic_disable(struct drm_crtc *crtc,
  336. struct drm_crtc_state *old_state)
  337. {
  338. struct drm_device *dev = crtc->dev;
  339. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);
  340. unsigned int chan = vc4_state->assigned_channel;
  341. vc4_hvs_stop_channel(dev, chan);
  342. }
  343. void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
  344. struct drm_crtc_state *old_state)
  345. {
  346. struct drm_device *dev = crtc->dev;
  347. struct vc4_dev *vc4 = to_vc4_dev(dev);
  348. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
  349. struct drm_plane *plane;
  350. struct vc4_plane_state *vc4_plane_state;
  351. bool debug_dump_regs = false;
  352. bool enable_bg_fill = false;
  353. u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
  354. u32 __iomem *dlist_next = dlist_start;
  355. if (debug_dump_regs) {
  356. DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
  357. vc4_hvs_dump_state(dev);
  358. }
  359. /* Copy all the active planes' dlist contents to the hardware dlist. */
  360. drm_atomic_crtc_for_each_plane(plane, crtc) {
  361. /* Is this the first active plane? */
  362. if (dlist_next == dlist_start) {
  363. /* We need to enable background fill when a plane
  364. * could be alpha blending from the background, i.e.
  365. * where no other plane is underneath. It suffices to
  366. * consider the first active plane here since we set
  367. * needs_bg_fill such that either the first plane
  368. * already needs it or all planes on top blend from
  369. * the first or a lower plane.
  370. */
  371. vc4_plane_state = to_vc4_plane_state(plane->state);
  372. enable_bg_fill = vc4_plane_state->needs_bg_fill;
  373. }
  374. dlist_next += vc4_plane_write_dlist(plane, dlist_next);
  375. }
  376. writel(SCALER_CTL0_END, dlist_next);
  377. dlist_next++;
  378. WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
  379. if (enable_bg_fill)
  380. /* This sets a black background color fill, as is the case
  381. * with other DRM drivers.
  382. */
  383. HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel),
  384. HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel)) |
  385. SCALER_DISPBKGND_FILL);
  386. /* Only update DISPLIST if the CRTC was already running and is not
  387. * being disabled.
  388. * vc4_crtc_enable() takes care of updating the dlist just after
  389. * re-enabling VBLANK interrupts and before enabling the engine.
  390. * If the CRTC is being disabled, there's no point in updating this
  391. * information.
  392. */
  393. if (crtc->state->active && old_state->active)
  394. vc4_hvs_update_dlist(crtc);
  395. if (crtc->state->color_mgmt_changed) {
  396. u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_state->assigned_channel));
  397. if (crtc->state->gamma_lut) {
  398. vc4_hvs_update_gamma_lut(crtc);
  399. dispbkgndx |= SCALER_DISPBKGND_GAMMA;
  400. } else {
  401. /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
  402. * in hardware, which is the same as a linear lut that
  403. * DRM expects us to use in absence of a user lut.
  404. */
  405. dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
  406. }
  407. HVS_WRITE(SCALER_DISPBKGNDX(vc4_state->assigned_channel), dispbkgndx);
  408. }
  409. if (debug_dump_regs) {
  410. DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
  411. vc4_hvs_dump_state(dev);
  412. }
  413. }
  414. void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
  415. {
  416. struct vc4_dev *vc4 = to_vc4_dev(dev);
  417. u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
  418. dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
  419. HVS_WRITE(SCALER_DISPCTRL, dispctrl);
  420. }
  421. void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
  422. {
  423. struct vc4_dev *vc4 = to_vc4_dev(dev);
  424. u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
  425. dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
  426. HVS_WRITE(SCALER_DISPSTAT,
  427. SCALER_DISPSTAT_EUFLOW(channel));
  428. HVS_WRITE(SCALER_DISPCTRL, dispctrl);
  429. }
  430. static void vc4_hvs_report_underrun(struct drm_device *dev)
  431. {
  432. struct vc4_dev *vc4 = to_vc4_dev(dev);
  433. atomic_inc(&vc4->underrun);
  434. DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
  435. }
  436. static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
  437. {
  438. struct drm_device *dev = data;
  439. struct vc4_dev *vc4 = to_vc4_dev(dev);
  440. irqreturn_t irqret = IRQ_NONE;
  441. int channel;
  442. u32 control;
  443. u32 status;
  444. status = HVS_READ(SCALER_DISPSTAT);
  445. control = HVS_READ(SCALER_DISPCTRL);
  446. for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
  447. /* Interrupt masking is not always honored, so check it here. */
  448. if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
  449. control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
  450. vc4_hvs_mask_underrun(dev, channel);
  451. vc4_hvs_report_underrun(dev);
  452. irqret = IRQ_HANDLED;
  453. }
  454. }
  455. /* Clear every per-channel interrupt flag. */
  456. HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
  457. SCALER_DISPSTAT_IRQMASK(1) |
  458. SCALER_DISPSTAT_IRQMASK(2));
  459. return irqret;
  460. }
  461. static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
  462. {
  463. struct platform_device *pdev = to_platform_device(dev);
  464. struct drm_device *drm = dev_get_drvdata(master);
  465. struct vc4_dev *vc4 = to_vc4_dev(drm);
  466. struct vc4_hvs *hvs = NULL;
  467. int ret;
  468. u32 dispctrl;
  469. hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
  470. if (!hvs)
  471. return -ENOMEM;
  472. hvs->pdev = pdev;
  473. if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
  474. hvs->hvs5 = true;
  475. hvs->regs = vc4_ioremap_regs(pdev, 0);
  476. if (IS_ERR(hvs->regs))
  477. return PTR_ERR(hvs->regs);
  478. hvs->regset.base = hvs->regs;
  479. hvs->regset.regs = hvs_regs;
  480. hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
  481. if (hvs->hvs5) {
  482. hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
  483. if (IS_ERR(hvs->core_clk)) {
  484. dev_err(&pdev->dev, "Couldn't get core clock\n");
  485. return PTR_ERR(hvs->core_clk);
  486. }
  487. ret = clk_prepare_enable(hvs->core_clk);
  488. if (ret) {
  489. dev_err(&pdev->dev, "Couldn't enable the core clock\n");
  490. return ret;
  491. }
  492. }
  493. if (!hvs->hvs5)
  494. hvs->dlist = hvs->regs + SCALER_DLIST_START;
  495. else
  496. hvs->dlist = hvs->regs + SCALER5_DLIST_START;
  497. spin_lock_init(&hvs->mm_lock);
  498. /* Set up the HVS display list memory manager. We never
  499. * overwrite the setup from the bootloader (just 128b out of
  500. * our 16K), since we don't want to scramble the screen when
  501. * transitioning from the firmware's boot setup to runtime.
  502. */
  503. drm_mm_init(&hvs->dlist_mm,
  504. HVS_BOOTLOADER_DLIST_END,
  505. (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
  506. /* Set up the HVS LBM memory manager. We could have some more
  507. * complicated data structure that allowed reuse of LBM areas
  508. * between planes when they don't overlap on the screen, but
  509. * for now we just allocate globally.
  510. */
  511. if (!hvs->hvs5)
  512. /* 48k words of 2x12-bit pixels */
  513. drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
  514. else
  515. /* 60k words of 4x12-bit pixels */
  516. drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
  517. /* Upload filter kernels. We only have the one for now, so we
  518. * keep it around for the lifetime of the driver.
  519. */
  520. ret = vc4_hvs_upload_linear_kernel(hvs,
  521. &hvs->mitchell_netravali_filter,
  522. mitchell_netravali_1_3_1_3_kernel);
  523. if (ret)
  524. return ret;
  525. vc4->hvs = hvs;
  526. dispctrl = HVS_READ(SCALER_DISPCTRL);
  527. dispctrl |= SCALER_DISPCTRL_ENABLE;
  528. dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
  529. SCALER_DISPCTRL_DISPEIRQ(1) |
  530. SCALER_DISPCTRL_DISPEIRQ(2);
  531. /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
  532. * be unused.
  533. */
  534. dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
  535. dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
  536. SCALER_DISPCTRL_SLVWREIRQ |
  537. SCALER_DISPCTRL_SLVRDEIRQ |
  538. SCALER_DISPCTRL_DSPEIEOF(0) |
  539. SCALER_DISPCTRL_DSPEIEOF(1) |
  540. SCALER_DISPCTRL_DSPEIEOF(2) |
  541. SCALER_DISPCTRL_DSPEIEOLN(0) |
  542. SCALER_DISPCTRL_DSPEIEOLN(1) |
  543. SCALER_DISPCTRL_DSPEIEOLN(2) |
  544. SCALER_DISPCTRL_DSPEISLUR(0) |
  545. SCALER_DISPCTRL_DSPEISLUR(1) |
  546. SCALER_DISPCTRL_DSPEISLUR(2) |
  547. SCALER_DISPCTRL_SCLEIRQ);
  548. dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
  549. HVS_WRITE(SCALER_DISPCTRL, dispctrl);
  550. ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
  551. vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
  552. if (ret)
  553. return ret;
  554. vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset);
  555. vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun,
  556. NULL);
  557. return 0;
  558. }
  559. static void vc4_hvs_unbind(struct device *dev, struct device *master,
  560. void *data)
  561. {
  562. struct drm_device *drm = dev_get_drvdata(master);
  563. struct vc4_dev *vc4 = to_vc4_dev(drm);
  564. struct vc4_hvs *hvs = vc4->hvs;
  565. if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter))
  566. drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
  567. drm_mm_takedown(&vc4->hvs->dlist_mm);
  568. drm_mm_takedown(&vc4->hvs->lbm_mm);
  569. clk_disable_unprepare(hvs->core_clk);
  570. vc4->hvs = NULL;
  571. }
  572. static const struct component_ops vc4_hvs_ops = {
  573. .bind = vc4_hvs_bind,
  574. .unbind = vc4_hvs_unbind,
  575. };
  576. static int vc4_hvs_dev_probe(struct platform_device *pdev)
  577. {
  578. return component_add(&pdev->dev, &vc4_hvs_ops);
  579. }
  580. static int vc4_hvs_dev_remove(struct platform_device *pdev)
  581. {
  582. component_del(&pdev->dev, &vc4_hvs_ops);
  583. return 0;
  584. }
  585. static const struct of_device_id vc4_hvs_dt_match[] = {
  586. { .compatible = "brcm,bcm2711-hvs" },
  587. { .compatible = "brcm,bcm2835-hvs" },
  588. {}
  589. };
  590. struct platform_driver vc4_hvs_driver = {
  591. .probe = vc4_hvs_dev_probe,
  592. .remove = vc4_hvs_dev_remove,
  593. .driver = {
  594. .name = "vc4_hvs",
  595. .of_match_table = vc4_hvs_dt_match,
  596. },
  597. };