vc4_hdmi_regs.h 12 KB

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  1. #ifndef _VC4_HDMI_REGS_H_
  2. #define _VC4_HDMI_REGS_H_
  3. #include "vc4_hdmi.h"
  4. #define VC4_HDMI_PACKET_STRIDE 0x24
  5. enum vc4_hdmi_regs {
  6. VC4_INVALID = 0,
  7. VC4_HDMI,
  8. VC4_HD,
  9. VC5_CEC,
  10. VC5_CSC,
  11. VC5_DVP,
  12. VC5_PHY,
  13. VC5_RAM,
  14. VC5_RM,
  15. };
  16. enum vc4_hdmi_field {
  17. HDMI_AUDIO_PACKET_CONFIG,
  18. HDMI_CEC_CNTRL_1,
  19. HDMI_CEC_CNTRL_2,
  20. HDMI_CEC_CNTRL_3,
  21. HDMI_CEC_CNTRL_4,
  22. HDMI_CEC_CNTRL_5,
  23. HDMI_CEC_CPU_CLEAR,
  24. HDMI_CEC_CPU_MASK_CLEAR,
  25. HDMI_CEC_CPU_MASK_SET,
  26. HDMI_CEC_CPU_MASK_STATUS,
  27. HDMI_CEC_CPU_STATUS,
  28. HDMI_CEC_CPU_SET,
  29. /*
  30. * Transmit data, first byte is low byte of the 32-bit reg.
  31. * MSB of each byte transmitted first.
  32. */
  33. HDMI_CEC_RX_DATA_1,
  34. HDMI_CEC_RX_DATA_2,
  35. HDMI_CEC_RX_DATA_3,
  36. HDMI_CEC_RX_DATA_4,
  37. HDMI_CEC_TX_DATA_1,
  38. HDMI_CEC_TX_DATA_2,
  39. HDMI_CEC_TX_DATA_3,
  40. HDMI_CEC_TX_DATA_4,
  41. HDMI_CLOCK_STOP,
  42. HDMI_CORE_REV,
  43. HDMI_CRP_CFG,
  44. HDMI_CSC_12_11,
  45. HDMI_CSC_14_13,
  46. HDMI_CSC_22_21,
  47. HDMI_CSC_24_23,
  48. HDMI_CSC_32_31,
  49. HDMI_CSC_34_33,
  50. HDMI_CSC_CTL,
  51. /*
  52. * 20-bit fields containing CTS values to be transmitted if
  53. * !EXTERNAL_CTS_EN
  54. */
  55. HDMI_CTS_0,
  56. HDMI_CTS_1,
  57. HDMI_DVP_CTL,
  58. HDMI_FIFO_CTL,
  59. HDMI_FRAME_COUNT,
  60. HDMI_HORZA,
  61. HDMI_HORZB,
  62. HDMI_HOTPLUG,
  63. HDMI_HOTPLUG_INT,
  64. /*
  65. * 3 bits per field, where each field maps from that
  66. * corresponding MAI bus channel to the given HDMI channel.
  67. */
  68. HDMI_MAI_CHANNEL_MAP,
  69. HDMI_MAI_CONFIG,
  70. HDMI_MAI_CTL,
  71. /*
  72. * Register for DMAing in audio data to be transported over
  73. * the MAI bus to the Falcon core.
  74. */
  75. HDMI_MAI_DATA,
  76. /* Format header to be placed on the MAI data. Unused. */
  77. HDMI_MAI_FMT,
  78. /* Last received format word on the MAI bus. */
  79. HDMI_MAI_FORMAT,
  80. HDMI_MAI_SMP,
  81. HDMI_MAI_THR,
  82. HDMI_M_CTL,
  83. HDMI_RAM_PACKET_CONFIG,
  84. HDMI_RAM_PACKET_START,
  85. HDMI_RAM_PACKET_STATUS,
  86. HDMI_RM_CONTROL,
  87. HDMI_RM_FORMAT,
  88. HDMI_RM_OFFSET,
  89. HDMI_SCHEDULER_CONTROL,
  90. HDMI_SW_RESET_CONTROL,
  91. HDMI_TX_PHY_CHANNEL_SWAP,
  92. HDMI_TX_PHY_CLK_DIV,
  93. HDMI_TX_PHY_CTL_0,
  94. HDMI_TX_PHY_CTL_1,
  95. HDMI_TX_PHY_CTL_2,
  96. HDMI_TX_PHY_CTL_3,
  97. HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
  98. HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
  99. HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
  100. HDMI_TX_PHY_PLL_CFG,
  101. HDMI_TX_PHY_PLL_CTL_0,
  102. HDMI_TX_PHY_PLL_CTL_1,
  103. HDMI_TX_PHY_POWERDOWN_CTL,
  104. HDMI_TX_PHY_RESET_CTL,
  105. HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
  106. HDMI_VEC_INTERFACE_XBAR,
  107. HDMI_VERTA0,
  108. HDMI_VERTA1,
  109. HDMI_VERTB0,
  110. HDMI_VERTB1,
  111. HDMI_VID_CTL,
  112. };
  113. struct vc4_hdmi_register {
  114. char *name;
  115. enum vc4_hdmi_regs reg;
  116. unsigned int offset;
  117. };
  118. #define _VC4_REG(_base, _reg, _offset) \
  119. [_reg] = { \
  120. .name = #_reg, \
  121. .reg = _base, \
  122. .offset = _offset, \
  123. }
  124. #define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset)
  125. #define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset)
  126. #define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset)
  127. #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset)
  128. #define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset)
  129. #define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset)
  130. #define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset)
  131. #define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset)
  132. static const struct vc4_hdmi_register vc4_hdmi_fields[] = {
  133. VC4_HD_REG(HDMI_M_CTL, 0x000c),
  134. VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
  135. VC4_HD_REG(HDMI_MAI_THR, 0x0018),
  136. VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
  137. VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
  138. VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
  139. VC4_HD_REG(HDMI_VID_CTL, 0x0038),
  140. VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
  141. VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
  142. VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
  143. VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
  144. VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
  145. VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
  146. VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
  147. VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
  148. VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
  149. VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
  150. VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
  151. VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
  152. VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
  153. VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
  154. VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
  155. VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
  156. VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
  157. VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
  158. VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
  159. VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
  160. VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
  161. VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
  162. VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
  163. VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
  164. VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
  165. VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
  166. VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
  167. VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
  168. VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
  169. VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
  170. VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
  171. VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
  172. VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
  173. VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
  174. VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
  175. VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
  176. VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
  177. VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
  178. VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
  179. VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
  180. VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
  181. VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
  182. VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
  183. VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
  184. VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
  185. VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
  186. VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
  187. VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
  188. VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
  189. VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
  190. VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
  191. };
  192. static const struct vc4_hdmi_register vc5_hdmi_hdmi0_fields[] = {
  193. VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
  194. VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
  195. VC4_HD_REG(HDMI_MAI_THR, 0x0014),
  196. VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
  197. VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
  198. VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
  199. VC4_HD_REG(HDMI_VID_CTL, 0x0044),
  200. VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
  201. VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
  202. VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
  203. VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
  204. VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
  205. VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
  206. VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
  207. VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
  208. VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
  209. VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
  210. VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
  211. VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
  212. VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
  213. VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
  214. VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
  215. VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
  216. VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
  217. VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
  218. VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
  219. VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
  220. VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
  221. VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
  222. VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
  223. VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
  224. VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
  225. VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
  226. VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
  227. VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
  228. VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
  229. VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
  230. VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
  231. VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
  232. VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
  233. VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
  234. VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
  235. VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
  236. VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
  237. VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
  238. VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
  239. VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
  240. VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
  241. VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
  242. VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
  243. VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
  244. VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
  245. VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
  246. VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
  247. VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
  248. VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
  249. VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
  250. VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
  251. VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
  252. VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
  253. VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
  254. VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
  255. VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
  256. VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
  257. VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
  258. VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
  259. };
  260. static const struct vc4_hdmi_register vc5_hdmi_hdmi1_fields[] = {
  261. VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
  262. VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
  263. VC4_HD_REG(HDMI_MAI_THR, 0x0034),
  264. VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
  265. VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
  266. VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
  267. VC4_HD_REG(HDMI_VID_CTL, 0x0048),
  268. VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
  269. VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
  270. VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
  271. VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
  272. VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
  273. VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
  274. VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
  275. VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
  276. VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
  277. VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
  278. VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
  279. VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
  280. VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
  281. VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
  282. VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
  283. VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
  284. VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
  285. VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
  286. VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
  287. VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
  288. VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
  289. VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
  290. VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
  291. VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
  292. VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
  293. VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
  294. VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
  295. VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
  296. VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
  297. VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
  298. VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
  299. VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
  300. VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
  301. VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
  302. VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
  303. VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
  304. VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
  305. VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
  306. VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
  307. VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
  308. VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
  309. VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
  310. VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
  311. VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
  312. VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
  313. VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
  314. VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
  315. VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
  316. VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
  317. VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
  318. VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
  319. VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
  320. VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
  321. VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
  322. VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
  323. VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
  324. VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
  325. VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
  326. VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
  327. };
  328. static inline
  329. void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
  330. enum vc4_hdmi_regs reg)
  331. {
  332. switch (reg) {
  333. case VC4_HD:
  334. return hdmi->hd_regs;
  335. case VC4_HDMI:
  336. return hdmi->hdmicore_regs;
  337. case VC5_CSC:
  338. return hdmi->csc_regs;
  339. case VC5_CEC:
  340. return hdmi->cec_regs;
  341. case VC5_DVP:
  342. return hdmi->dvp_regs;
  343. case VC5_PHY:
  344. return hdmi->phy_regs;
  345. case VC5_RAM:
  346. return hdmi->ram_regs;
  347. case VC5_RM:
  348. return hdmi->rm_regs;
  349. default:
  350. return NULL;
  351. }
  352. return NULL;
  353. }
  354. static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
  355. enum vc4_hdmi_field reg)
  356. {
  357. const struct vc4_hdmi_register *field;
  358. const struct vc4_hdmi_variant *variant = hdmi->variant;
  359. void __iomem *base;
  360. if (reg >= variant->num_registers) {
  361. dev_warn(&hdmi->pdev->dev,
  362. "Invalid register ID %u\n", reg);
  363. return 0;
  364. }
  365. field = &variant->registers[reg];
  366. base = __vc4_hdmi_get_field_base(hdmi, field->reg);
  367. if (!base) {
  368. dev_warn(&hdmi->pdev->dev,
  369. "Unknown register ID %u\n", reg);
  370. return 0;
  371. }
  372. return readl(base + field->offset);
  373. }
  374. #define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg)
  375. static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
  376. enum vc4_hdmi_field reg,
  377. u32 value)
  378. {
  379. const struct vc4_hdmi_register *field;
  380. const struct vc4_hdmi_variant *variant = hdmi->variant;
  381. void __iomem *base;
  382. if (reg >= variant->num_registers) {
  383. dev_warn(&hdmi->pdev->dev,
  384. "Invalid register ID %u\n", reg);
  385. return;
  386. }
  387. field = &variant->registers[reg];
  388. base = __vc4_hdmi_get_field_base(hdmi, field->reg);
  389. if (!base)
  390. return;
  391. writel(value, base + field->offset);
  392. }
  393. #define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val)
  394. #endif /* _VC4_HDMI_REGS_H_ */