vc4_hdmi_phy.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2015 Broadcom
  4. * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  5. * Copyright (C) 2013 Red Hat
  6. * Author: Rob Clark <robdclark@gmail.com>
  7. */
  8. #include "vc4_hdmi.h"
  9. #include "vc4_regs.h"
  10. #include "vc4_hdmi_regs.h"
  11. #define VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB BIT(5)
  12. #define VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB BIT(4)
  13. #define VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET BIT(3)
  14. #define VC4_HDMI_TX_PHY_RESET_CTL_TX_2_RESET BIT(2)
  15. #define VC4_HDMI_TX_PHY_RESET_CTL_TX_1_RESET BIT(1)
  16. #define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET BIT(0)
  17. #define VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN BIT(4)
  18. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_SHIFT 29
  19. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK VC4_MASK(31, 29)
  20. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_SHIFT 24
  21. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK VC4_MASK(28, 24)
  22. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_SHIFT 21
  23. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK VC4_MASK(23, 21)
  24. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_SHIFT 16
  25. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK VC4_MASK(20, 16)
  26. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_SHIFT 13
  27. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK VC4_MASK(15, 13)
  28. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_SHIFT 8
  29. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK VC4_MASK(12, 8)
  30. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_SHIFT 5
  31. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK VC4_MASK(7, 5)
  32. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT 0
  33. #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)
  34. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_SHIFT 15
  35. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK VC4_MASK(19, 15)
  36. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_SHIFT 10
  37. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK VC4_MASK(14, 10)
  38. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_SHIFT 5
  39. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_MASK VC4_MASK(9, 5)
  40. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT 0
  41. #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)
  42. #define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_SHIFT 16
  43. #define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_MASK VC4_MASK(19, 16)
  44. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_SHIFT 12
  45. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_MASK VC4_MASK(15, 12)
  46. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_SHIFT 8
  47. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_MASK VC4_MASK(11, 8)
  48. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_SHIFT 4
  49. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_MASK VC4_MASK(7, 4)
  50. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT 0
  51. #define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK VC4_MASK(3, 0)
  52. #define VC4_HDMI_TX_PHY_CTL_3_RP_SHIFT 17
  53. #define VC4_HDMI_TX_PHY_CTL_3_RP_MASK VC4_MASK(19, 17)
  54. #define VC4_HDMI_TX_PHY_CTL_3_RZ_SHIFT 12
  55. #define VC4_HDMI_TX_PHY_CTL_3_RZ_MASK VC4_MASK(16, 12)
  56. #define VC4_HDMI_TX_PHY_CTL_3_CP1_SHIFT 10
  57. #define VC4_HDMI_TX_PHY_CTL_3_CP1_MASK VC4_MASK(11, 10)
  58. #define VC4_HDMI_TX_PHY_CTL_3_CP_SHIFT 8
  59. #define VC4_HDMI_TX_PHY_CTL_3_CP_MASK VC4_MASK(9, 8)
  60. #define VC4_HDMI_TX_PHY_CTL_3_CZ_SHIFT 6
  61. #define VC4_HDMI_TX_PHY_CTL_3_CZ_MASK VC4_MASK(7, 6)
  62. #define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT 0
  63. #define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK VC4_MASK(5, 0)
  64. #define VC4_HDMI_TX_PHY_PLL_CTL_0_MASH11_MODE BIT(13)
  65. #define VC4_HDMI_TX_PHY_PLL_CTL_0_VC_RANGE_EN BIT(12)
  66. #define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_LOW BIT(11)
  67. #define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_HIGH BIT(10)
  68. #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_SHIFT 9
  69. #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_MASK VC4_MASK(9, 9)
  70. #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_FB_DIV2 BIT(8)
  71. #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_POST_DIV2 BIT(7)
  72. #define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_CONT_EN BIT(6)
  73. #define VC4_HDMI_TX_PHY_PLL_CTL_0_ENA_VCO_CLK BIT(5)
  74. #define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_SHIFT 16
  75. #define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_MASK VC4_MASK(27, 16)
  76. #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_SHIFT 14
  77. #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_MASK VC4_MASK(15, 14)
  78. #define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_ENABLE BIT(13)
  79. #define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_SHIFT 11
  80. #define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_MASK VC4_MASK(12, 11)
  81. #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_SHIFT 8
  82. #define VC4_HDMI_TX_PHY_CLK_DIV_VCO_MASK VC4_MASK(15, 8)
  83. #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT 0
  84. #define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK VC4_MASK(3, 0)
  85. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_MASK VC4_MASK(13, 12)
  86. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_SHIFT 12
  87. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_MASK VC4_MASK(9, 8)
  88. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_SHIFT 8
  89. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_MASK VC4_MASK(5, 4)
  90. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_SHIFT 4
  91. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK VC4_MASK(1, 0)
  92. #define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_SHIFT 0
  93. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK VC4_MASK(27, 0)
  94. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_SHIFT 0
  95. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK VC4_MASK(27, 0)
  96. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_SHIFT 0
  97. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_MASK VC4_MASK(31, 16)
  98. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_SHIFT 16
  99. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK VC4_MASK(15, 0)
  100. #define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_SHIFT 0
  101. #define VC4_HDMI_RM_CONTROL_EN_FREEZE_COUNTERS BIT(19)
  102. #define VC4_HDMI_RM_CONTROL_EN_LOAD_INTEGRATOR BIT(17)
  103. #define VC4_HDMI_RM_CONTROL_FREE_RUN BIT(4)
  104. #define VC4_HDMI_RM_OFFSET_ONLY BIT(31)
  105. #define VC4_HDMI_RM_OFFSET_OFFSET_SHIFT 0
  106. #define VC4_HDMI_RM_OFFSET_OFFSET_MASK VC4_MASK(30, 0)
  107. #define VC4_HDMI_RM_FORMAT_SHIFT_SHIFT 24
  108. #define VC4_HDMI_RM_FORMAT_SHIFT_MASK VC4_MASK(25, 24)
  109. #define OSCILLATOR_FREQUENCY 54000000
  110. void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
  111. {
  112. /* PHY should be in reset, like
  113. * vc4_hdmi_encoder_disable() does.
  114. */
  115. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
  116. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
  117. }
  118. void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
  119. {
  120. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);
  121. }
  122. void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)
  123. {
  124. HDMI_WRITE(HDMI_TX_PHY_CTL_0,
  125. HDMI_READ(HDMI_TX_PHY_CTL_0) &
  126. ~VC4_HDMI_TX_PHY_RNG_PWRDN);
  127. }
  128. void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)
  129. {
  130. HDMI_WRITE(HDMI_TX_PHY_CTL_0,
  131. HDMI_READ(HDMI_TX_PHY_CTL_0) |
  132. VC4_HDMI_TX_PHY_RNG_PWRDN);
  133. }
  134. static unsigned long long
  135. phy_get_vco_freq(unsigned long long clock, u8 *vco_sel, u8 *vco_div)
  136. {
  137. unsigned long long vco_freq = clock;
  138. unsigned int _vco_div = 0;
  139. unsigned int _vco_sel = 0;
  140. while (vco_freq < 3000000000ULL) {
  141. _vco_div++;
  142. vco_freq = clock * _vco_div * 10;
  143. }
  144. if (vco_freq > 4500000000ULL)
  145. _vco_sel = 1;
  146. *vco_sel = _vco_sel;
  147. *vco_div = _vco_div;
  148. return vco_freq;
  149. }
  150. static u8 phy_get_cp_current(unsigned long vco_freq)
  151. {
  152. if (vco_freq < 3700000000ULL)
  153. return 0x1c;
  154. return 0x18;
  155. }
  156. static u32 phy_get_rm_offset(unsigned long long vco_freq)
  157. {
  158. unsigned long long fref = OSCILLATOR_FREQUENCY;
  159. u64 offset = 0;
  160. /* RM offset is stored as 9.22 format */
  161. offset = vco_freq * 2;
  162. offset = offset << 22;
  163. do_div(offset, fref);
  164. offset >>= 2;
  165. return offset;
  166. }
  167. static u8 phy_get_vco_gain(unsigned long long vco_freq)
  168. {
  169. if (vco_freq < 3350000000ULL)
  170. return 0xf;
  171. if (vco_freq < 3700000000ULL)
  172. return 0xc;
  173. if (vco_freq < 4050000000ULL)
  174. return 0x6;
  175. if (vco_freq < 4800000000ULL)
  176. return 0x5;
  177. if (vco_freq < 5200000000ULL)
  178. return 0x7;
  179. return 0x2;
  180. }
  181. struct phy_lane_settings {
  182. struct {
  183. u8 preemphasis;
  184. u8 main_driver;
  185. } amplitude;
  186. u8 res_sel_data;
  187. u8 term_res_sel_data;
  188. };
  189. struct phy_settings {
  190. unsigned long long min_rate;
  191. unsigned long long max_rate;
  192. struct phy_lane_settings channel[3];
  193. struct phy_lane_settings clock;
  194. };
  195. static const struct phy_settings vc5_hdmi_phy_settings[] = {
  196. {
  197. 0, 50000000,
  198. {
  199. {{0x0, 0x0A}, 0x12, 0x0},
  200. {{0x0, 0x0A}, 0x12, 0x0},
  201. {{0x0, 0x0A}, 0x12, 0x0}
  202. },
  203. {{0x0, 0x0A}, 0x18, 0x0},
  204. },
  205. {
  206. 50000001, 75000000,
  207. {
  208. {{0x0, 0x09}, 0x12, 0x0},
  209. {{0x0, 0x09}, 0x12, 0x0},
  210. {{0x0, 0x09}, 0x12, 0x0}
  211. },
  212. {{0x0, 0x0C}, 0x18, 0x3},
  213. },
  214. {
  215. 75000001, 165000000,
  216. {
  217. {{0x0, 0x09}, 0x12, 0x0},
  218. {{0x0, 0x09}, 0x12, 0x0},
  219. {{0x0, 0x09}, 0x12, 0x0}
  220. },
  221. {{0x0, 0x0C}, 0x18, 0x3},
  222. },
  223. {
  224. 165000001, 250000000,
  225. {
  226. {{0x0, 0x0F}, 0x12, 0x1},
  227. {{0x0, 0x0F}, 0x12, 0x1},
  228. {{0x0, 0x0F}, 0x12, 0x1}
  229. },
  230. {{0x0, 0x0C}, 0x18, 0x3},
  231. },
  232. {
  233. 250000001, 340000000,
  234. {
  235. {{0x2, 0x0D}, 0x12, 0x1},
  236. {{0x2, 0x0D}, 0x12, 0x1},
  237. {{0x2, 0x0D}, 0x12, 0x1}
  238. },
  239. {{0x0, 0x0C}, 0x18, 0xF},
  240. },
  241. {
  242. 340000001, 450000000,
  243. {
  244. {{0x0, 0x1B}, 0x12, 0xF},
  245. {{0x0, 0x1B}, 0x12, 0xF},
  246. {{0x0, 0x1B}, 0x12, 0xF}
  247. },
  248. {{0x0, 0x0A}, 0x12, 0xF},
  249. },
  250. {
  251. 450000001, 600000000,
  252. {
  253. {{0x0, 0x1C}, 0x12, 0xF},
  254. {{0x0, 0x1C}, 0x12, 0xF},
  255. {{0x0, 0x1C}, 0x12, 0xF}
  256. },
  257. {{0x0, 0x0B}, 0x13, 0xF},
  258. },
  259. };
  260. static const struct phy_settings *phy_get_settings(unsigned long long tmds_rate)
  261. {
  262. unsigned int count = ARRAY_SIZE(vc5_hdmi_phy_settings);
  263. unsigned int i;
  264. for (i = 0; i < count; i++) {
  265. const struct phy_settings *s = &vc5_hdmi_phy_settings[i];
  266. if (tmds_rate >= s->min_rate && tmds_rate <= s->max_rate)
  267. return s;
  268. }
  269. /*
  270. * If the pixel clock exceeds our max setting, try the max
  271. * setting anyway.
  272. */
  273. return &vc5_hdmi_phy_settings[count - 1];
  274. }
  275. static const struct phy_lane_settings *
  276. phy_get_channel_settings(enum vc4_hdmi_phy_channel chan,
  277. unsigned long long tmds_rate)
  278. {
  279. const struct phy_settings *settings = phy_get_settings(tmds_rate);
  280. if (chan == PHY_LANE_CK)
  281. return &settings->clock;
  282. return &settings->channel[chan];
  283. }
  284. static void vc5_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)
  285. {
  286. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x0f);
  287. HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL, BIT(10));
  288. }
  289. void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
  290. {
  291. const struct phy_lane_settings *chan0_settings, *chan1_settings, *chan2_settings, *clock_settings;
  292. const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
  293. unsigned long long pixel_freq = mode->clock * 1000;
  294. unsigned long long vco_freq;
  295. unsigned char word_sel;
  296. u8 vco_sel, vco_div;
  297. vco_freq = phy_get_vco_freq(pixel_freq, &vco_sel, &vco_div);
  298. vc5_hdmi_reset_phy(vc4_hdmi);
  299. HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,
  300. VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
  301. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,
  302. HDMI_READ(HDMI_TX_PHY_RESET_CTL) &
  303. ~VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET &
  304. ~VC4_HDMI_TX_PHY_RESET_CTL_TX_1_RESET &
  305. ~VC4_HDMI_TX_PHY_RESET_CTL_TX_2_RESET &
  306. ~VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET);
  307. HDMI_WRITE(HDMI_RM_CONTROL,
  308. HDMI_READ(HDMI_RM_CONTROL) |
  309. VC4_HDMI_RM_CONTROL_EN_FREEZE_COUNTERS |
  310. VC4_HDMI_RM_CONTROL_EN_LOAD_INTEGRATOR |
  311. VC4_HDMI_RM_CONTROL_FREE_RUN);
  312. HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
  313. (HDMI_READ(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1) &
  314. ~VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK) |
  315. VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT));
  316. HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
  317. (HDMI_READ(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2) &
  318. ~VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK) |
  319. VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT));
  320. HDMI_WRITE(HDMI_RM_OFFSET,
  321. VC4_SET_FIELD(phy_get_rm_offset(vco_freq),
  322. VC4_HDMI_RM_OFFSET_OFFSET) |
  323. VC4_HDMI_RM_OFFSET_ONLY);
  324. HDMI_WRITE(HDMI_TX_PHY_CLK_DIV,
  325. VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO));
  326. HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
  327. VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) |
  328. VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD));
  329. HDMI_WRITE(HDMI_TX_PHY_PLL_CTL_0,
  330. VC4_HDMI_TX_PHY_PLL_CTL_0_ENA_VCO_CLK |
  331. VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_CONT_EN |
  332. VC4_HDMI_TX_PHY_PLL_CTL_0_MASH11_MODE |
  333. VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL));
  334. HDMI_WRITE(HDMI_TX_PHY_PLL_CTL_1,
  335. HDMI_READ(HDMI_TX_PHY_PLL_CTL_1) |
  336. VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_ENABLE |
  337. VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) |
  338. VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) |
  339. VC4_SET_FIELD(0x8a, VC4_HDMI_TX_PHY_PLL_CTL_1_CPP));
  340. HDMI_WRITE(HDMI_RM_FORMAT,
  341. HDMI_READ(HDMI_RM_FORMAT) |
  342. VC4_SET_FIELD(2, VC4_HDMI_RM_FORMAT_SHIFT));
  343. HDMI_WRITE(HDMI_TX_PHY_PLL_CFG,
  344. HDMI_READ(HDMI_TX_PHY_PLL_CFG) |
  345. VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CFG_PDIV));
  346. if (pixel_freq >= 340000000)
  347. word_sel = 3;
  348. else
  349. word_sel = 0;
  350. HDMI_WRITE(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, word_sel);
  351. HDMI_WRITE(HDMI_TX_PHY_CTL_3,
  352. VC4_SET_FIELD(phy_get_cp_current(vco_freq),
  353. VC4_HDMI_TX_PHY_CTL_3_ICP) |
  354. VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP) |
  355. VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP1) |
  356. VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_CTL_3_CZ) |
  357. VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) |
  358. VC4_SET_FIELD(6, VC4_HDMI_TX_PHY_CTL_3_RZ));
  359. chan0_settings =
  360. phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_0],
  361. pixel_freq);
  362. chan1_settings =
  363. phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_1],
  364. pixel_freq);
  365. chan2_settings =
  366. phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_2],
  367. pixel_freq);
  368. clock_settings =
  369. phy_get_channel_settings(variant->phy_lane_mapping[PHY_LANE_CK],
  370. pixel_freq);
  371. HDMI_WRITE(HDMI_TX_PHY_CTL_0,
  372. VC4_SET_FIELD(chan0_settings->amplitude.preemphasis,
  373. VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP) |
  374. VC4_SET_FIELD(chan0_settings->amplitude.main_driver,
  375. VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV) |
  376. VC4_SET_FIELD(chan1_settings->amplitude.preemphasis,
  377. VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP) |
  378. VC4_SET_FIELD(chan1_settings->amplitude.main_driver,
  379. VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV) |
  380. VC4_SET_FIELD(chan2_settings->amplitude.preemphasis,
  381. VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP) |
  382. VC4_SET_FIELD(chan2_settings->amplitude.main_driver,
  383. VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV) |
  384. VC4_SET_FIELD(clock_settings->amplitude.preemphasis,
  385. VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP) |
  386. VC4_SET_FIELD(clock_settings->amplitude.main_driver,
  387. VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV));
  388. HDMI_WRITE(HDMI_TX_PHY_CTL_1,
  389. HDMI_READ(HDMI_TX_PHY_CTL_1) |
  390. VC4_SET_FIELD(chan0_settings->res_sel_data,
  391. VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0) |
  392. VC4_SET_FIELD(chan1_settings->res_sel_data,
  393. VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1) |
  394. VC4_SET_FIELD(chan2_settings->res_sel_data,
  395. VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2) |
  396. VC4_SET_FIELD(clock_settings->res_sel_data,
  397. VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK));
  398. HDMI_WRITE(HDMI_TX_PHY_CTL_2,
  399. VC4_SET_FIELD(chan0_settings->term_res_sel_data,
  400. VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0) |
  401. VC4_SET_FIELD(chan1_settings->term_res_sel_data,
  402. VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1) |
  403. VC4_SET_FIELD(chan2_settings->term_res_sel_data,
  404. VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2) |
  405. VC4_SET_FIELD(clock_settings->term_res_sel_data,
  406. VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK) |
  407. VC4_SET_FIELD(phy_get_vco_gain(vco_freq),
  408. VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN));
  409. HDMI_WRITE(HDMI_TX_PHY_CHANNEL_SWAP,
  410. VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_0],
  411. VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL) |
  412. VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_1],
  413. VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL) |
  414. VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_2],
  415. VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL) |
  416. VC4_SET_FIELD(variant->phy_lane_mapping[PHY_LANE_CK],
  417. VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL));
  418. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,
  419. HDMI_READ(HDMI_TX_PHY_RESET_CTL) &
  420. ~(VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB |
  421. VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB));
  422. HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,
  423. HDMI_READ(HDMI_TX_PHY_RESET_CTL) |
  424. VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB |
  425. VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB);
  426. }
  427. void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
  428. {
  429. vc5_hdmi_reset_phy(vc4_hdmi);
  430. }
  431. void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)
  432. {
  433. HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,
  434. HDMI_READ(HDMI_TX_PHY_POWERDOWN_CTL) &
  435. ~VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
  436. }
  437. void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)
  438. {
  439. HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,
  440. HDMI_READ(HDMI_TX_PHY_POWERDOWN_CTL) |
  441. VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN);
  442. }