vc4_drv.h 28 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2015 Broadcom
  4. */
  5. #ifndef _VC4_DRV_H_
  6. #define _VC4_DRV_H_
  7. #include <linux/delay.h>
  8. #include <linux/refcount.h>
  9. #include <linux/uaccess.h>
  10. #include <drm/drm_atomic.h>
  11. #include <drm/drm_debugfs.h>
  12. #include <drm/drm_device.h>
  13. #include <drm/drm_encoder.h>
  14. #include <drm/drm_gem_cma_helper.h>
  15. #include <drm/drm_managed.h>
  16. #include <drm/drm_mm.h>
  17. #include <drm/drm_modeset_lock.h>
  18. #include "uapi/drm/vc4_drm.h"
  19. struct drm_device;
  20. struct drm_gem_object;
  21. /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
  22. * this.
  23. */
  24. enum vc4_kernel_bo_type {
  25. /* Any kernel allocation (gem_create_object hook) before it
  26. * gets another type set.
  27. */
  28. VC4_BO_TYPE_KERNEL,
  29. VC4_BO_TYPE_V3D,
  30. VC4_BO_TYPE_V3D_SHADER,
  31. VC4_BO_TYPE_DUMB,
  32. VC4_BO_TYPE_BIN,
  33. VC4_BO_TYPE_RCL,
  34. VC4_BO_TYPE_BCL,
  35. VC4_BO_TYPE_KERNEL_CACHE,
  36. VC4_BO_TYPE_COUNT
  37. };
  38. /* Performance monitor object. The perform lifetime is controlled by userspace
  39. * using perfmon related ioctls. A perfmon can be attached to a submit_cl
  40. * request, and when this is the case, HW perf counters will be activated just
  41. * before the submit_cl is submitted to the GPU and disabled when the job is
  42. * done. This way, only events related to a specific job will be counted.
  43. */
  44. struct vc4_perfmon {
  45. /* Tracks the number of users of the perfmon, when this counter reaches
  46. * zero the perfmon is destroyed.
  47. */
  48. refcount_t refcnt;
  49. /* Number of counters activated in this perfmon instance
  50. * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
  51. */
  52. u8 ncounters;
  53. /* Events counted by the HW perf counters. */
  54. u8 events[DRM_VC4_MAX_PERF_COUNTERS];
  55. /* Storage for counter values. Counters are incremented by the HW
  56. * perf counter values every time the perfmon is attached to a GPU job.
  57. * This way, perfmon users don't have to retrieve the results after
  58. * each job if they want to track events covering several submissions.
  59. * Note that counter values can't be reset, but you can fake a reset by
  60. * destroying the perfmon and creating a new one.
  61. */
  62. u64 counters[];
  63. };
  64. struct vc4_dev {
  65. struct drm_device base;
  66. struct vc4_hvs *hvs;
  67. struct vc4_v3d *v3d;
  68. struct vc4_dpi *dpi;
  69. struct vc4_dsi *dsi1;
  70. struct vc4_vec *vec;
  71. struct vc4_txp *txp;
  72. struct vc4_hang_state *hang_state;
  73. /* The kernel-space BO cache. Tracks buffers that have been
  74. * unreferenced by all other users (refcounts of 0!) but not
  75. * yet freed, so we can do cheap allocations.
  76. */
  77. struct vc4_bo_cache {
  78. /* Array of list heads for entries in the BO cache,
  79. * based on number of pages, so we can do O(1) lookups
  80. * in the cache when allocating.
  81. */
  82. struct list_head *size_list;
  83. uint32_t size_list_size;
  84. /* List of all BOs in the cache, ordered by age, so we
  85. * can do O(1) lookups when trying to free old
  86. * buffers.
  87. */
  88. struct list_head time_list;
  89. struct work_struct time_work;
  90. struct timer_list time_timer;
  91. } bo_cache;
  92. u32 num_labels;
  93. struct vc4_label {
  94. const char *name;
  95. u32 num_allocated;
  96. u32 size_allocated;
  97. } *bo_labels;
  98. /* Protects bo_cache and bo_labels. */
  99. struct mutex bo_lock;
  100. /* Purgeable BO pool. All BOs in this pool can have their memory
  101. * reclaimed if the driver is unable to allocate new BOs. We also
  102. * keep stats related to the purge mechanism here.
  103. */
  104. struct {
  105. struct list_head list;
  106. unsigned int num;
  107. size_t size;
  108. unsigned int purged_num;
  109. size_t purged_size;
  110. struct mutex lock;
  111. } purgeable;
  112. uint64_t dma_fence_context;
  113. /* Sequence number for the last job queued in bin_job_list.
  114. * Starts at 0 (no jobs emitted).
  115. */
  116. uint64_t emit_seqno;
  117. /* Sequence number for the last completed job on the GPU.
  118. * Starts at 0 (no jobs completed).
  119. */
  120. uint64_t finished_seqno;
  121. /* List of all struct vc4_exec_info for jobs to be executed in
  122. * the binner. The first job in the list is the one currently
  123. * programmed into ct0ca for execution.
  124. */
  125. struct list_head bin_job_list;
  126. /* List of all struct vc4_exec_info for jobs that have
  127. * completed binning and are ready for rendering. The first
  128. * job in the list is the one currently programmed into ct1ca
  129. * for execution.
  130. */
  131. struct list_head render_job_list;
  132. /* List of the finished vc4_exec_infos waiting to be freed by
  133. * job_done_work.
  134. */
  135. struct list_head job_done_list;
  136. /* Spinlock used to synchronize the job_list and seqno
  137. * accesses between the IRQ handler and GEM ioctls.
  138. */
  139. spinlock_t job_lock;
  140. wait_queue_head_t job_wait_queue;
  141. struct work_struct job_done_work;
  142. /* Used to track the active perfmon if any. Access to this field is
  143. * protected by job_lock.
  144. */
  145. struct vc4_perfmon *active_perfmon;
  146. /* List of struct vc4_seqno_cb for callbacks to be made from a
  147. * workqueue when the given seqno is passed.
  148. */
  149. struct list_head seqno_cb_list;
  150. /* The memory used for storing binner tile alloc, tile state,
  151. * and overflow memory allocations. This is freed when V3D
  152. * powers down.
  153. */
  154. struct vc4_bo *bin_bo;
  155. /* Size of blocks allocated within bin_bo. */
  156. uint32_t bin_alloc_size;
  157. /* Bitmask of the bin_alloc_size chunks in bin_bo that are
  158. * used.
  159. */
  160. uint32_t bin_alloc_used;
  161. /* Bitmask of the current bin_alloc used for overflow memory. */
  162. uint32_t bin_alloc_overflow;
  163. /* Incremented when an underrun error happened after an atomic commit.
  164. * This is particularly useful to detect when a specific modeset is too
  165. * demanding in term of memory or HVS bandwidth which is hard to guess
  166. * at atomic check time.
  167. */
  168. atomic_t underrun;
  169. struct work_struct overflow_mem_work;
  170. int power_refcount;
  171. /* Set to true when the load tracker is supported. */
  172. bool load_tracker_available;
  173. /* Set to true when the load tracker is active. */
  174. bool load_tracker_enabled;
  175. /* Mutex controlling the power refcount. */
  176. struct mutex power_lock;
  177. struct {
  178. struct timer_list timer;
  179. struct work_struct reset_work;
  180. } hangcheck;
  181. struct semaphore async_modeset;
  182. struct drm_modeset_lock ctm_state_lock;
  183. struct drm_private_obj ctm_manager;
  184. struct drm_private_obj hvs_channels;
  185. struct drm_private_obj load_tracker;
  186. /* List of vc4_debugfs_info_entry for adding to debugfs once
  187. * the minor is available (after drm_dev_register()).
  188. */
  189. struct list_head debugfs_list;
  190. /* Mutex for binner bo allocation. */
  191. struct mutex bin_bo_lock;
  192. /* Reference count for our binner bo. */
  193. struct kref bin_bo_kref;
  194. };
  195. static inline struct vc4_dev *
  196. to_vc4_dev(struct drm_device *dev)
  197. {
  198. return container_of(dev, struct vc4_dev, base);
  199. }
  200. struct vc4_bo {
  201. struct drm_gem_cma_object base;
  202. /* seqno of the last job to render using this BO. */
  203. uint64_t seqno;
  204. /* seqno of the last job to use the RCL to write to this BO.
  205. *
  206. * Note that this doesn't include binner overflow memory
  207. * writes.
  208. */
  209. uint64_t write_seqno;
  210. bool t_format;
  211. /* List entry for the BO's position in either
  212. * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
  213. */
  214. struct list_head unref_head;
  215. /* Time in jiffies when the BO was put in vc4->bo_cache. */
  216. unsigned long free_time;
  217. /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
  218. struct list_head size_head;
  219. /* Struct for shader validation state, if created by
  220. * DRM_IOCTL_VC4_CREATE_SHADER_BO.
  221. */
  222. struct vc4_validated_shader_info *validated_shader;
  223. /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
  224. * for user-allocated labels.
  225. */
  226. int label;
  227. /* Count the number of active users. This is needed to determine
  228. * whether we can move the BO to the purgeable list or not (when the BO
  229. * is used by the GPU or the display engine we can't purge it).
  230. */
  231. refcount_t usecnt;
  232. /* Store purgeable/purged state here */
  233. u32 madv;
  234. struct mutex madv_lock;
  235. };
  236. static inline struct vc4_bo *
  237. to_vc4_bo(struct drm_gem_object *bo)
  238. {
  239. return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base);
  240. }
  241. struct vc4_fence {
  242. struct dma_fence base;
  243. struct drm_device *dev;
  244. /* vc4 seqno for signaled() test */
  245. uint64_t seqno;
  246. };
  247. static inline struct vc4_fence *
  248. to_vc4_fence(struct dma_fence *fence)
  249. {
  250. return container_of(fence, struct vc4_fence, base);
  251. }
  252. struct vc4_seqno_cb {
  253. struct work_struct work;
  254. uint64_t seqno;
  255. void (*func)(struct vc4_seqno_cb *cb);
  256. };
  257. struct vc4_v3d {
  258. struct vc4_dev *vc4;
  259. struct platform_device *pdev;
  260. void __iomem *regs;
  261. struct clk *clk;
  262. struct debugfs_regset32 regset;
  263. };
  264. struct vc4_hvs {
  265. struct platform_device *pdev;
  266. void __iomem *regs;
  267. u32 __iomem *dlist;
  268. struct clk *core_clk;
  269. /* Memory manager for CRTCs to allocate space in the display
  270. * list. Units are dwords.
  271. */
  272. struct drm_mm dlist_mm;
  273. /* Memory manager for the LBM memory used by HVS scaling. */
  274. struct drm_mm lbm_mm;
  275. spinlock_t mm_lock;
  276. struct drm_mm_node mitchell_netravali_filter;
  277. struct debugfs_regset32 regset;
  278. /* HVS version 5 flag, therefore requires updated dlist structures */
  279. bool hvs5;
  280. };
  281. struct vc4_plane {
  282. struct drm_plane base;
  283. };
  284. static inline struct vc4_plane *
  285. to_vc4_plane(struct drm_plane *plane)
  286. {
  287. return container_of(plane, struct vc4_plane, base);
  288. }
  289. enum vc4_scaling_mode {
  290. VC4_SCALING_NONE,
  291. VC4_SCALING_TPZ,
  292. VC4_SCALING_PPF,
  293. };
  294. struct vc4_plane_state {
  295. struct drm_plane_state base;
  296. /* System memory copy of the display list for this element, computed
  297. * at atomic_check time.
  298. */
  299. u32 *dlist;
  300. u32 dlist_size; /* Number of dwords allocated for the display list */
  301. u32 dlist_count; /* Number of used dwords in the display list. */
  302. /* Offset in the dlist to various words, for pageflip or
  303. * cursor updates.
  304. */
  305. u32 pos0_offset;
  306. u32 pos2_offset;
  307. u32 ptr0_offset;
  308. u32 lbm_offset;
  309. /* Offset where the plane's dlist was last stored in the
  310. * hardware at vc4_crtc_atomic_flush() time.
  311. */
  312. u32 __iomem *hw_dlist;
  313. /* Clipped coordinates of the plane on the display. */
  314. int crtc_x, crtc_y, crtc_w, crtc_h;
  315. /* Clipped area being scanned from in the FB. */
  316. u32 src_x, src_y;
  317. u32 src_w[2], src_h[2];
  318. /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
  319. enum vc4_scaling_mode x_scaling[2], y_scaling[2];
  320. bool is_unity;
  321. bool is_yuv;
  322. /* Offset to start scanning out from the start of the plane's
  323. * BO.
  324. */
  325. u32 offsets[3];
  326. /* Our allocation in LBM for temporary storage during scaling. */
  327. struct drm_mm_node lbm;
  328. /* Set when the plane has per-pixel alpha content or does not cover
  329. * the entire screen. This is a hint to the CRTC that it might need
  330. * to enable background color fill.
  331. */
  332. bool needs_bg_fill;
  333. /* Mark the dlist as initialized. Useful to avoid initializing it twice
  334. * when async update is not possible.
  335. */
  336. bool dlist_initialized;
  337. /* Load of this plane on the HVS block. The load is expressed in HVS
  338. * cycles/sec.
  339. */
  340. u64 hvs_load;
  341. /* Memory bandwidth needed for this plane. This is expressed in
  342. * bytes/sec.
  343. */
  344. u64 membus_load;
  345. };
  346. static inline struct vc4_plane_state *
  347. to_vc4_plane_state(struct drm_plane_state *state)
  348. {
  349. return container_of(state, struct vc4_plane_state, base);
  350. }
  351. enum vc4_encoder_type {
  352. VC4_ENCODER_TYPE_NONE,
  353. VC4_ENCODER_TYPE_HDMI0,
  354. VC4_ENCODER_TYPE_HDMI1,
  355. VC4_ENCODER_TYPE_VEC,
  356. VC4_ENCODER_TYPE_DSI0,
  357. VC4_ENCODER_TYPE_DSI1,
  358. VC4_ENCODER_TYPE_SMI,
  359. VC4_ENCODER_TYPE_DPI,
  360. };
  361. struct vc4_encoder {
  362. struct drm_encoder base;
  363. enum vc4_encoder_type type;
  364. u32 clock_select;
  365. void (*pre_crtc_configure)(struct drm_encoder *encoder);
  366. void (*pre_crtc_enable)(struct drm_encoder *encoder);
  367. void (*post_crtc_enable)(struct drm_encoder *encoder);
  368. void (*post_crtc_disable)(struct drm_encoder *encoder);
  369. void (*post_crtc_powerdown)(struct drm_encoder *encoder);
  370. };
  371. static inline struct vc4_encoder *
  372. to_vc4_encoder(struct drm_encoder *encoder)
  373. {
  374. return container_of(encoder, struct vc4_encoder, base);
  375. }
  376. struct vc4_crtc_data {
  377. /* Bitmask of channels (FIFOs) of the HVS that the output can source from */
  378. unsigned int hvs_available_channels;
  379. /* Which output of the HVS this pixelvalve sources from. */
  380. int hvs_output;
  381. };
  382. struct vc4_pv_data {
  383. struct vc4_crtc_data base;
  384. /* Depth of the PixelValve FIFO in bytes */
  385. unsigned int fifo_depth;
  386. /* Number of pixels output per clock period */
  387. u8 pixels_per_clock;
  388. enum vc4_encoder_type encoder_types[4];
  389. const char *debugfs_name;
  390. };
  391. struct vc4_crtc {
  392. struct drm_crtc base;
  393. struct platform_device *pdev;
  394. const struct vc4_crtc_data *data;
  395. void __iomem *regs;
  396. /* Timestamp at start of vblank irq - unaffected by lock delays. */
  397. ktime_t t_vblank;
  398. u8 lut_r[256];
  399. u8 lut_g[256];
  400. u8 lut_b[256];
  401. struct drm_pending_vblank_event *event;
  402. struct debugfs_regset32 regset;
  403. };
  404. static inline struct vc4_crtc *
  405. to_vc4_crtc(struct drm_crtc *crtc)
  406. {
  407. return container_of(crtc, struct vc4_crtc, base);
  408. }
  409. static inline const struct vc4_crtc_data *
  410. vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc)
  411. {
  412. return crtc->data;
  413. }
  414. static inline const struct vc4_pv_data *
  415. vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc)
  416. {
  417. const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc);
  418. return container_of(data, struct vc4_pv_data, base);
  419. }
  420. struct vc4_crtc_state {
  421. struct drm_crtc_state base;
  422. /* Dlist area for this CRTC configuration. */
  423. struct drm_mm_node mm;
  424. bool feed_txp;
  425. bool txp_armed;
  426. unsigned int assigned_channel;
  427. struct {
  428. unsigned int left;
  429. unsigned int right;
  430. unsigned int top;
  431. unsigned int bottom;
  432. } margins;
  433. /* Transitional state below, only valid during atomic commits */
  434. bool update_muxing;
  435. };
  436. #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1)
  437. static inline struct vc4_crtc_state *
  438. to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  439. {
  440. return container_of(crtc_state, struct vc4_crtc_state, base);
  441. }
  442. #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
  443. #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
  444. #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
  445. #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
  446. #define VC4_REG32(reg) { .name = #reg, .offset = reg }
  447. struct vc4_exec_info {
  448. /* Sequence number for this bin/render job. */
  449. uint64_t seqno;
  450. /* Latest write_seqno of any BO that binning depends on. */
  451. uint64_t bin_dep_seqno;
  452. struct dma_fence *fence;
  453. /* Last current addresses the hardware was processing when the
  454. * hangcheck timer checked on us.
  455. */
  456. uint32_t last_ct0ca, last_ct1ca;
  457. /* Kernel-space copy of the ioctl arguments */
  458. struct drm_vc4_submit_cl *args;
  459. /* This is the array of BOs that were looked up at the start of exec.
  460. * Command validation will use indices into this array.
  461. */
  462. struct drm_gem_cma_object **bo;
  463. uint32_t bo_count;
  464. /* List of BOs that are being written by the RCL. Other than
  465. * the binner temporary storage, this is all the BOs written
  466. * by the job.
  467. */
  468. struct drm_gem_cma_object *rcl_write_bo[4];
  469. uint32_t rcl_write_bo_count;
  470. /* Pointers for our position in vc4->job_list */
  471. struct list_head head;
  472. /* List of other BOs used in the job that need to be released
  473. * once the job is complete.
  474. */
  475. struct list_head unref_list;
  476. /* Current unvalidated indices into @bo loaded by the non-hardware
  477. * VC4_PACKET_GEM_HANDLES.
  478. */
  479. uint32_t bo_index[2];
  480. /* This is the BO where we store the validated command lists, shader
  481. * records, and uniforms.
  482. */
  483. struct drm_gem_cma_object *exec_bo;
  484. /**
  485. * This tracks the per-shader-record state (packet 64) that
  486. * determines the length of the shader record and the offset
  487. * it's expected to be found at. It gets read in from the
  488. * command lists.
  489. */
  490. struct vc4_shader_state {
  491. uint32_t addr;
  492. /* Maximum vertex index referenced by any primitive using this
  493. * shader state.
  494. */
  495. uint32_t max_index;
  496. } *shader_state;
  497. /** How many shader states the user declared they were using. */
  498. uint32_t shader_state_size;
  499. /** How many shader state records the validator has seen. */
  500. uint32_t shader_state_count;
  501. bool found_tile_binning_mode_config_packet;
  502. bool found_start_tile_binning_packet;
  503. bool found_increment_semaphore_packet;
  504. bool found_flush;
  505. uint8_t bin_tiles_x, bin_tiles_y;
  506. /* Physical address of the start of the tile alloc array
  507. * (where each tile's binned CL will start)
  508. */
  509. uint32_t tile_alloc_offset;
  510. /* Bitmask of which binner slots are freed when this job completes. */
  511. uint32_t bin_slots;
  512. /**
  513. * Computed addresses pointing into exec_bo where we start the
  514. * bin thread (ct0) and render thread (ct1).
  515. */
  516. uint32_t ct0ca, ct0ea;
  517. uint32_t ct1ca, ct1ea;
  518. /* Pointer to the unvalidated bin CL (if present). */
  519. void *bin_u;
  520. /* Pointers to the shader recs. These paddr gets incremented as CL
  521. * packets are relocated in validate_gl_shader_state, and the vaddrs
  522. * (u and v) get incremented and size decremented as the shader recs
  523. * themselves are validated.
  524. */
  525. void *shader_rec_u;
  526. void *shader_rec_v;
  527. uint32_t shader_rec_p;
  528. uint32_t shader_rec_size;
  529. /* Pointers to the uniform data. These pointers are incremented, and
  530. * size decremented, as each batch of uniforms is uploaded.
  531. */
  532. void *uniforms_u;
  533. void *uniforms_v;
  534. uint32_t uniforms_p;
  535. uint32_t uniforms_size;
  536. /* Pointer to a performance monitor object if the user requested it,
  537. * NULL otherwise.
  538. */
  539. struct vc4_perfmon *perfmon;
  540. /* Whether the exec has taken a reference to the binner BO, which should
  541. * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
  542. */
  543. bool bin_bo_used;
  544. };
  545. /* Per-open file private data. Any driver-specific resource that has to be
  546. * released when the DRM file is closed should be placed here.
  547. */
  548. struct vc4_file {
  549. struct {
  550. struct idr idr;
  551. struct mutex lock;
  552. } perfmon;
  553. bool bin_bo_used;
  554. };
  555. static inline struct vc4_exec_info *
  556. vc4_first_bin_job(struct vc4_dev *vc4)
  557. {
  558. return list_first_entry_or_null(&vc4->bin_job_list,
  559. struct vc4_exec_info, head);
  560. }
  561. static inline struct vc4_exec_info *
  562. vc4_first_render_job(struct vc4_dev *vc4)
  563. {
  564. return list_first_entry_or_null(&vc4->render_job_list,
  565. struct vc4_exec_info, head);
  566. }
  567. static inline struct vc4_exec_info *
  568. vc4_last_render_job(struct vc4_dev *vc4)
  569. {
  570. if (list_empty(&vc4->render_job_list))
  571. return NULL;
  572. return list_last_entry(&vc4->render_job_list,
  573. struct vc4_exec_info, head);
  574. }
  575. /**
  576. * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
  577. * setup parameters.
  578. *
  579. * This will be used at draw time to relocate the reference to the texture
  580. * contents in p0, and validate that the offset combined with
  581. * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
  582. * Note that the hardware treats unprovided config parameters as 0, so not all
  583. * of them need to be set up for every texure sample, and we'll store ~0 as
  584. * the offset to mark the unused ones.
  585. *
  586. * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
  587. * Setup") for definitions of the texture parameters.
  588. */
  589. struct vc4_texture_sample_info {
  590. bool is_direct;
  591. uint32_t p_offset[4];
  592. };
  593. /**
  594. * struct vc4_validated_shader_info - information about validated shaders that
  595. * needs to be used from command list validation.
  596. *
  597. * For a given shader, each time a shader state record references it, we need
  598. * to verify that the shader doesn't read more uniforms than the shader state
  599. * record's uniform BO pointer can provide, and we need to apply relocations
  600. * and validate the shader state record's uniforms that define the texture
  601. * samples.
  602. */
  603. struct vc4_validated_shader_info {
  604. uint32_t uniforms_size;
  605. uint32_t uniforms_src_size;
  606. uint32_t num_texture_samples;
  607. struct vc4_texture_sample_info *texture_samples;
  608. uint32_t num_uniform_addr_offsets;
  609. uint32_t *uniform_addr_offsets;
  610. bool is_threaded;
  611. };
  612. /**
  613. * __wait_for - magic wait macro
  614. *
  615. * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  616. * important that we check the condition again after having timed out, since the
  617. * timeout could be due to preemption or similar and we've never had a chance to
  618. * check the condition before the timeout.
  619. */
  620. #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  621. const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  622. long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  623. int ret__; \
  624. might_sleep(); \
  625. for (;;) { \
  626. const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  627. OP; \
  628. /* Guarantee COND check prior to timeout */ \
  629. barrier(); \
  630. if (COND) { \
  631. ret__ = 0; \
  632. break; \
  633. } \
  634. if (expired__) { \
  635. ret__ = -ETIMEDOUT; \
  636. break; \
  637. } \
  638. usleep_range(wait__, wait__ * 2); \
  639. if (wait__ < (Wmax)) \
  640. wait__ <<= 1; \
  641. } \
  642. ret__; \
  643. })
  644. #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  645. (Wmax))
  646. #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
  647. /* vc4_bo.c */
  648. struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
  649. void vc4_free_object(struct drm_gem_object *gem_obj);
  650. struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
  651. bool from_cache, enum vc4_kernel_bo_type type);
  652. int vc4_dumb_create(struct drm_file *file_priv,
  653. struct drm_device *dev,
  654. struct drm_mode_create_dumb *args);
  655. struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
  656. int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
  657. struct drm_file *file_priv);
  658. int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
  659. struct drm_file *file_priv);
  660. int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
  661. struct drm_file *file_priv);
  662. int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
  663. struct drm_file *file_priv);
  664. int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
  665. struct drm_file *file_priv);
  666. int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
  667. struct drm_file *file_priv);
  668. int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
  669. struct drm_file *file_priv);
  670. vm_fault_t vc4_fault(struct vm_fault *vmf);
  671. int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
  672. int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
  673. struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
  674. struct dma_buf_attachment *attach,
  675. struct sg_table *sgt);
  676. void *vc4_prime_vmap(struct drm_gem_object *obj);
  677. int vc4_bo_cache_init(struct drm_device *dev);
  678. int vc4_bo_inc_usecnt(struct vc4_bo *bo);
  679. void vc4_bo_dec_usecnt(struct vc4_bo *bo);
  680. void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
  681. void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
  682. /* vc4_crtc.c */
  683. extern struct platform_driver vc4_crtc_driver;
  684. int vc4_crtc_disable_at_boot(struct drm_crtc *crtc);
  685. int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
  686. const struct drm_crtc_funcs *crtc_funcs,
  687. const struct drm_crtc_helper_funcs *crtc_helper_funcs);
  688. void vc4_crtc_destroy(struct drm_crtc *crtc);
  689. int vc4_page_flip(struct drm_crtc *crtc,
  690. struct drm_framebuffer *fb,
  691. struct drm_pending_vblank_event *event,
  692. uint32_t flags,
  693. struct drm_modeset_acquire_ctx *ctx);
  694. struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc);
  695. void vc4_crtc_destroy_state(struct drm_crtc *crtc,
  696. struct drm_crtc_state *state);
  697. void vc4_crtc_reset(struct drm_crtc *crtc);
  698. void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
  699. void vc4_crtc_get_margins(struct drm_crtc_state *state,
  700. unsigned int *left, unsigned int *right,
  701. unsigned int *top, unsigned int *bottom);
  702. /* vc4_debugfs.c */
  703. void vc4_debugfs_init(struct drm_minor *minor);
  704. #ifdef CONFIG_DEBUG_FS
  705. void vc4_debugfs_add_file(struct drm_device *drm,
  706. const char *filename,
  707. int (*show)(struct seq_file*, void*),
  708. void *data);
  709. void vc4_debugfs_add_regset32(struct drm_device *drm,
  710. const char *filename,
  711. struct debugfs_regset32 *regset);
  712. #else
  713. static inline void vc4_debugfs_add_file(struct drm_device *drm,
  714. const char *filename,
  715. int (*show)(struct seq_file*, void*),
  716. void *data)
  717. {
  718. }
  719. static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
  720. const char *filename,
  721. struct debugfs_regset32 *regset)
  722. {
  723. }
  724. #endif
  725. /* vc4_drv.c */
  726. void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
  727. /* vc4_dpi.c */
  728. extern struct platform_driver vc4_dpi_driver;
  729. /* vc4_dsi.c */
  730. extern struct platform_driver vc4_dsi_driver;
  731. /* vc4_fence.c */
  732. extern const struct dma_fence_ops vc4_fence_ops;
  733. /* vc4_gem.c */
  734. int vc4_gem_init(struct drm_device *dev);
  735. int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
  736. struct drm_file *file_priv);
  737. int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
  738. struct drm_file *file_priv);
  739. int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
  740. struct drm_file *file_priv);
  741. void vc4_submit_next_bin_job(struct drm_device *dev);
  742. void vc4_submit_next_render_job(struct drm_device *dev);
  743. void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
  744. int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
  745. uint64_t timeout_ns, bool interruptible);
  746. void vc4_job_handle_completed(struct vc4_dev *vc4);
  747. int vc4_queue_seqno_cb(struct drm_device *dev,
  748. struct vc4_seqno_cb *cb, uint64_t seqno,
  749. void (*func)(struct vc4_seqno_cb *cb));
  750. int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
  751. struct drm_file *file_priv);
  752. /* vc4_hdmi.c */
  753. extern struct platform_driver vc4_hdmi_driver;
  754. /* vc4_vec.c */
  755. extern struct platform_driver vc4_vec_driver;
  756. /* vc4_txp.c */
  757. extern struct platform_driver vc4_txp_driver;
  758. /* vc4_irq.c */
  759. irqreturn_t vc4_irq(int irq, void *arg);
  760. void vc4_irq_preinstall(struct drm_device *dev);
  761. int vc4_irq_postinstall(struct drm_device *dev);
  762. void vc4_irq_uninstall(struct drm_device *dev);
  763. void vc4_irq_reset(struct drm_device *dev);
  764. /* vc4_hvs.c */
  765. extern struct platform_driver vc4_hvs_driver;
  766. void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
  767. int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
  768. int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
  769. void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);
  770. void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);
  771. void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state);
  772. void vc4_hvs_dump_state(struct drm_device *dev);
  773. void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
  774. void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
  775. /* vc4_kms.c */
  776. int vc4_kms_load(struct drm_device *dev);
  777. /* vc4_plane.c */
  778. struct drm_plane *vc4_plane_init(struct drm_device *dev,
  779. enum drm_plane_type type);
  780. int vc4_plane_create_additional_planes(struct drm_device *dev);
  781. u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
  782. u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
  783. void vc4_plane_async_set_fb(struct drm_plane *plane,
  784. struct drm_framebuffer *fb);
  785. /* vc4_v3d.c */
  786. extern struct platform_driver vc4_v3d_driver;
  787. extern const struct of_device_id vc4_v3d_dt_match[];
  788. int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
  789. int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
  790. void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
  791. int vc4_v3d_pm_get(struct vc4_dev *vc4);
  792. void vc4_v3d_pm_put(struct vc4_dev *vc4);
  793. /* vc4_validate.c */
  794. int
  795. vc4_validate_bin_cl(struct drm_device *dev,
  796. void *validated,
  797. void *unvalidated,
  798. struct vc4_exec_info *exec);
  799. int
  800. vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
  801. struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
  802. uint32_t hindex);
  803. int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
  804. bool vc4_check_tex_size(struct vc4_exec_info *exec,
  805. struct drm_gem_cma_object *fbo,
  806. uint32_t offset, uint8_t tiling_format,
  807. uint32_t width, uint32_t height, uint8_t cpp);
  808. /* vc4_validate_shader.c */
  809. struct vc4_validated_shader_info *
  810. vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
  811. /* vc4_perfmon.c */
  812. void vc4_perfmon_get(struct vc4_perfmon *perfmon);
  813. void vc4_perfmon_put(struct vc4_perfmon *perfmon);
  814. void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
  815. void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
  816. bool capture);
  817. struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
  818. void vc4_perfmon_open_file(struct vc4_file *vc4file);
  819. void vc4_perfmon_close_file(struct vc4_file *vc4file);
  820. int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
  821. struct drm_file *file_priv);
  822. int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
  823. struct drm_file *file_priv);
  824. int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
  825. struct drm_file *file_priv);
  826. #endif /* _VC4_DRV_H_ */