v3d_mmu.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright (C) 2017-2018 Broadcom */
  3. /**
  4. * DOC: Broadcom V3D MMU
  5. *
  6. * The V3D 3.x hardware (compared to VC4) now includes an MMU. It has
  7. * a single level of page tables for the V3D's 4GB address space to
  8. * map to AXI bus addresses, thus it could need up to 4MB of
  9. * physically contiguous memory to store the PTEs.
  10. *
  11. * Because the 4MB of contiguous memory for page tables is precious,
  12. * and switching between them is expensive, we load all BOs into the
  13. * same 4GB address space.
  14. *
  15. * To protect clients from each other, we should use the GMP to
  16. * quickly mask out (at 128kb granularity) what pages are available to
  17. * each client. This is not yet implemented.
  18. */
  19. #include "v3d_drv.h"
  20. #include "v3d_regs.h"
  21. #define V3D_MMU_PAGE_SHIFT 12
  22. /* Note: All PTEs for the 1MB superpage must be filled with the
  23. * superpage bit set.
  24. */
  25. #define V3D_PTE_SUPERPAGE BIT(31)
  26. #define V3D_PTE_WRITEABLE BIT(29)
  27. #define V3D_PTE_VALID BIT(28)
  28. static int v3d_mmu_flush_all(struct v3d_dev *v3d)
  29. {
  30. int ret;
  31. /* Make sure that another flush isn't already running when we
  32. * start this one.
  33. */
  34. ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
  35. V3D_MMU_CTL_TLB_CLEARING), 100);
  36. if (ret)
  37. dev_err(v3d->drm.dev, "TLB clear wait idle pre-wait failed\n");
  38. V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) |
  39. V3D_MMU_CTL_TLB_CLEAR);
  40. V3D_WRITE(V3D_MMUC_CONTROL,
  41. V3D_MMUC_CONTROL_FLUSH |
  42. V3D_MMUC_CONTROL_ENABLE);
  43. ret = wait_for(!(V3D_READ(V3D_MMU_CTL) &
  44. V3D_MMU_CTL_TLB_CLEARING), 100);
  45. if (ret) {
  46. dev_err(v3d->drm.dev, "TLB clear wait idle failed\n");
  47. return ret;
  48. }
  49. ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) &
  50. V3D_MMUC_CONTROL_FLUSHING), 100);
  51. if (ret)
  52. dev_err(v3d->drm.dev, "MMUC flush wait idle failed\n");
  53. return ret;
  54. }
  55. int v3d_mmu_set_page_table(struct v3d_dev *v3d)
  56. {
  57. V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT);
  58. V3D_WRITE(V3D_MMU_CTL,
  59. V3D_MMU_CTL_ENABLE |
  60. V3D_MMU_CTL_PT_INVALID_ENABLE |
  61. V3D_MMU_CTL_PT_INVALID_ABORT |
  62. V3D_MMU_CTL_PT_INVALID_INT |
  63. V3D_MMU_CTL_WRITE_VIOLATION_ABORT |
  64. V3D_MMU_CTL_WRITE_VIOLATION_INT |
  65. V3D_MMU_CTL_CAP_EXCEEDED_ABORT |
  66. V3D_MMU_CTL_CAP_EXCEEDED_INT);
  67. V3D_WRITE(V3D_MMU_ILLEGAL_ADDR,
  68. (v3d->mmu_scratch_paddr >> V3D_MMU_PAGE_SHIFT) |
  69. V3D_MMU_ILLEGAL_ADDR_ENABLE);
  70. V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE);
  71. return v3d_mmu_flush_all(v3d);
  72. }
  73. void v3d_mmu_insert_ptes(struct v3d_bo *bo)
  74. {
  75. struct drm_gem_shmem_object *shmem_obj = &bo->base;
  76. struct v3d_dev *v3d = to_v3d_dev(shmem_obj->base.dev);
  77. u32 page = bo->node.start;
  78. u32 page_prot = V3D_PTE_WRITEABLE | V3D_PTE_VALID;
  79. struct sg_dma_page_iter dma_iter;
  80. for_each_sgtable_dma_page(shmem_obj->sgt, &dma_iter, 0) {
  81. dma_addr_t dma_addr = sg_page_iter_dma_address(&dma_iter);
  82. u32 page_address = dma_addr >> V3D_MMU_PAGE_SHIFT;
  83. u32 pte = page_prot | page_address;
  84. u32 i;
  85. BUG_ON(page_address + (PAGE_SIZE >> V3D_MMU_PAGE_SHIFT) >=
  86. BIT(24));
  87. for (i = 0; i < PAGE_SIZE >> V3D_MMU_PAGE_SHIFT; i++)
  88. v3d->pt[page++] = pte + i;
  89. }
  90. WARN_ON_ONCE(page - bo->node.start !=
  91. shmem_obj->base.size >> V3D_MMU_PAGE_SHIFT);
  92. if (v3d_mmu_flush_all(v3d))
  93. dev_err(v3d->drm.dev, "MMU flush timeout\n");
  94. }
  95. void v3d_mmu_remove_ptes(struct v3d_bo *bo)
  96. {
  97. struct v3d_dev *v3d = to_v3d_dev(bo->base.base.dev);
  98. u32 npages = bo->base.base.size >> V3D_MMU_PAGE_SHIFT;
  99. u32 page;
  100. for (page = bo->node.start; page < bo->node.start + npages; page++)
  101. v3d->pt[page] = 0;
  102. if (v3d_mmu_flush_all(v3d))
  103. dev_err(v3d->drm.dev, "MMU flush timeout\n");
  104. }