sor.c 101 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 NVIDIA Corporation
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/clk-provider.h>
  7. #include <linux/debugfs.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_runtime.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/reset.h>
  15. #include <soc/tegra/pmc.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_debugfs.h>
  18. #include <drm/drm_dp_helper.h>
  19. #include <drm/drm_file.h>
  20. #include <drm/drm_panel.h>
  21. #include <drm/drm_scdc_helper.h>
  22. #include <drm/drm_simple_kms_helper.h>
  23. #include "dc.h"
  24. #include "dp.h"
  25. #include "drm.h"
  26. #include "hda.h"
  27. #include "sor.h"
  28. #include "trace.h"
  29. #define SOR_REKEY 0x38
  30. struct tegra_sor_hdmi_settings {
  31. unsigned long frequency;
  32. u8 vcocap;
  33. u8 filter;
  34. u8 ichpmp;
  35. u8 loadadj;
  36. u8 tmds_termadj;
  37. u8 tx_pu_value;
  38. u8 bg_temp_coef;
  39. u8 bg_vref_level;
  40. u8 avdd10_level;
  41. u8 avdd14_level;
  42. u8 sparepll;
  43. u8 drive_current[4];
  44. u8 preemphasis[4];
  45. };
  46. #if 1
  47. static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  48. {
  49. .frequency = 54000000,
  50. .vcocap = 0x0,
  51. .filter = 0x0,
  52. .ichpmp = 0x1,
  53. .loadadj = 0x3,
  54. .tmds_termadj = 0x9,
  55. .tx_pu_value = 0x10,
  56. .bg_temp_coef = 0x3,
  57. .bg_vref_level = 0x8,
  58. .avdd10_level = 0x4,
  59. .avdd14_level = 0x4,
  60. .sparepll = 0x0,
  61. .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  62. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  63. }, {
  64. .frequency = 75000000,
  65. .vcocap = 0x3,
  66. .filter = 0x0,
  67. .ichpmp = 0x1,
  68. .loadadj = 0x3,
  69. .tmds_termadj = 0x9,
  70. .tx_pu_value = 0x40,
  71. .bg_temp_coef = 0x3,
  72. .bg_vref_level = 0x8,
  73. .avdd10_level = 0x4,
  74. .avdd14_level = 0x4,
  75. .sparepll = 0x0,
  76. .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  77. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  78. }, {
  79. .frequency = 150000000,
  80. .vcocap = 0x3,
  81. .filter = 0x0,
  82. .ichpmp = 0x1,
  83. .loadadj = 0x3,
  84. .tmds_termadj = 0x9,
  85. .tx_pu_value = 0x66,
  86. .bg_temp_coef = 0x3,
  87. .bg_vref_level = 0x8,
  88. .avdd10_level = 0x4,
  89. .avdd14_level = 0x4,
  90. .sparepll = 0x0,
  91. .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  92. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  93. }, {
  94. .frequency = 300000000,
  95. .vcocap = 0x3,
  96. .filter = 0x0,
  97. .ichpmp = 0x1,
  98. .loadadj = 0x3,
  99. .tmds_termadj = 0x9,
  100. .tx_pu_value = 0x66,
  101. .bg_temp_coef = 0x3,
  102. .bg_vref_level = 0xa,
  103. .avdd10_level = 0x4,
  104. .avdd14_level = 0x4,
  105. .sparepll = 0x0,
  106. .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  107. .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
  108. }, {
  109. .frequency = 600000000,
  110. .vcocap = 0x3,
  111. .filter = 0x0,
  112. .ichpmp = 0x1,
  113. .loadadj = 0x3,
  114. .tmds_termadj = 0x9,
  115. .tx_pu_value = 0x66,
  116. .bg_temp_coef = 0x3,
  117. .bg_vref_level = 0x8,
  118. .avdd10_level = 0x4,
  119. .avdd14_level = 0x4,
  120. .sparepll = 0x0,
  121. .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
  122. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  123. },
  124. };
  125. #else
  126. static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  127. {
  128. .frequency = 75000000,
  129. .vcocap = 0x3,
  130. .filter = 0x0,
  131. .ichpmp = 0x1,
  132. .loadadj = 0x3,
  133. .tmds_termadj = 0x9,
  134. .tx_pu_value = 0x40,
  135. .bg_temp_coef = 0x3,
  136. .bg_vref_level = 0x8,
  137. .avdd10_level = 0x4,
  138. .avdd14_level = 0x4,
  139. .sparepll = 0x0,
  140. .drive_current = { 0x29, 0x29, 0x29, 0x29 },
  141. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  142. }, {
  143. .frequency = 150000000,
  144. .vcocap = 0x3,
  145. .filter = 0x0,
  146. .ichpmp = 0x1,
  147. .loadadj = 0x3,
  148. .tmds_termadj = 0x9,
  149. .tx_pu_value = 0x66,
  150. .bg_temp_coef = 0x3,
  151. .bg_vref_level = 0x8,
  152. .avdd10_level = 0x4,
  153. .avdd14_level = 0x4,
  154. .sparepll = 0x0,
  155. .drive_current = { 0x30, 0x37, 0x37, 0x37 },
  156. .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
  157. }, {
  158. .frequency = 300000000,
  159. .vcocap = 0x3,
  160. .filter = 0x0,
  161. .ichpmp = 0x6,
  162. .loadadj = 0x3,
  163. .tmds_termadj = 0x9,
  164. .tx_pu_value = 0x66,
  165. .bg_temp_coef = 0x3,
  166. .bg_vref_level = 0xf,
  167. .avdd10_level = 0x4,
  168. .avdd14_level = 0x4,
  169. .sparepll = 0x0,
  170. .drive_current = { 0x30, 0x37, 0x37, 0x37 },
  171. .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
  172. }, {
  173. .frequency = 600000000,
  174. .vcocap = 0x3,
  175. .filter = 0x0,
  176. .ichpmp = 0xa,
  177. .loadadj = 0x3,
  178. .tmds_termadj = 0xb,
  179. .tx_pu_value = 0x66,
  180. .bg_temp_coef = 0x3,
  181. .bg_vref_level = 0xe,
  182. .avdd10_level = 0x4,
  183. .avdd14_level = 0x4,
  184. .sparepll = 0x0,
  185. .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
  186. .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
  187. },
  188. };
  189. #endif
  190. static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
  191. {
  192. .frequency = 54000000,
  193. .vcocap = 0,
  194. .filter = 5,
  195. .ichpmp = 5,
  196. .loadadj = 3,
  197. .tmds_termadj = 0xf,
  198. .tx_pu_value = 0,
  199. .bg_temp_coef = 3,
  200. .bg_vref_level = 8,
  201. .avdd10_level = 4,
  202. .avdd14_level = 4,
  203. .sparepll = 0x54,
  204. .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
  205. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  206. }, {
  207. .frequency = 75000000,
  208. .vcocap = 1,
  209. .filter = 5,
  210. .ichpmp = 5,
  211. .loadadj = 3,
  212. .tmds_termadj = 0xf,
  213. .tx_pu_value = 0,
  214. .bg_temp_coef = 3,
  215. .bg_vref_level = 8,
  216. .avdd10_level = 4,
  217. .avdd14_level = 4,
  218. .sparepll = 0x44,
  219. .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
  220. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  221. }, {
  222. .frequency = 150000000,
  223. .vcocap = 3,
  224. .filter = 5,
  225. .ichpmp = 5,
  226. .loadadj = 3,
  227. .tmds_termadj = 15,
  228. .tx_pu_value = 0x66 /* 0 */,
  229. .bg_temp_coef = 3,
  230. .bg_vref_level = 8,
  231. .avdd10_level = 4,
  232. .avdd14_level = 4,
  233. .sparepll = 0x00, /* 0x34 */
  234. .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
  235. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  236. }, {
  237. .frequency = 300000000,
  238. .vcocap = 3,
  239. .filter = 5,
  240. .ichpmp = 5,
  241. .loadadj = 3,
  242. .tmds_termadj = 15,
  243. .tx_pu_value = 64,
  244. .bg_temp_coef = 3,
  245. .bg_vref_level = 8,
  246. .avdd10_level = 4,
  247. .avdd14_level = 4,
  248. .sparepll = 0x34,
  249. .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
  250. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  251. }, {
  252. .frequency = 600000000,
  253. .vcocap = 3,
  254. .filter = 5,
  255. .ichpmp = 5,
  256. .loadadj = 3,
  257. .tmds_termadj = 12,
  258. .tx_pu_value = 96,
  259. .bg_temp_coef = 3,
  260. .bg_vref_level = 8,
  261. .avdd10_level = 4,
  262. .avdd14_level = 4,
  263. .sparepll = 0x34,
  264. .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
  265. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  266. }
  267. };
  268. static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
  269. {
  270. .frequency = 54000000,
  271. .vcocap = 0,
  272. .filter = 5,
  273. .ichpmp = 5,
  274. .loadadj = 3,
  275. .tmds_termadj = 0xf,
  276. .tx_pu_value = 0,
  277. .bg_temp_coef = 3,
  278. .bg_vref_level = 8,
  279. .avdd10_level = 4,
  280. .avdd14_level = 4,
  281. .sparepll = 0x54,
  282. .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
  283. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  284. }, {
  285. .frequency = 75000000,
  286. .vcocap = 1,
  287. .filter = 5,
  288. .ichpmp = 5,
  289. .loadadj = 3,
  290. .tmds_termadj = 0xf,
  291. .tx_pu_value = 0,
  292. .bg_temp_coef = 3,
  293. .bg_vref_level = 8,
  294. .avdd10_level = 4,
  295. .avdd14_level = 4,
  296. .sparepll = 0x44,
  297. .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
  298. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  299. }, {
  300. .frequency = 150000000,
  301. .vcocap = 3,
  302. .filter = 5,
  303. .ichpmp = 5,
  304. .loadadj = 3,
  305. .tmds_termadj = 15,
  306. .tx_pu_value = 0x66 /* 0 */,
  307. .bg_temp_coef = 3,
  308. .bg_vref_level = 8,
  309. .avdd10_level = 4,
  310. .avdd14_level = 4,
  311. .sparepll = 0x00, /* 0x34 */
  312. .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
  313. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  314. }, {
  315. .frequency = 300000000,
  316. .vcocap = 3,
  317. .filter = 5,
  318. .ichpmp = 5,
  319. .loadadj = 3,
  320. .tmds_termadj = 15,
  321. .tx_pu_value = 64,
  322. .bg_temp_coef = 3,
  323. .bg_vref_level = 8,
  324. .avdd10_level = 4,
  325. .avdd14_level = 4,
  326. .sparepll = 0x34,
  327. .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
  328. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  329. }, {
  330. .frequency = 600000000,
  331. .vcocap = 3,
  332. .filter = 5,
  333. .ichpmp = 5,
  334. .loadadj = 3,
  335. .tmds_termadj = 12,
  336. .tx_pu_value = 96,
  337. .bg_temp_coef = 3,
  338. .bg_vref_level = 8,
  339. .avdd10_level = 4,
  340. .avdd14_level = 4,
  341. .sparepll = 0x34,
  342. .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
  343. .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  344. }
  345. };
  346. struct tegra_sor_regs {
  347. unsigned int head_state0;
  348. unsigned int head_state1;
  349. unsigned int head_state2;
  350. unsigned int head_state3;
  351. unsigned int head_state4;
  352. unsigned int head_state5;
  353. unsigned int pll0;
  354. unsigned int pll1;
  355. unsigned int pll2;
  356. unsigned int pll3;
  357. unsigned int dp_padctl0;
  358. unsigned int dp_padctl2;
  359. };
  360. struct tegra_sor_soc {
  361. bool supports_lvds;
  362. bool supports_hdmi;
  363. bool supports_dp;
  364. bool supports_audio;
  365. bool supports_hdcp;
  366. const struct tegra_sor_regs *regs;
  367. bool has_nvdisplay;
  368. const struct tegra_sor_hdmi_settings *settings;
  369. unsigned int num_settings;
  370. const u8 *xbar_cfg;
  371. const u8 *lane_map;
  372. const u8 (*voltage_swing)[4][4];
  373. const u8 (*pre_emphasis)[4][4];
  374. const u8 (*post_cursor)[4][4];
  375. const u8 (*tx_pu)[4][4];
  376. };
  377. struct tegra_sor;
  378. struct tegra_sor_ops {
  379. const char *name;
  380. int (*probe)(struct tegra_sor *sor);
  381. void (*audio_enable)(struct tegra_sor *sor);
  382. void (*audio_disable)(struct tegra_sor *sor);
  383. };
  384. struct tegra_sor {
  385. struct host1x_client client;
  386. struct tegra_output output;
  387. struct device *dev;
  388. const struct tegra_sor_soc *soc;
  389. void __iomem *regs;
  390. unsigned int index;
  391. unsigned int irq;
  392. struct reset_control *rst;
  393. struct clk *clk_parent;
  394. struct clk *clk_safe;
  395. struct clk *clk_out;
  396. struct clk *clk_pad;
  397. struct clk *clk_dp;
  398. struct clk *clk;
  399. u8 xbar_cfg[5];
  400. struct drm_dp_link link;
  401. struct drm_dp_aux *aux;
  402. struct drm_info_list *debugfs_files;
  403. const struct tegra_sor_ops *ops;
  404. enum tegra_io_pad pad;
  405. /* for HDMI 2.0 */
  406. struct tegra_sor_hdmi_settings *settings;
  407. unsigned int num_settings;
  408. struct regulator *avdd_io_supply;
  409. struct regulator *vdd_pll_supply;
  410. struct regulator *hdmi_supply;
  411. struct delayed_work scdc;
  412. bool scdc_enabled;
  413. struct tegra_hda_format format;
  414. };
  415. struct tegra_sor_state {
  416. struct drm_connector_state base;
  417. unsigned int link_speed;
  418. unsigned long pclk;
  419. unsigned int bpc;
  420. };
  421. static inline struct tegra_sor_state *
  422. to_sor_state(struct drm_connector_state *state)
  423. {
  424. return container_of(state, struct tegra_sor_state, base);
  425. }
  426. struct tegra_sor_config {
  427. u32 bits_per_pixel;
  428. u32 active_polarity;
  429. u32 active_count;
  430. u32 tu_size;
  431. u32 active_frac;
  432. u32 watermark;
  433. u32 hblank_symbols;
  434. u32 vblank_symbols;
  435. };
  436. static inline struct tegra_sor *
  437. host1x_client_to_sor(struct host1x_client *client)
  438. {
  439. return container_of(client, struct tegra_sor, client);
  440. }
  441. static inline struct tegra_sor *to_sor(struct tegra_output *output)
  442. {
  443. return container_of(output, struct tegra_sor, output);
  444. }
  445. static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
  446. {
  447. u32 value = readl(sor->regs + (offset << 2));
  448. trace_sor_readl(sor->dev, offset, value);
  449. return value;
  450. }
  451. static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
  452. unsigned int offset)
  453. {
  454. trace_sor_writel(sor->dev, offset, value);
  455. writel(value, sor->regs + (offset << 2));
  456. }
  457. static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
  458. {
  459. int err;
  460. clk_disable_unprepare(sor->clk);
  461. err = clk_set_parent(sor->clk_out, parent);
  462. if (err < 0)
  463. return err;
  464. err = clk_prepare_enable(sor->clk);
  465. if (err < 0)
  466. return err;
  467. return 0;
  468. }
  469. struct tegra_clk_sor_pad {
  470. struct clk_hw hw;
  471. struct tegra_sor *sor;
  472. };
  473. static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
  474. {
  475. return container_of(hw, struct tegra_clk_sor_pad, hw);
  476. }
  477. static const char * const tegra_clk_sor_pad_parents[2][2] = {
  478. { "pll_d_out0", "pll_dp" },
  479. { "pll_d2_out0", "pll_dp" },
  480. };
  481. /*
  482. * Implementing ->set_parent() here isn't really required because the parent
  483. * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
  484. * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
  485. * Tegra186 and later SoC generations where the BPMP implements this clock
  486. * and doesn't expose the mux via the common clock framework.
  487. */
  488. static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
  489. {
  490. struct tegra_clk_sor_pad *pad = to_pad(hw);
  491. struct tegra_sor *sor = pad->sor;
  492. u32 value;
  493. value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
  494. value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
  495. switch (index) {
  496. case 0:
  497. value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
  498. break;
  499. case 1:
  500. value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
  501. break;
  502. }
  503. tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
  504. return 0;
  505. }
  506. static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
  507. {
  508. struct tegra_clk_sor_pad *pad = to_pad(hw);
  509. struct tegra_sor *sor = pad->sor;
  510. u8 parent = U8_MAX;
  511. u32 value;
  512. value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
  513. switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
  514. case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
  515. case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
  516. parent = 0;
  517. break;
  518. case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
  519. case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
  520. parent = 1;
  521. break;
  522. }
  523. return parent;
  524. }
  525. static const struct clk_ops tegra_clk_sor_pad_ops = {
  526. .set_parent = tegra_clk_sor_pad_set_parent,
  527. .get_parent = tegra_clk_sor_pad_get_parent,
  528. };
  529. static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
  530. const char *name)
  531. {
  532. struct tegra_clk_sor_pad *pad;
  533. struct clk_init_data init;
  534. struct clk *clk;
  535. pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
  536. if (!pad)
  537. return ERR_PTR(-ENOMEM);
  538. pad->sor = sor;
  539. init.name = name;
  540. init.flags = 0;
  541. init.parent_names = tegra_clk_sor_pad_parents[sor->index];
  542. init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
  543. init.ops = &tegra_clk_sor_pad_ops;
  544. pad->hw.init = &init;
  545. clk = devm_clk_register(sor->dev, &pad->hw);
  546. return clk;
  547. }
  548. static void tegra_sor_filter_rates(struct tegra_sor *sor)
  549. {
  550. struct drm_dp_link *link = &sor->link;
  551. unsigned int i;
  552. /* Tegra only supports RBR, HBR and HBR2 */
  553. for (i = 0; i < link->num_rates; i++) {
  554. switch (link->rates[i]) {
  555. case 1620000:
  556. case 2700000:
  557. case 5400000:
  558. break;
  559. default:
  560. DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
  561. link->rates[i]);
  562. link->rates[i] = 0;
  563. break;
  564. }
  565. }
  566. drm_dp_link_update_rates(link);
  567. }
  568. static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
  569. {
  570. unsigned long timeout;
  571. u32 value;
  572. /*
  573. * Clear or set the PD_TXD bit corresponding to each lane, depending
  574. * on whether it is used or not.
  575. */
  576. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  577. if (lanes <= 2)
  578. value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
  579. SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
  580. else
  581. value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
  582. SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
  583. if (lanes <= 1)
  584. value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
  585. else
  586. value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
  587. if (lanes == 0)
  588. value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
  589. else
  590. value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
  591. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  592. /* start lane sequencer */
  593. value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
  594. SOR_LANE_SEQ_CTL_POWER_STATE_UP;
  595. tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
  596. timeout = jiffies + msecs_to_jiffies(250);
  597. while (time_before(jiffies, timeout)) {
  598. value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
  599. if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
  600. break;
  601. usleep_range(250, 1000);
  602. }
  603. if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
  604. return -ETIMEDOUT;
  605. return 0;
  606. }
  607. static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
  608. {
  609. unsigned long timeout;
  610. u32 value;
  611. /* power down all lanes */
  612. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  613. value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
  614. SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
  615. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  616. /* start lane sequencer */
  617. value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
  618. SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
  619. tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
  620. timeout = jiffies + msecs_to_jiffies(250);
  621. while (time_before(jiffies, timeout)) {
  622. value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
  623. if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
  624. break;
  625. usleep_range(25, 100);
  626. }
  627. if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
  628. return -ETIMEDOUT;
  629. return 0;
  630. }
  631. static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
  632. {
  633. u32 value;
  634. /* pre-charge all used lanes */
  635. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  636. if (lanes <= 2)
  637. value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
  638. SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
  639. else
  640. value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
  641. SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
  642. if (lanes <= 1)
  643. value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
  644. else
  645. value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
  646. if (lanes == 0)
  647. value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
  648. else
  649. value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
  650. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  651. usleep_range(15, 100);
  652. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  653. value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
  654. SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
  655. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  656. }
  657. static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
  658. {
  659. u32 mask = 0x08, adj = 0, value;
  660. /* enable pad calibration logic */
  661. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  662. value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
  663. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  664. value = tegra_sor_readl(sor, sor->soc->regs->pll1);
  665. value |= SOR_PLL1_TMDS_TERM;
  666. tegra_sor_writel(sor, value, sor->soc->regs->pll1);
  667. while (mask) {
  668. adj |= mask;
  669. value = tegra_sor_readl(sor, sor->soc->regs->pll1);
  670. value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
  671. value |= SOR_PLL1_TMDS_TERMADJ(adj);
  672. tegra_sor_writel(sor, value, sor->soc->regs->pll1);
  673. usleep_range(100, 200);
  674. value = tegra_sor_readl(sor, sor->soc->regs->pll1);
  675. if (value & SOR_PLL1_TERM_COMPOUT)
  676. adj &= ~mask;
  677. mask >>= 1;
  678. }
  679. value = tegra_sor_readl(sor, sor->soc->regs->pll1);
  680. value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
  681. value |= SOR_PLL1_TMDS_TERMADJ(adj);
  682. tegra_sor_writel(sor, value, sor->soc->regs->pll1);
  683. /* disable pad calibration logic */
  684. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  685. value |= SOR_DP_PADCTL_PAD_CAL_PD;
  686. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  687. }
  688. static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
  689. {
  690. struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
  691. u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
  692. const struct tegra_sor_soc *soc = sor->soc;
  693. u32 pattern = 0, tx_pu = 0, value;
  694. unsigned int i;
  695. for (value = 0, i = 0; i < link->lanes; i++) {
  696. u8 vs = link->train.request.voltage_swing[i];
  697. u8 pe = link->train.request.pre_emphasis[i];
  698. u8 pc = link->train.request.post_cursor[i];
  699. u8 shift = sor->soc->lane_map[i] << 3;
  700. voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
  701. pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
  702. post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
  703. if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
  704. tx_pu = sor->soc->tx_pu[pc][vs][pe];
  705. switch (link->train.pattern) {
  706. case DP_TRAINING_PATTERN_DISABLE:
  707. value = SOR_DP_TPG_SCRAMBLER_GALIOS |
  708. SOR_DP_TPG_PATTERN_NONE;
  709. break;
  710. case DP_TRAINING_PATTERN_1:
  711. value = SOR_DP_TPG_SCRAMBLER_NONE |
  712. SOR_DP_TPG_PATTERN_TRAIN1;
  713. break;
  714. case DP_TRAINING_PATTERN_2:
  715. value = SOR_DP_TPG_SCRAMBLER_NONE |
  716. SOR_DP_TPG_PATTERN_TRAIN2;
  717. break;
  718. case DP_TRAINING_PATTERN_3:
  719. value = SOR_DP_TPG_SCRAMBLER_NONE |
  720. SOR_DP_TPG_PATTERN_TRAIN3;
  721. break;
  722. default:
  723. return -EINVAL;
  724. }
  725. if (link->caps.channel_coding)
  726. value |= SOR_DP_TPG_CHANNEL_CODING;
  727. pattern = pattern << 8 | value;
  728. }
  729. tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
  730. tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
  731. if (link->caps.tps3_supported)
  732. tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
  733. tegra_sor_writel(sor, pattern, SOR_DP_TPG);
  734. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  735. value &= ~SOR_DP_PADCTL_TX_PU_MASK;
  736. value |= SOR_DP_PADCTL_TX_PU_ENABLE;
  737. value |= SOR_DP_PADCTL_TX_PU(tx_pu);
  738. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  739. usleep_range(20, 100);
  740. return 0;
  741. }
  742. static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
  743. {
  744. struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
  745. unsigned int rate, lanes;
  746. u32 value;
  747. int err;
  748. rate = drm_dp_link_rate_to_bw_code(link->rate);
  749. lanes = link->lanes;
  750. /* configure link speed and lane count */
  751. value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
  752. value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
  753. value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
  754. tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
  755. value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
  756. value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
  757. value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
  758. if (link->caps.enhanced_framing)
  759. value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
  760. tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
  761. usleep_range(400, 1000);
  762. /* configure load pulse position adjustment */
  763. value = tegra_sor_readl(sor, sor->soc->regs->pll1);
  764. value &= ~SOR_PLL1_LOADADJ_MASK;
  765. switch (rate) {
  766. case DP_LINK_BW_1_62:
  767. value |= SOR_PLL1_LOADADJ(0x3);
  768. break;
  769. case DP_LINK_BW_2_7:
  770. value |= SOR_PLL1_LOADADJ(0x4);
  771. break;
  772. case DP_LINK_BW_5_4:
  773. value |= SOR_PLL1_LOADADJ(0x6);
  774. break;
  775. }
  776. tegra_sor_writel(sor, value, sor->soc->regs->pll1);
  777. /* use alternate scrambler reset for eDP */
  778. value = tegra_sor_readl(sor, SOR_DP_SPARE0);
  779. if (link->edp == 0)
  780. value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
  781. else
  782. value |= SOR_DP_SPARE_PANEL_INTERNAL;
  783. tegra_sor_writel(sor, value, SOR_DP_SPARE0);
  784. err = tegra_sor_power_down_lanes(sor);
  785. if (err < 0) {
  786. dev_err(sor->dev, "failed to power down lanes: %d\n", err);
  787. return err;
  788. }
  789. /* power up and pre-charge lanes */
  790. err = tegra_sor_power_up_lanes(sor, lanes);
  791. if (err < 0) {
  792. dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
  793. lanes, (lanes != 1) ? "s" : "", err);
  794. return err;
  795. }
  796. tegra_sor_dp_precharge(sor, lanes);
  797. return 0;
  798. }
  799. static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
  800. .apply_training = tegra_sor_dp_link_apply_training,
  801. .configure = tegra_sor_dp_link_configure,
  802. };
  803. static void tegra_sor_super_update(struct tegra_sor *sor)
  804. {
  805. tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
  806. tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
  807. tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
  808. }
  809. static void tegra_sor_update(struct tegra_sor *sor)
  810. {
  811. tegra_sor_writel(sor, 0, SOR_STATE0);
  812. tegra_sor_writel(sor, 1, SOR_STATE0);
  813. tegra_sor_writel(sor, 0, SOR_STATE0);
  814. }
  815. static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
  816. {
  817. u32 value;
  818. value = tegra_sor_readl(sor, SOR_PWM_DIV);
  819. value &= ~SOR_PWM_DIV_MASK;
  820. value |= 0x400; /* period */
  821. tegra_sor_writel(sor, value, SOR_PWM_DIV);
  822. value = tegra_sor_readl(sor, SOR_PWM_CTL);
  823. value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
  824. value |= 0x400; /* duty cycle */
  825. value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
  826. value |= SOR_PWM_CTL_TRIGGER;
  827. tegra_sor_writel(sor, value, SOR_PWM_CTL);
  828. timeout = jiffies + msecs_to_jiffies(timeout);
  829. while (time_before(jiffies, timeout)) {
  830. value = tegra_sor_readl(sor, SOR_PWM_CTL);
  831. if ((value & SOR_PWM_CTL_TRIGGER) == 0)
  832. return 0;
  833. usleep_range(25, 100);
  834. }
  835. return -ETIMEDOUT;
  836. }
  837. static int tegra_sor_attach(struct tegra_sor *sor)
  838. {
  839. unsigned long value, timeout;
  840. /* wake up in normal mode */
  841. value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
  842. value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
  843. value |= SOR_SUPER_STATE_MODE_NORMAL;
  844. tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
  845. tegra_sor_super_update(sor);
  846. /* attach */
  847. value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
  848. value |= SOR_SUPER_STATE_ATTACHED;
  849. tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
  850. tegra_sor_super_update(sor);
  851. timeout = jiffies + msecs_to_jiffies(250);
  852. while (time_before(jiffies, timeout)) {
  853. value = tegra_sor_readl(sor, SOR_TEST);
  854. if ((value & SOR_TEST_ATTACHED) != 0)
  855. return 0;
  856. usleep_range(25, 100);
  857. }
  858. return -ETIMEDOUT;
  859. }
  860. static int tegra_sor_wakeup(struct tegra_sor *sor)
  861. {
  862. unsigned long value, timeout;
  863. timeout = jiffies + msecs_to_jiffies(250);
  864. /* wait for head to wake up */
  865. while (time_before(jiffies, timeout)) {
  866. value = tegra_sor_readl(sor, SOR_TEST);
  867. value &= SOR_TEST_HEAD_MODE_MASK;
  868. if (value == SOR_TEST_HEAD_MODE_AWAKE)
  869. return 0;
  870. usleep_range(25, 100);
  871. }
  872. return -ETIMEDOUT;
  873. }
  874. static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
  875. {
  876. u32 value;
  877. value = tegra_sor_readl(sor, SOR_PWR);
  878. value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
  879. tegra_sor_writel(sor, value, SOR_PWR);
  880. timeout = jiffies + msecs_to_jiffies(timeout);
  881. while (time_before(jiffies, timeout)) {
  882. value = tegra_sor_readl(sor, SOR_PWR);
  883. if ((value & SOR_PWR_TRIGGER) == 0)
  884. return 0;
  885. usleep_range(25, 100);
  886. }
  887. return -ETIMEDOUT;
  888. }
  889. struct tegra_sor_params {
  890. /* number of link clocks per line */
  891. unsigned int num_clocks;
  892. /* ratio between input and output */
  893. u64 ratio;
  894. /* precision factor */
  895. u64 precision;
  896. unsigned int active_polarity;
  897. unsigned int active_count;
  898. unsigned int active_frac;
  899. unsigned int tu_size;
  900. unsigned int error;
  901. };
  902. static int tegra_sor_compute_params(struct tegra_sor *sor,
  903. struct tegra_sor_params *params,
  904. unsigned int tu_size)
  905. {
  906. u64 active_sym, active_count, frac, approx;
  907. u32 active_polarity, active_frac = 0;
  908. const u64 f = params->precision;
  909. s64 error;
  910. active_sym = params->ratio * tu_size;
  911. active_count = div_u64(active_sym, f) * f;
  912. frac = active_sym - active_count;
  913. /* fraction < 0.5 */
  914. if (frac >= (f / 2)) {
  915. active_polarity = 1;
  916. frac = f - frac;
  917. } else {
  918. active_polarity = 0;
  919. }
  920. if (frac != 0) {
  921. frac = div_u64(f * f, frac); /* 1/fraction */
  922. if (frac <= (15 * f)) {
  923. active_frac = div_u64(frac, f);
  924. /* round up */
  925. if (active_polarity)
  926. active_frac++;
  927. } else {
  928. active_frac = active_polarity ? 1 : 15;
  929. }
  930. }
  931. if (active_frac == 1)
  932. active_polarity = 0;
  933. if (active_polarity == 1) {
  934. if (active_frac) {
  935. approx = active_count + (active_frac * (f - 1)) * f;
  936. approx = div_u64(approx, active_frac * f);
  937. } else {
  938. approx = active_count + f;
  939. }
  940. } else {
  941. if (active_frac)
  942. approx = active_count + div_u64(f, active_frac);
  943. else
  944. approx = active_count;
  945. }
  946. error = div_s64(active_sym - approx, tu_size);
  947. error *= params->num_clocks;
  948. if (error <= 0 && abs(error) < params->error) {
  949. params->active_count = div_u64(active_count, f);
  950. params->active_polarity = active_polarity;
  951. params->active_frac = active_frac;
  952. params->error = abs(error);
  953. params->tu_size = tu_size;
  954. if (error == 0)
  955. return true;
  956. }
  957. return false;
  958. }
  959. static int tegra_sor_compute_config(struct tegra_sor *sor,
  960. const struct drm_display_mode *mode,
  961. struct tegra_sor_config *config,
  962. struct drm_dp_link *link)
  963. {
  964. const u64 f = 100000, link_rate = link->rate * 1000;
  965. const u64 pclk = mode->clock * 1000;
  966. u64 input, output, watermark, num;
  967. struct tegra_sor_params params;
  968. u32 num_syms_per_line;
  969. unsigned int i;
  970. if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
  971. return -EINVAL;
  972. input = pclk * config->bits_per_pixel;
  973. output = link_rate * 8 * link->lanes;
  974. if (input >= output)
  975. return -ERANGE;
  976. memset(&params, 0, sizeof(params));
  977. params.ratio = div64_u64(input * f, output);
  978. params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
  979. params.precision = f;
  980. params.error = 64 * f;
  981. params.tu_size = 64;
  982. for (i = params.tu_size; i >= 32; i--)
  983. if (tegra_sor_compute_params(sor, &params, i))
  984. break;
  985. if (params.active_frac == 0) {
  986. config->active_polarity = 0;
  987. config->active_count = params.active_count;
  988. if (!params.active_polarity)
  989. config->active_count--;
  990. config->tu_size = params.tu_size;
  991. config->active_frac = 1;
  992. } else {
  993. config->active_polarity = params.active_polarity;
  994. config->active_count = params.active_count;
  995. config->active_frac = params.active_frac;
  996. config->tu_size = params.tu_size;
  997. }
  998. dev_dbg(sor->dev,
  999. "polarity: %d active count: %d tu size: %d active frac: %d\n",
  1000. config->active_polarity, config->active_count,
  1001. config->tu_size, config->active_frac);
  1002. watermark = params.ratio * config->tu_size * (f - params.ratio);
  1003. watermark = div_u64(watermark, f);
  1004. watermark = div_u64(watermark + params.error, f);
  1005. config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
  1006. num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
  1007. (link->lanes * 8);
  1008. if (config->watermark > 30) {
  1009. config->watermark = 30;
  1010. dev_err(sor->dev,
  1011. "unable to compute TU size, forcing watermark to %u\n",
  1012. config->watermark);
  1013. } else if (config->watermark > num_syms_per_line) {
  1014. config->watermark = num_syms_per_line;
  1015. dev_err(sor->dev, "watermark too high, forcing to %u\n",
  1016. config->watermark);
  1017. }
  1018. /* compute the number of symbols per horizontal blanking interval */
  1019. num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
  1020. config->hblank_symbols = div_u64(num, pclk);
  1021. if (link->caps.enhanced_framing)
  1022. config->hblank_symbols -= 3;
  1023. config->hblank_symbols -= 12 / link->lanes;
  1024. /* compute the number of symbols per vertical blanking interval */
  1025. num = (mode->hdisplay - 25) * link_rate;
  1026. config->vblank_symbols = div_u64(num, pclk);
  1027. config->vblank_symbols -= 36 / link->lanes + 4;
  1028. dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
  1029. config->vblank_symbols);
  1030. return 0;
  1031. }
  1032. static void tegra_sor_apply_config(struct tegra_sor *sor,
  1033. const struct tegra_sor_config *config)
  1034. {
  1035. u32 value;
  1036. value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
  1037. value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
  1038. value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
  1039. tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
  1040. value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
  1041. value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
  1042. value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
  1043. value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
  1044. value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
  1045. value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
  1046. value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
  1047. if (config->active_polarity)
  1048. value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
  1049. else
  1050. value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
  1051. value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
  1052. value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
  1053. tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
  1054. value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
  1055. value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
  1056. value |= config->hblank_symbols & 0xffff;
  1057. tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
  1058. value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
  1059. value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
  1060. value |= config->vblank_symbols & 0xffff;
  1061. tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
  1062. }
  1063. static void tegra_sor_mode_set(struct tegra_sor *sor,
  1064. const struct drm_display_mode *mode,
  1065. struct tegra_sor_state *state)
  1066. {
  1067. struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
  1068. unsigned int vbe, vse, hbe, hse, vbs, hbs;
  1069. u32 value;
  1070. value = tegra_sor_readl(sor, SOR_STATE1);
  1071. value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
  1072. value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
  1073. value &= ~SOR_STATE_ASY_OWNER_MASK;
  1074. value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
  1075. SOR_STATE_ASY_OWNER(dc->pipe + 1);
  1076. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  1077. value &= ~SOR_STATE_ASY_HSYNCPOL;
  1078. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  1079. value |= SOR_STATE_ASY_HSYNCPOL;
  1080. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  1081. value &= ~SOR_STATE_ASY_VSYNCPOL;
  1082. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  1083. value |= SOR_STATE_ASY_VSYNCPOL;
  1084. switch (state->bpc) {
  1085. case 16:
  1086. value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
  1087. break;
  1088. case 12:
  1089. value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
  1090. break;
  1091. case 10:
  1092. value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
  1093. break;
  1094. case 8:
  1095. value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
  1096. break;
  1097. case 6:
  1098. value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
  1099. break;
  1100. default:
  1101. value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
  1102. break;
  1103. }
  1104. tegra_sor_writel(sor, value, SOR_STATE1);
  1105. /*
  1106. * TODO: The video timing programming below doesn't seem to match the
  1107. * register definitions.
  1108. */
  1109. value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
  1110. tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
  1111. /* sync end = sync width - 1 */
  1112. vse = mode->vsync_end - mode->vsync_start - 1;
  1113. hse = mode->hsync_end - mode->hsync_start - 1;
  1114. value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
  1115. tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
  1116. /* blank end = sync end + back porch */
  1117. vbe = vse + (mode->vtotal - mode->vsync_end);
  1118. hbe = hse + (mode->htotal - mode->hsync_end);
  1119. value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
  1120. tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
  1121. /* blank start = blank end + active */
  1122. vbs = vbe + mode->vdisplay;
  1123. hbs = hbe + mode->hdisplay;
  1124. value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
  1125. tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
  1126. /* XXX interlacing support */
  1127. tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
  1128. }
  1129. static int tegra_sor_detach(struct tegra_sor *sor)
  1130. {
  1131. unsigned long value, timeout;
  1132. /* switch to safe mode */
  1133. value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
  1134. value &= ~SOR_SUPER_STATE_MODE_NORMAL;
  1135. tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
  1136. tegra_sor_super_update(sor);
  1137. timeout = jiffies + msecs_to_jiffies(250);
  1138. while (time_before(jiffies, timeout)) {
  1139. value = tegra_sor_readl(sor, SOR_PWR);
  1140. if (value & SOR_PWR_MODE_SAFE)
  1141. break;
  1142. }
  1143. if ((value & SOR_PWR_MODE_SAFE) == 0)
  1144. return -ETIMEDOUT;
  1145. /* go to sleep */
  1146. value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
  1147. value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
  1148. tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
  1149. tegra_sor_super_update(sor);
  1150. /* detach */
  1151. value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
  1152. value &= ~SOR_SUPER_STATE_ATTACHED;
  1153. tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
  1154. tegra_sor_super_update(sor);
  1155. timeout = jiffies + msecs_to_jiffies(250);
  1156. while (time_before(jiffies, timeout)) {
  1157. value = tegra_sor_readl(sor, SOR_TEST);
  1158. if ((value & SOR_TEST_ATTACHED) == 0)
  1159. break;
  1160. usleep_range(25, 100);
  1161. }
  1162. if ((value & SOR_TEST_ATTACHED) != 0)
  1163. return -ETIMEDOUT;
  1164. return 0;
  1165. }
  1166. static int tegra_sor_power_down(struct tegra_sor *sor)
  1167. {
  1168. unsigned long value, timeout;
  1169. int err;
  1170. value = tegra_sor_readl(sor, SOR_PWR);
  1171. value &= ~SOR_PWR_NORMAL_STATE_PU;
  1172. value |= SOR_PWR_TRIGGER;
  1173. tegra_sor_writel(sor, value, SOR_PWR);
  1174. timeout = jiffies + msecs_to_jiffies(250);
  1175. while (time_before(jiffies, timeout)) {
  1176. value = tegra_sor_readl(sor, SOR_PWR);
  1177. if ((value & SOR_PWR_TRIGGER) == 0)
  1178. return 0;
  1179. usleep_range(25, 100);
  1180. }
  1181. if ((value & SOR_PWR_TRIGGER) != 0)
  1182. return -ETIMEDOUT;
  1183. /* switch to safe parent clock */
  1184. err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
  1185. if (err < 0) {
  1186. dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
  1187. return err;
  1188. }
  1189. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  1190. value |= SOR_PLL2_PORT_POWERDOWN;
  1191. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  1192. usleep_range(20, 100);
  1193. value = tegra_sor_readl(sor, sor->soc->regs->pll0);
  1194. value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
  1195. tegra_sor_writel(sor, value, sor->soc->regs->pll0);
  1196. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  1197. value |= SOR_PLL2_SEQ_PLLCAPPD;
  1198. value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
  1199. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  1200. usleep_range(20, 100);
  1201. return 0;
  1202. }
  1203. static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
  1204. {
  1205. u32 value;
  1206. timeout = jiffies + msecs_to_jiffies(timeout);
  1207. while (time_before(jiffies, timeout)) {
  1208. value = tegra_sor_readl(sor, SOR_CRCA);
  1209. if (value & SOR_CRCA_VALID)
  1210. return 0;
  1211. usleep_range(100, 200);
  1212. }
  1213. return -ETIMEDOUT;
  1214. }
  1215. static int tegra_sor_show_crc(struct seq_file *s, void *data)
  1216. {
  1217. struct drm_info_node *node = s->private;
  1218. struct tegra_sor *sor = node->info_ent->data;
  1219. struct drm_crtc *crtc = sor->output.encoder.crtc;
  1220. struct drm_device *drm = node->minor->dev;
  1221. int err = 0;
  1222. u32 value;
  1223. drm_modeset_lock_all(drm);
  1224. if (!crtc || !crtc->state->active) {
  1225. err = -EBUSY;
  1226. goto unlock;
  1227. }
  1228. value = tegra_sor_readl(sor, SOR_STATE1);
  1229. value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
  1230. tegra_sor_writel(sor, value, SOR_STATE1);
  1231. value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
  1232. value |= SOR_CRC_CNTRL_ENABLE;
  1233. tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
  1234. value = tegra_sor_readl(sor, SOR_TEST);
  1235. value &= ~SOR_TEST_CRC_POST_SERIALIZE;
  1236. tegra_sor_writel(sor, value, SOR_TEST);
  1237. err = tegra_sor_crc_wait(sor, 100);
  1238. if (err < 0)
  1239. goto unlock;
  1240. tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
  1241. value = tegra_sor_readl(sor, SOR_CRCB);
  1242. seq_printf(s, "%08x\n", value);
  1243. unlock:
  1244. drm_modeset_unlock_all(drm);
  1245. return err;
  1246. }
  1247. #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
  1248. static const struct debugfs_reg32 tegra_sor_regs[] = {
  1249. DEBUGFS_REG32(SOR_CTXSW),
  1250. DEBUGFS_REG32(SOR_SUPER_STATE0),
  1251. DEBUGFS_REG32(SOR_SUPER_STATE1),
  1252. DEBUGFS_REG32(SOR_STATE0),
  1253. DEBUGFS_REG32(SOR_STATE1),
  1254. DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
  1255. DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
  1256. DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
  1257. DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
  1258. DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
  1259. DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
  1260. DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
  1261. DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
  1262. DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
  1263. DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
  1264. DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
  1265. DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
  1266. DEBUGFS_REG32(SOR_CRC_CNTRL),
  1267. DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
  1268. DEBUGFS_REG32(SOR_CLK_CNTRL),
  1269. DEBUGFS_REG32(SOR_CAP),
  1270. DEBUGFS_REG32(SOR_PWR),
  1271. DEBUGFS_REG32(SOR_TEST),
  1272. DEBUGFS_REG32(SOR_PLL0),
  1273. DEBUGFS_REG32(SOR_PLL1),
  1274. DEBUGFS_REG32(SOR_PLL2),
  1275. DEBUGFS_REG32(SOR_PLL3),
  1276. DEBUGFS_REG32(SOR_CSTM),
  1277. DEBUGFS_REG32(SOR_LVDS),
  1278. DEBUGFS_REG32(SOR_CRCA),
  1279. DEBUGFS_REG32(SOR_CRCB),
  1280. DEBUGFS_REG32(SOR_BLANK),
  1281. DEBUGFS_REG32(SOR_SEQ_CTL),
  1282. DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
  1283. DEBUGFS_REG32(SOR_SEQ_INST(0)),
  1284. DEBUGFS_REG32(SOR_SEQ_INST(1)),
  1285. DEBUGFS_REG32(SOR_SEQ_INST(2)),
  1286. DEBUGFS_REG32(SOR_SEQ_INST(3)),
  1287. DEBUGFS_REG32(SOR_SEQ_INST(4)),
  1288. DEBUGFS_REG32(SOR_SEQ_INST(5)),
  1289. DEBUGFS_REG32(SOR_SEQ_INST(6)),
  1290. DEBUGFS_REG32(SOR_SEQ_INST(7)),
  1291. DEBUGFS_REG32(SOR_SEQ_INST(8)),
  1292. DEBUGFS_REG32(SOR_SEQ_INST(9)),
  1293. DEBUGFS_REG32(SOR_SEQ_INST(10)),
  1294. DEBUGFS_REG32(SOR_SEQ_INST(11)),
  1295. DEBUGFS_REG32(SOR_SEQ_INST(12)),
  1296. DEBUGFS_REG32(SOR_SEQ_INST(13)),
  1297. DEBUGFS_REG32(SOR_SEQ_INST(14)),
  1298. DEBUGFS_REG32(SOR_SEQ_INST(15)),
  1299. DEBUGFS_REG32(SOR_PWM_DIV),
  1300. DEBUGFS_REG32(SOR_PWM_CTL),
  1301. DEBUGFS_REG32(SOR_VCRC_A0),
  1302. DEBUGFS_REG32(SOR_VCRC_A1),
  1303. DEBUGFS_REG32(SOR_VCRC_B0),
  1304. DEBUGFS_REG32(SOR_VCRC_B1),
  1305. DEBUGFS_REG32(SOR_CCRC_A0),
  1306. DEBUGFS_REG32(SOR_CCRC_A1),
  1307. DEBUGFS_REG32(SOR_CCRC_B0),
  1308. DEBUGFS_REG32(SOR_CCRC_B1),
  1309. DEBUGFS_REG32(SOR_EDATA_A0),
  1310. DEBUGFS_REG32(SOR_EDATA_A1),
  1311. DEBUGFS_REG32(SOR_EDATA_B0),
  1312. DEBUGFS_REG32(SOR_EDATA_B1),
  1313. DEBUGFS_REG32(SOR_COUNT_A0),
  1314. DEBUGFS_REG32(SOR_COUNT_A1),
  1315. DEBUGFS_REG32(SOR_COUNT_B0),
  1316. DEBUGFS_REG32(SOR_COUNT_B1),
  1317. DEBUGFS_REG32(SOR_DEBUG_A0),
  1318. DEBUGFS_REG32(SOR_DEBUG_A1),
  1319. DEBUGFS_REG32(SOR_DEBUG_B0),
  1320. DEBUGFS_REG32(SOR_DEBUG_B1),
  1321. DEBUGFS_REG32(SOR_TRIG),
  1322. DEBUGFS_REG32(SOR_MSCHECK),
  1323. DEBUGFS_REG32(SOR_XBAR_CTRL),
  1324. DEBUGFS_REG32(SOR_XBAR_POL),
  1325. DEBUGFS_REG32(SOR_DP_LINKCTL0),
  1326. DEBUGFS_REG32(SOR_DP_LINKCTL1),
  1327. DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
  1328. DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
  1329. DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
  1330. DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
  1331. DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
  1332. DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
  1333. DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
  1334. DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
  1335. DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
  1336. DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
  1337. DEBUGFS_REG32(SOR_DP_CONFIG0),
  1338. DEBUGFS_REG32(SOR_DP_CONFIG1),
  1339. DEBUGFS_REG32(SOR_DP_MN0),
  1340. DEBUGFS_REG32(SOR_DP_MN1),
  1341. DEBUGFS_REG32(SOR_DP_PADCTL0),
  1342. DEBUGFS_REG32(SOR_DP_PADCTL1),
  1343. DEBUGFS_REG32(SOR_DP_PADCTL2),
  1344. DEBUGFS_REG32(SOR_DP_DEBUG0),
  1345. DEBUGFS_REG32(SOR_DP_DEBUG1),
  1346. DEBUGFS_REG32(SOR_DP_SPARE0),
  1347. DEBUGFS_REG32(SOR_DP_SPARE1),
  1348. DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
  1349. DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
  1350. DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
  1351. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
  1352. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
  1353. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
  1354. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
  1355. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
  1356. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
  1357. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
  1358. DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
  1359. DEBUGFS_REG32(SOR_DP_TPG),
  1360. DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
  1361. DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
  1362. DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
  1363. DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
  1364. };
  1365. static int tegra_sor_show_regs(struct seq_file *s, void *data)
  1366. {
  1367. struct drm_info_node *node = s->private;
  1368. struct tegra_sor *sor = node->info_ent->data;
  1369. struct drm_crtc *crtc = sor->output.encoder.crtc;
  1370. struct drm_device *drm = node->minor->dev;
  1371. unsigned int i;
  1372. int err = 0;
  1373. drm_modeset_lock_all(drm);
  1374. if (!crtc || !crtc->state->active) {
  1375. err = -EBUSY;
  1376. goto unlock;
  1377. }
  1378. for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
  1379. unsigned int offset = tegra_sor_regs[i].offset;
  1380. seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
  1381. offset, tegra_sor_readl(sor, offset));
  1382. }
  1383. unlock:
  1384. drm_modeset_unlock_all(drm);
  1385. return err;
  1386. }
  1387. static const struct drm_info_list debugfs_files[] = {
  1388. { "crc", tegra_sor_show_crc, 0, NULL },
  1389. { "regs", tegra_sor_show_regs, 0, NULL },
  1390. };
  1391. static int tegra_sor_late_register(struct drm_connector *connector)
  1392. {
  1393. struct tegra_output *output = connector_to_output(connector);
  1394. unsigned int i, count = ARRAY_SIZE(debugfs_files);
  1395. struct drm_minor *minor = connector->dev->primary;
  1396. struct dentry *root = connector->debugfs_entry;
  1397. struct tegra_sor *sor = to_sor(output);
  1398. sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
  1399. GFP_KERNEL);
  1400. if (!sor->debugfs_files)
  1401. return -ENOMEM;
  1402. for (i = 0; i < count; i++)
  1403. sor->debugfs_files[i].data = sor;
  1404. drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
  1405. return 0;
  1406. }
  1407. static void tegra_sor_early_unregister(struct drm_connector *connector)
  1408. {
  1409. struct tegra_output *output = connector_to_output(connector);
  1410. unsigned int count = ARRAY_SIZE(debugfs_files);
  1411. struct tegra_sor *sor = to_sor(output);
  1412. drm_debugfs_remove_files(sor->debugfs_files, count,
  1413. connector->dev->primary);
  1414. kfree(sor->debugfs_files);
  1415. sor->debugfs_files = NULL;
  1416. }
  1417. static void tegra_sor_connector_reset(struct drm_connector *connector)
  1418. {
  1419. struct tegra_sor_state *state;
  1420. state = kzalloc(sizeof(*state), GFP_KERNEL);
  1421. if (!state)
  1422. return;
  1423. if (connector->state) {
  1424. __drm_atomic_helper_connector_destroy_state(connector->state);
  1425. kfree(connector->state);
  1426. }
  1427. __drm_atomic_helper_connector_reset(connector, &state->base);
  1428. }
  1429. static enum drm_connector_status
  1430. tegra_sor_connector_detect(struct drm_connector *connector, bool force)
  1431. {
  1432. struct tegra_output *output = connector_to_output(connector);
  1433. struct tegra_sor *sor = to_sor(output);
  1434. if (sor->aux)
  1435. return drm_dp_aux_detect(sor->aux);
  1436. return tegra_output_connector_detect(connector, force);
  1437. }
  1438. static struct drm_connector_state *
  1439. tegra_sor_connector_duplicate_state(struct drm_connector *connector)
  1440. {
  1441. struct tegra_sor_state *state = to_sor_state(connector->state);
  1442. struct tegra_sor_state *copy;
  1443. copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
  1444. if (!copy)
  1445. return NULL;
  1446. __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
  1447. return &copy->base;
  1448. }
  1449. static const struct drm_connector_funcs tegra_sor_connector_funcs = {
  1450. .reset = tegra_sor_connector_reset,
  1451. .detect = tegra_sor_connector_detect,
  1452. .fill_modes = drm_helper_probe_single_connector_modes,
  1453. .destroy = tegra_output_connector_destroy,
  1454. .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
  1455. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  1456. .late_register = tegra_sor_late_register,
  1457. .early_unregister = tegra_sor_early_unregister,
  1458. };
  1459. static int tegra_sor_connector_get_modes(struct drm_connector *connector)
  1460. {
  1461. struct tegra_output *output = connector_to_output(connector);
  1462. struct tegra_sor *sor = to_sor(output);
  1463. int err;
  1464. if (sor->aux)
  1465. drm_dp_aux_enable(sor->aux);
  1466. err = tegra_output_connector_get_modes(connector);
  1467. if (sor->aux)
  1468. drm_dp_aux_disable(sor->aux);
  1469. return err;
  1470. }
  1471. static enum drm_mode_status
  1472. tegra_sor_connector_mode_valid(struct drm_connector *connector,
  1473. struct drm_display_mode *mode)
  1474. {
  1475. return MODE_OK;
  1476. }
  1477. static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
  1478. .get_modes = tegra_sor_connector_get_modes,
  1479. .mode_valid = tegra_sor_connector_mode_valid,
  1480. };
  1481. static int
  1482. tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
  1483. struct drm_crtc_state *crtc_state,
  1484. struct drm_connector_state *conn_state)
  1485. {
  1486. struct tegra_output *output = encoder_to_output(encoder);
  1487. struct tegra_sor_state *state = to_sor_state(conn_state);
  1488. struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
  1489. unsigned long pclk = crtc_state->mode.clock * 1000;
  1490. struct tegra_sor *sor = to_sor(output);
  1491. struct drm_display_info *info;
  1492. int err;
  1493. info = &output->connector.display_info;
  1494. /*
  1495. * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
  1496. * the pixel clock must be corrected accordingly.
  1497. */
  1498. if (pclk >= 340000000) {
  1499. state->link_speed = 20;
  1500. state->pclk = pclk / 2;
  1501. } else {
  1502. state->link_speed = 10;
  1503. state->pclk = pclk;
  1504. }
  1505. err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
  1506. pclk, 0);
  1507. if (err < 0) {
  1508. dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
  1509. return err;
  1510. }
  1511. switch (info->bpc) {
  1512. case 8:
  1513. case 6:
  1514. state->bpc = info->bpc;
  1515. break;
  1516. default:
  1517. DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
  1518. state->bpc = 8;
  1519. break;
  1520. }
  1521. return 0;
  1522. }
  1523. static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
  1524. {
  1525. u32 value = 0;
  1526. size_t i;
  1527. for (i = size; i > 0; i--)
  1528. value = (value << 8) | ptr[i - 1];
  1529. return value;
  1530. }
  1531. static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
  1532. const void *data, size_t size)
  1533. {
  1534. const u8 *ptr = data;
  1535. unsigned long offset;
  1536. size_t i, j;
  1537. u32 value;
  1538. switch (ptr[0]) {
  1539. case HDMI_INFOFRAME_TYPE_AVI:
  1540. offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
  1541. break;
  1542. case HDMI_INFOFRAME_TYPE_AUDIO:
  1543. offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
  1544. break;
  1545. case HDMI_INFOFRAME_TYPE_VENDOR:
  1546. offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
  1547. break;
  1548. default:
  1549. dev_err(sor->dev, "unsupported infoframe type: %02x\n",
  1550. ptr[0]);
  1551. return;
  1552. }
  1553. value = INFOFRAME_HEADER_TYPE(ptr[0]) |
  1554. INFOFRAME_HEADER_VERSION(ptr[1]) |
  1555. INFOFRAME_HEADER_LEN(ptr[2]);
  1556. tegra_sor_writel(sor, value, offset);
  1557. offset++;
  1558. /*
  1559. * Each subpack contains 7 bytes, divided into:
  1560. * - subpack_low: bytes 0 - 3
  1561. * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
  1562. */
  1563. for (i = 3, j = 0; i < size; i += 7, j += 8) {
  1564. size_t rem = size - i, num = min_t(size_t, rem, 4);
  1565. value = tegra_sor_hdmi_subpack(&ptr[i], num);
  1566. tegra_sor_writel(sor, value, offset++);
  1567. num = min_t(size_t, rem - num, 3);
  1568. value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
  1569. tegra_sor_writel(sor, value, offset++);
  1570. }
  1571. }
  1572. static int
  1573. tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
  1574. const struct drm_display_mode *mode)
  1575. {
  1576. u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  1577. struct hdmi_avi_infoframe frame;
  1578. u32 value;
  1579. int err;
  1580. /* disable AVI infoframe */
  1581. value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
  1582. value &= ~INFOFRAME_CTRL_SINGLE;
  1583. value &= ~INFOFRAME_CTRL_OTHER;
  1584. value &= ~INFOFRAME_CTRL_ENABLE;
  1585. tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
  1586. err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
  1587. &sor->output.connector, mode);
  1588. if (err < 0) {
  1589. dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
  1590. return err;
  1591. }
  1592. err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  1593. if (err < 0) {
  1594. dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
  1595. return err;
  1596. }
  1597. tegra_sor_hdmi_write_infopack(sor, buffer, err);
  1598. /* enable AVI infoframe */
  1599. value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
  1600. value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
  1601. value |= INFOFRAME_CTRL_ENABLE;
  1602. tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
  1603. return 0;
  1604. }
  1605. static void tegra_sor_write_eld(struct tegra_sor *sor)
  1606. {
  1607. size_t length = drm_eld_size(sor->output.connector.eld), i;
  1608. for (i = 0; i < length; i++)
  1609. tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
  1610. SOR_AUDIO_HDA_ELD_BUFWR);
  1611. /*
  1612. * The HDA codec will always report an ELD buffer size of 96 bytes and
  1613. * the HDA codec driver will check that each byte read from the buffer
  1614. * is valid. Therefore every byte must be written, even if no 96 bytes
  1615. * were parsed from EDID.
  1616. */
  1617. for (i = length; i < 96; i++)
  1618. tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
  1619. }
  1620. static void tegra_sor_audio_prepare(struct tegra_sor *sor)
  1621. {
  1622. u32 value;
  1623. /*
  1624. * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
  1625. * is used for interoperability between the HDA codec driver and the
  1626. * HDMI/DP driver.
  1627. */
  1628. value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
  1629. tegra_sor_writel(sor, value, SOR_INT_ENABLE);
  1630. tegra_sor_writel(sor, value, SOR_INT_MASK);
  1631. tegra_sor_write_eld(sor);
  1632. value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
  1633. tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
  1634. }
  1635. static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
  1636. {
  1637. tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
  1638. tegra_sor_writel(sor, 0, SOR_INT_MASK);
  1639. tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
  1640. }
  1641. static void tegra_sor_audio_enable(struct tegra_sor *sor)
  1642. {
  1643. u32 value;
  1644. value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
  1645. /* select HDA audio input */
  1646. value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
  1647. value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
  1648. /* inject null samples */
  1649. if (sor->format.channels != 2)
  1650. value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
  1651. else
  1652. value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
  1653. value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
  1654. tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
  1655. /* enable advertising HBR capability */
  1656. tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
  1657. }
  1658. static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
  1659. {
  1660. u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
  1661. struct hdmi_audio_infoframe frame;
  1662. u32 value;
  1663. int err;
  1664. err = hdmi_audio_infoframe_init(&frame);
  1665. if (err < 0) {
  1666. dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
  1667. return err;
  1668. }
  1669. frame.channels = sor->format.channels;
  1670. err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
  1671. if (err < 0) {
  1672. dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
  1673. return err;
  1674. }
  1675. tegra_sor_hdmi_write_infopack(sor, buffer, err);
  1676. value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
  1677. value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
  1678. value |= INFOFRAME_CTRL_ENABLE;
  1679. tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
  1680. return 0;
  1681. }
  1682. static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
  1683. {
  1684. u32 value;
  1685. tegra_sor_audio_enable(sor);
  1686. tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
  1687. value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
  1688. SOR_HDMI_SPARE_CTS_RESET(1) |
  1689. SOR_HDMI_SPARE_HW_CTS_ENABLE;
  1690. tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
  1691. /* enable HW CTS */
  1692. value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
  1693. tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
  1694. /* allow packet to be sent */
  1695. value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
  1696. tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
  1697. /* reset N counter and enable lookup */
  1698. value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
  1699. tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
  1700. value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
  1701. tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
  1702. tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
  1703. tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
  1704. tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
  1705. tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
  1706. tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
  1707. tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
  1708. tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
  1709. value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
  1710. tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
  1711. tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
  1712. value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
  1713. tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
  1714. tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
  1715. value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
  1716. tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
  1717. tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
  1718. value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
  1719. value &= ~SOR_HDMI_AUDIO_N_RESET;
  1720. tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
  1721. tegra_sor_hdmi_enable_audio_infoframe(sor);
  1722. }
  1723. static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
  1724. {
  1725. u32 value;
  1726. value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
  1727. value &= ~INFOFRAME_CTRL_ENABLE;
  1728. tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
  1729. }
  1730. static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
  1731. {
  1732. tegra_sor_hdmi_disable_audio_infoframe(sor);
  1733. }
  1734. static struct tegra_sor_hdmi_settings *
  1735. tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
  1736. {
  1737. unsigned int i;
  1738. for (i = 0; i < sor->num_settings; i++)
  1739. if (frequency <= sor->settings[i].frequency)
  1740. return &sor->settings[i];
  1741. return NULL;
  1742. }
  1743. static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
  1744. {
  1745. u32 value;
  1746. value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
  1747. value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
  1748. value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
  1749. tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
  1750. }
  1751. static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
  1752. {
  1753. struct i2c_adapter *ddc = sor->output.ddc;
  1754. drm_scdc_set_high_tmds_clock_ratio(ddc, false);
  1755. drm_scdc_set_scrambling(ddc, false);
  1756. tegra_sor_hdmi_disable_scrambling(sor);
  1757. }
  1758. static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
  1759. {
  1760. if (sor->scdc_enabled) {
  1761. cancel_delayed_work_sync(&sor->scdc);
  1762. tegra_sor_hdmi_scdc_disable(sor);
  1763. }
  1764. }
  1765. static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
  1766. {
  1767. u32 value;
  1768. value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
  1769. value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
  1770. value |= SOR_HDMI2_CTRL_SCRAMBLE;
  1771. tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
  1772. }
  1773. static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
  1774. {
  1775. struct i2c_adapter *ddc = sor->output.ddc;
  1776. drm_scdc_set_high_tmds_clock_ratio(ddc, true);
  1777. drm_scdc_set_scrambling(ddc, true);
  1778. tegra_sor_hdmi_enable_scrambling(sor);
  1779. }
  1780. static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
  1781. {
  1782. struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
  1783. struct i2c_adapter *ddc = sor->output.ddc;
  1784. if (!drm_scdc_get_scrambling_status(ddc)) {
  1785. DRM_DEBUG_KMS("SCDC not scrambled\n");
  1786. tegra_sor_hdmi_scdc_enable(sor);
  1787. }
  1788. schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
  1789. }
  1790. static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
  1791. {
  1792. struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
  1793. struct drm_display_mode *mode;
  1794. mode = &sor->output.encoder.crtc->state->adjusted_mode;
  1795. if (mode->clock >= 340000 && scdc->supported) {
  1796. schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
  1797. tegra_sor_hdmi_scdc_enable(sor);
  1798. sor->scdc_enabled = true;
  1799. }
  1800. }
  1801. static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
  1802. {
  1803. struct tegra_output *output = encoder_to_output(encoder);
  1804. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  1805. struct tegra_sor *sor = to_sor(output);
  1806. u32 value;
  1807. int err;
  1808. tegra_sor_audio_unprepare(sor);
  1809. tegra_sor_hdmi_scdc_stop(sor);
  1810. err = tegra_sor_detach(sor);
  1811. if (err < 0)
  1812. dev_err(sor->dev, "failed to detach SOR: %d\n", err);
  1813. tegra_sor_writel(sor, 0, SOR_STATE1);
  1814. tegra_sor_update(sor);
  1815. /* disable display to SOR clock */
  1816. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  1817. if (!sor->soc->has_nvdisplay)
  1818. value &= ~SOR1_TIMING_CYA;
  1819. value &= ~SOR_ENABLE(sor->index);
  1820. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  1821. tegra_dc_commit(dc);
  1822. err = tegra_sor_power_down(sor);
  1823. if (err < 0)
  1824. dev_err(sor->dev, "failed to power down SOR: %d\n", err);
  1825. err = tegra_io_pad_power_disable(sor->pad);
  1826. if (err < 0)
  1827. dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
  1828. host1x_client_suspend(&sor->client);
  1829. }
  1830. static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
  1831. {
  1832. struct tegra_output *output = encoder_to_output(encoder);
  1833. unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
  1834. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  1835. struct tegra_sor_hdmi_settings *settings;
  1836. struct tegra_sor *sor = to_sor(output);
  1837. struct tegra_sor_state *state;
  1838. struct drm_display_mode *mode;
  1839. unsigned long rate, pclk;
  1840. unsigned int div, i;
  1841. u32 value;
  1842. int err;
  1843. state = to_sor_state(output->connector.state);
  1844. mode = &encoder->crtc->state->adjusted_mode;
  1845. pclk = mode->clock * 1000;
  1846. err = host1x_client_resume(&sor->client);
  1847. if (err < 0) {
  1848. dev_err(sor->dev, "failed to resume: %d\n", err);
  1849. return;
  1850. }
  1851. /* switch to safe parent clock */
  1852. err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
  1853. if (err < 0) {
  1854. dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
  1855. return;
  1856. }
  1857. div = clk_get_rate(sor->clk) / 1000000 * 4;
  1858. err = tegra_io_pad_power_enable(sor->pad);
  1859. if (err < 0)
  1860. dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
  1861. usleep_range(20, 100);
  1862. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  1863. value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
  1864. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  1865. usleep_range(20, 100);
  1866. value = tegra_sor_readl(sor, sor->soc->regs->pll3);
  1867. value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
  1868. tegra_sor_writel(sor, value, sor->soc->regs->pll3);
  1869. value = tegra_sor_readl(sor, sor->soc->regs->pll0);
  1870. value &= ~SOR_PLL0_VCOPD;
  1871. value &= ~SOR_PLL0_PWR;
  1872. tegra_sor_writel(sor, value, sor->soc->regs->pll0);
  1873. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  1874. value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
  1875. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  1876. usleep_range(200, 400);
  1877. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  1878. value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
  1879. value &= ~SOR_PLL2_PORT_POWERDOWN;
  1880. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  1881. usleep_range(20, 100);
  1882. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  1883. value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
  1884. SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
  1885. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  1886. while (true) {
  1887. value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
  1888. if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
  1889. break;
  1890. usleep_range(250, 1000);
  1891. }
  1892. value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
  1893. SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
  1894. tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
  1895. while (true) {
  1896. value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
  1897. if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
  1898. break;
  1899. usleep_range(250, 1000);
  1900. }
  1901. value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
  1902. value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
  1903. value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
  1904. if (mode->clock < 340000) {
  1905. DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
  1906. value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
  1907. } else {
  1908. DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
  1909. value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
  1910. }
  1911. value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
  1912. tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
  1913. /* SOR pad PLL stabilization time */
  1914. usleep_range(250, 1000);
  1915. value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
  1916. value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
  1917. value |= SOR_DP_LINKCTL_LANE_COUNT(4);
  1918. tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
  1919. value = tegra_sor_readl(sor, SOR_DP_SPARE0);
  1920. value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
  1921. value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
  1922. value &= ~SOR_DP_SPARE_SEQ_ENABLE;
  1923. value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
  1924. tegra_sor_writel(sor, value, SOR_DP_SPARE0);
  1925. value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
  1926. SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
  1927. tegra_sor_writel(sor, value, SOR_SEQ_CTL);
  1928. value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
  1929. SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
  1930. tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
  1931. tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
  1932. if (!sor->soc->has_nvdisplay) {
  1933. /* program the reference clock */
  1934. value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
  1935. tegra_sor_writel(sor, value, SOR_REFCLK);
  1936. }
  1937. /* XXX not in TRM */
  1938. for (value = 0, i = 0; i < 5; i++)
  1939. value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
  1940. SOR_XBAR_CTRL_LINK1_XSEL(i, i);
  1941. tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
  1942. tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
  1943. /*
  1944. * Switch the pad clock to the DP clock. Note that we cannot actually
  1945. * do this because Tegra186 and later don't support clk_set_parent()
  1946. * on the sorX_pad_clkout clocks. We already do the equivalent above
  1947. * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
  1948. */
  1949. #if 0
  1950. err = clk_set_parent(sor->clk_pad, sor->clk_dp);
  1951. if (err < 0) {
  1952. dev_err(sor->dev, "failed to select pad parent clock: %d\n",
  1953. err);
  1954. return;
  1955. }
  1956. #endif
  1957. /* switch the SOR clock to the pad clock */
  1958. err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
  1959. if (err < 0) {
  1960. dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
  1961. err);
  1962. return;
  1963. }
  1964. /* switch the output clock to the parent pixel clock */
  1965. err = clk_set_parent(sor->clk, sor->clk_parent);
  1966. if (err < 0) {
  1967. dev_err(sor->dev, "failed to select output parent clock: %d\n",
  1968. err);
  1969. return;
  1970. }
  1971. /* adjust clock rate for HDMI 2.0 modes */
  1972. rate = clk_get_rate(sor->clk_parent);
  1973. if (mode->clock >= 340000)
  1974. rate /= 2;
  1975. DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
  1976. clk_set_rate(sor->clk, rate);
  1977. if (!sor->soc->has_nvdisplay) {
  1978. value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
  1979. /* XXX is this the proper check? */
  1980. if (mode->clock < 75000)
  1981. value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
  1982. tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
  1983. }
  1984. max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
  1985. value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
  1986. SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
  1987. tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
  1988. if (!dc->soc->has_nvdisplay) {
  1989. /* H_PULSE2 setup */
  1990. pulse_start = h_ref_to_sync +
  1991. (mode->hsync_end - mode->hsync_start) +
  1992. (mode->htotal - mode->hsync_end) - 10;
  1993. value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
  1994. PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
  1995. tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
  1996. value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
  1997. tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
  1998. value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
  1999. value |= H_PULSE2_ENABLE;
  2000. tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
  2001. }
  2002. /* infoframe setup */
  2003. err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
  2004. if (err < 0)
  2005. dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
  2006. /* XXX HDMI audio support not implemented yet */
  2007. tegra_sor_hdmi_disable_audio_infoframe(sor);
  2008. /* use single TMDS protocol */
  2009. value = tegra_sor_readl(sor, SOR_STATE1);
  2010. value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
  2011. value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
  2012. tegra_sor_writel(sor, value, SOR_STATE1);
  2013. /* power up pad calibration */
  2014. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  2015. value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
  2016. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  2017. /* production settings */
  2018. settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
  2019. if (!settings) {
  2020. dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
  2021. mode->clock * 1000);
  2022. return;
  2023. }
  2024. value = tegra_sor_readl(sor, sor->soc->regs->pll0);
  2025. value &= ~SOR_PLL0_ICHPMP_MASK;
  2026. value &= ~SOR_PLL0_FILTER_MASK;
  2027. value &= ~SOR_PLL0_VCOCAP_MASK;
  2028. value |= SOR_PLL0_ICHPMP(settings->ichpmp);
  2029. value |= SOR_PLL0_FILTER(settings->filter);
  2030. value |= SOR_PLL0_VCOCAP(settings->vcocap);
  2031. tegra_sor_writel(sor, value, sor->soc->regs->pll0);
  2032. /* XXX not in TRM */
  2033. value = tegra_sor_readl(sor, sor->soc->regs->pll1);
  2034. value &= ~SOR_PLL1_LOADADJ_MASK;
  2035. value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
  2036. value |= SOR_PLL1_LOADADJ(settings->loadadj);
  2037. value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
  2038. value |= SOR_PLL1_TMDS_TERM;
  2039. tegra_sor_writel(sor, value, sor->soc->regs->pll1);
  2040. value = tegra_sor_readl(sor, sor->soc->regs->pll3);
  2041. value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
  2042. value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
  2043. value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
  2044. value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
  2045. value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
  2046. value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
  2047. value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
  2048. value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
  2049. tegra_sor_writel(sor, value, sor->soc->regs->pll3);
  2050. value = settings->drive_current[3] << 24 |
  2051. settings->drive_current[2] << 16 |
  2052. settings->drive_current[1] << 8 |
  2053. settings->drive_current[0] << 0;
  2054. tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
  2055. value = settings->preemphasis[3] << 24 |
  2056. settings->preemphasis[2] << 16 |
  2057. settings->preemphasis[1] << 8 |
  2058. settings->preemphasis[0] << 0;
  2059. tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
  2060. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  2061. value &= ~SOR_DP_PADCTL_TX_PU_MASK;
  2062. value |= SOR_DP_PADCTL_TX_PU_ENABLE;
  2063. value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
  2064. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  2065. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
  2066. value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
  2067. value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
  2068. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
  2069. /* power down pad calibration */
  2070. value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
  2071. value |= SOR_DP_PADCTL_PAD_CAL_PD;
  2072. tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
  2073. if (!dc->soc->has_nvdisplay) {
  2074. /* miscellaneous display controller settings */
  2075. value = VSYNC_H_POSITION(1);
  2076. tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
  2077. }
  2078. value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
  2079. value &= ~DITHER_CONTROL_MASK;
  2080. value &= ~BASE_COLOR_SIZE_MASK;
  2081. switch (state->bpc) {
  2082. case 6:
  2083. value |= BASE_COLOR_SIZE_666;
  2084. break;
  2085. case 8:
  2086. value |= BASE_COLOR_SIZE_888;
  2087. break;
  2088. case 10:
  2089. value |= BASE_COLOR_SIZE_101010;
  2090. break;
  2091. case 12:
  2092. value |= BASE_COLOR_SIZE_121212;
  2093. break;
  2094. default:
  2095. WARN(1, "%u bits-per-color not supported\n", state->bpc);
  2096. value |= BASE_COLOR_SIZE_888;
  2097. break;
  2098. }
  2099. tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
  2100. /* XXX set display head owner */
  2101. value = tegra_sor_readl(sor, SOR_STATE1);
  2102. value &= ~SOR_STATE_ASY_OWNER_MASK;
  2103. value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
  2104. tegra_sor_writel(sor, value, SOR_STATE1);
  2105. err = tegra_sor_power_up(sor, 250);
  2106. if (err < 0)
  2107. dev_err(sor->dev, "failed to power up SOR: %d\n", err);
  2108. /* configure dynamic range of output */
  2109. value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
  2110. value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
  2111. value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
  2112. tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
  2113. /* configure colorspace */
  2114. value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
  2115. value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
  2116. value |= SOR_HEAD_STATE_COLORSPACE_RGB;
  2117. tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
  2118. tegra_sor_mode_set(sor, mode, state);
  2119. tegra_sor_update(sor);
  2120. /* program preamble timing in SOR (XXX) */
  2121. value = tegra_sor_readl(sor, SOR_DP_SPARE0);
  2122. value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
  2123. tegra_sor_writel(sor, value, SOR_DP_SPARE0);
  2124. err = tegra_sor_attach(sor);
  2125. if (err < 0)
  2126. dev_err(sor->dev, "failed to attach SOR: %d\n", err);
  2127. /* enable display to SOR clock and generate HDMI preamble */
  2128. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  2129. if (!sor->soc->has_nvdisplay)
  2130. value |= SOR1_TIMING_CYA;
  2131. value |= SOR_ENABLE(sor->index);
  2132. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  2133. if (dc->soc->has_nvdisplay) {
  2134. value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
  2135. value &= ~PROTOCOL_MASK;
  2136. value |= PROTOCOL_SINGLE_TMDS_A;
  2137. tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
  2138. }
  2139. tegra_dc_commit(dc);
  2140. err = tegra_sor_wakeup(sor);
  2141. if (err < 0)
  2142. dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
  2143. tegra_sor_hdmi_scdc_start(sor);
  2144. tegra_sor_audio_prepare(sor);
  2145. }
  2146. static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
  2147. .disable = tegra_sor_hdmi_disable,
  2148. .enable = tegra_sor_hdmi_enable,
  2149. .atomic_check = tegra_sor_encoder_atomic_check,
  2150. };
  2151. static void tegra_sor_dp_disable(struct drm_encoder *encoder)
  2152. {
  2153. struct tegra_output *output = encoder_to_output(encoder);
  2154. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  2155. struct tegra_sor *sor = to_sor(output);
  2156. u32 value;
  2157. int err;
  2158. if (output->panel)
  2159. drm_panel_disable(output->panel);
  2160. /*
  2161. * Do not attempt to power down a DP link if we're not connected since
  2162. * the AUX transactions would just be timing out.
  2163. */
  2164. if (output->connector.status != connector_status_disconnected) {
  2165. err = drm_dp_link_power_down(sor->aux, &sor->link);
  2166. if (err < 0)
  2167. dev_err(sor->dev, "failed to power down link: %d\n",
  2168. err);
  2169. }
  2170. err = tegra_sor_detach(sor);
  2171. if (err < 0)
  2172. dev_err(sor->dev, "failed to detach SOR: %d\n", err);
  2173. tegra_sor_writel(sor, 0, SOR_STATE1);
  2174. tegra_sor_update(sor);
  2175. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  2176. value &= ~SOR_ENABLE(sor->index);
  2177. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  2178. tegra_dc_commit(dc);
  2179. value = tegra_sor_readl(sor, SOR_STATE1);
  2180. value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
  2181. value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
  2182. value &= ~SOR_STATE_ASY_OWNER_MASK;
  2183. tegra_sor_writel(sor, value, SOR_STATE1);
  2184. tegra_sor_update(sor);
  2185. /* switch to safe parent clock */
  2186. err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
  2187. if (err < 0)
  2188. dev_err(sor->dev, "failed to set safe clock: %d\n", err);
  2189. err = tegra_sor_power_down(sor);
  2190. if (err < 0)
  2191. dev_err(sor->dev, "failed to power down SOR: %d\n", err);
  2192. err = tegra_io_pad_power_disable(sor->pad);
  2193. if (err < 0)
  2194. dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
  2195. err = drm_dp_aux_disable(sor->aux);
  2196. if (err < 0)
  2197. dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
  2198. if (output->panel)
  2199. drm_panel_unprepare(output->panel);
  2200. host1x_client_suspend(&sor->client);
  2201. }
  2202. static void tegra_sor_dp_enable(struct drm_encoder *encoder)
  2203. {
  2204. struct tegra_output *output = encoder_to_output(encoder);
  2205. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  2206. struct tegra_sor *sor = to_sor(output);
  2207. struct tegra_sor_config config;
  2208. struct tegra_sor_state *state;
  2209. struct drm_display_mode *mode;
  2210. struct drm_display_info *info;
  2211. unsigned int i;
  2212. u32 value;
  2213. int err;
  2214. state = to_sor_state(output->connector.state);
  2215. mode = &encoder->crtc->state->adjusted_mode;
  2216. info = &output->connector.display_info;
  2217. err = host1x_client_resume(&sor->client);
  2218. if (err < 0) {
  2219. dev_err(sor->dev, "failed to resume: %d\n", err);
  2220. return;
  2221. }
  2222. /* switch to safe parent clock */
  2223. err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
  2224. if (err < 0)
  2225. dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
  2226. err = tegra_io_pad_power_enable(sor->pad);
  2227. if (err < 0)
  2228. dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
  2229. usleep_range(20, 100);
  2230. err = drm_dp_aux_enable(sor->aux);
  2231. if (err < 0)
  2232. dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
  2233. err = drm_dp_link_probe(sor->aux, &sor->link);
  2234. if (err < 0)
  2235. dev_err(sor->dev, "failed to probe DP link: %d\n", err);
  2236. tegra_sor_filter_rates(sor);
  2237. err = drm_dp_link_choose(&sor->link, mode, info);
  2238. if (err < 0)
  2239. dev_err(sor->dev, "failed to choose link: %d\n", err);
  2240. if (output->panel)
  2241. drm_panel_prepare(output->panel);
  2242. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  2243. value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
  2244. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  2245. usleep_range(20, 40);
  2246. value = tegra_sor_readl(sor, sor->soc->regs->pll3);
  2247. value |= SOR_PLL3_PLL_VDD_MODE_3V3;
  2248. tegra_sor_writel(sor, value, sor->soc->regs->pll3);
  2249. value = tegra_sor_readl(sor, sor->soc->regs->pll0);
  2250. value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
  2251. tegra_sor_writel(sor, value, sor->soc->regs->pll0);
  2252. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  2253. value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
  2254. value |= SOR_PLL2_SEQ_PLLCAPPD;
  2255. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  2256. usleep_range(200, 400);
  2257. value = tegra_sor_readl(sor, sor->soc->regs->pll2);
  2258. value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
  2259. value &= ~SOR_PLL2_PORT_POWERDOWN;
  2260. tegra_sor_writel(sor, value, sor->soc->regs->pll2);
  2261. value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
  2262. value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
  2263. if (output->panel)
  2264. value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
  2265. else
  2266. value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
  2267. tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
  2268. usleep_range(200, 400);
  2269. value = tegra_sor_readl(sor, SOR_DP_SPARE0);
  2270. /* XXX not in TRM */
  2271. if (output->panel)
  2272. value |= SOR_DP_SPARE_PANEL_INTERNAL;
  2273. else
  2274. value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
  2275. value |= SOR_DP_SPARE_SEQ_ENABLE;
  2276. tegra_sor_writel(sor, value, SOR_DP_SPARE0);
  2277. /* XXX not in TRM */
  2278. tegra_sor_writel(sor, 0, SOR_LVDS);
  2279. value = tegra_sor_readl(sor, sor->soc->regs->pll0);
  2280. value &= ~SOR_PLL0_ICHPMP_MASK;
  2281. value &= ~SOR_PLL0_VCOCAP_MASK;
  2282. value |= SOR_PLL0_ICHPMP(0x1);
  2283. value |= SOR_PLL0_VCOCAP(0x3);
  2284. value |= SOR_PLL0_RESISTOR_EXT;
  2285. tegra_sor_writel(sor, value, sor->soc->regs->pll0);
  2286. /* XXX not in TRM */
  2287. for (value = 0, i = 0; i < 5; i++)
  2288. value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
  2289. SOR_XBAR_CTRL_LINK1_XSEL(i, i);
  2290. tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
  2291. tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
  2292. /*
  2293. * Switch the pad clock to the DP clock. Note that we cannot actually
  2294. * do this because Tegra186 and later don't support clk_set_parent()
  2295. * on the sorX_pad_clkout clocks. We already do the equivalent above
  2296. * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
  2297. */
  2298. #if 0
  2299. err = clk_set_parent(sor->clk_pad, sor->clk_parent);
  2300. if (err < 0) {
  2301. dev_err(sor->dev, "failed to select pad parent clock: %d\n",
  2302. err);
  2303. return;
  2304. }
  2305. #endif
  2306. /* switch the SOR clock to the pad clock */
  2307. err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
  2308. if (err < 0) {
  2309. dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
  2310. err);
  2311. return;
  2312. }
  2313. /* switch the output clock to the parent pixel clock */
  2314. err = clk_set_parent(sor->clk, sor->clk_parent);
  2315. if (err < 0) {
  2316. dev_err(sor->dev, "failed to select output parent clock: %d\n",
  2317. err);
  2318. return;
  2319. }
  2320. /* use DP-A protocol */
  2321. value = tegra_sor_readl(sor, SOR_STATE1);
  2322. value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
  2323. value |= SOR_STATE_ASY_PROTOCOL_DP_A;
  2324. tegra_sor_writel(sor, value, SOR_STATE1);
  2325. /* enable port */
  2326. value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
  2327. value |= SOR_DP_LINKCTL_ENABLE;
  2328. tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
  2329. tegra_sor_dp_term_calibrate(sor);
  2330. err = drm_dp_link_train(&sor->link);
  2331. if (err < 0)
  2332. dev_err(sor->dev, "link training failed: %d\n", err);
  2333. else
  2334. dev_dbg(sor->dev, "link training succeeded\n");
  2335. err = drm_dp_link_power_up(sor->aux, &sor->link);
  2336. if (err < 0)
  2337. dev_err(sor->dev, "failed to power up DP link: %d\n", err);
  2338. /* compute configuration */
  2339. memset(&config, 0, sizeof(config));
  2340. config.bits_per_pixel = state->bpc * 3;
  2341. err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
  2342. if (err < 0)
  2343. dev_err(sor->dev, "failed to compute configuration: %d\n", err);
  2344. tegra_sor_apply_config(sor, &config);
  2345. tegra_sor_mode_set(sor, mode, state);
  2346. if (output->panel) {
  2347. /* CSTM (LVDS, link A/B, upper) */
  2348. value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
  2349. SOR_CSTM_UPPER;
  2350. tegra_sor_writel(sor, value, SOR_CSTM);
  2351. /* PWM setup */
  2352. err = tegra_sor_setup_pwm(sor, 250);
  2353. if (err < 0)
  2354. dev_err(sor->dev, "failed to setup PWM: %d\n", err);
  2355. }
  2356. tegra_sor_update(sor);
  2357. err = tegra_sor_power_up(sor, 250);
  2358. if (err < 0)
  2359. dev_err(sor->dev, "failed to power up SOR: %d\n", err);
  2360. /* attach and wake up */
  2361. err = tegra_sor_attach(sor);
  2362. if (err < 0)
  2363. dev_err(sor->dev, "failed to attach SOR: %d\n", err);
  2364. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  2365. value |= SOR_ENABLE(sor->index);
  2366. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  2367. tegra_dc_commit(dc);
  2368. err = tegra_sor_wakeup(sor);
  2369. if (err < 0)
  2370. dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
  2371. if (output->panel)
  2372. drm_panel_enable(output->panel);
  2373. }
  2374. static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
  2375. .disable = tegra_sor_dp_disable,
  2376. .enable = tegra_sor_dp_enable,
  2377. .atomic_check = tegra_sor_encoder_atomic_check,
  2378. };
  2379. static void tegra_sor_disable_regulator(void *data)
  2380. {
  2381. struct regulator *reg = data;
  2382. regulator_disable(reg);
  2383. }
  2384. static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
  2385. {
  2386. int err;
  2387. err = regulator_enable(reg);
  2388. if (err)
  2389. return err;
  2390. return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
  2391. }
  2392. static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
  2393. {
  2394. int err;
  2395. sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
  2396. if (IS_ERR(sor->avdd_io_supply)) {
  2397. dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
  2398. PTR_ERR(sor->avdd_io_supply));
  2399. return PTR_ERR(sor->avdd_io_supply);
  2400. }
  2401. err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
  2402. if (err < 0) {
  2403. dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
  2404. err);
  2405. return err;
  2406. }
  2407. sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
  2408. if (IS_ERR(sor->vdd_pll_supply)) {
  2409. dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
  2410. PTR_ERR(sor->vdd_pll_supply));
  2411. return PTR_ERR(sor->vdd_pll_supply);
  2412. }
  2413. err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
  2414. if (err < 0) {
  2415. dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
  2416. err);
  2417. return err;
  2418. }
  2419. sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
  2420. if (IS_ERR(sor->hdmi_supply)) {
  2421. dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
  2422. PTR_ERR(sor->hdmi_supply));
  2423. return PTR_ERR(sor->hdmi_supply);
  2424. }
  2425. err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
  2426. if (err < 0) {
  2427. dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
  2428. return err;
  2429. }
  2430. INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
  2431. return 0;
  2432. }
  2433. static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
  2434. .name = "HDMI",
  2435. .probe = tegra_sor_hdmi_probe,
  2436. .audio_enable = tegra_sor_hdmi_audio_enable,
  2437. .audio_disable = tegra_sor_hdmi_audio_disable,
  2438. };
  2439. static int tegra_sor_dp_probe(struct tegra_sor *sor)
  2440. {
  2441. int err;
  2442. sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
  2443. if (IS_ERR(sor->avdd_io_supply))
  2444. return PTR_ERR(sor->avdd_io_supply);
  2445. err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
  2446. if (err < 0)
  2447. return err;
  2448. sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
  2449. if (IS_ERR(sor->vdd_pll_supply))
  2450. return PTR_ERR(sor->vdd_pll_supply);
  2451. err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
  2452. if (err < 0)
  2453. return err;
  2454. return 0;
  2455. }
  2456. static const struct tegra_sor_ops tegra_sor_dp_ops = {
  2457. .name = "DP",
  2458. .probe = tegra_sor_dp_probe,
  2459. };
  2460. static int tegra_sor_init(struct host1x_client *client)
  2461. {
  2462. struct drm_device *drm = dev_get_drvdata(client->host);
  2463. const struct drm_encoder_helper_funcs *helpers = NULL;
  2464. struct tegra_sor *sor = host1x_client_to_sor(client);
  2465. int connector = DRM_MODE_CONNECTOR_Unknown;
  2466. int encoder = DRM_MODE_ENCODER_NONE;
  2467. int err;
  2468. if (!sor->aux) {
  2469. if (sor->ops == &tegra_sor_hdmi_ops) {
  2470. connector = DRM_MODE_CONNECTOR_HDMIA;
  2471. encoder = DRM_MODE_ENCODER_TMDS;
  2472. helpers = &tegra_sor_hdmi_helpers;
  2473. } else if (sor->soc->supports_lvds) {
  2474. connector = DRM_MODE_CONNECTOR_LVDS;
  2475. encoder = DRM_MODE_ENCODER_LVDS;
  2476. }
  2477. } else {
  2478. if (sor->output.panel) {
  2479. connector = DRM_MODE_CONNECTOR_eDP;
  2480. encoder = DRM_MODE_ENCODER_TMDS;
  2481. helpers = &tegra_sor_dp_helpers;
  2482. } else {
  2483. connector = DRM_MODE_CONNECTOR_DisplayPort;
  2484. encoder = DRM_MODE_ENCODER_TMDS;
  2485. helpers = &tegra_sor_dp_helpers;
  2486. }
  2487. sor->link.ops = &tegra_sor_dp_link_ops;
  2488. sor->link.aux = sor->aux;
  2489. }
  2490. sor->output.dev = sor->dev;
  2491. drm_connector_init_with_ddc(drm, &sor->output.connector,
  2492. &tegra_sor_connector_funcs,
  2493. connector,
  2494. sor->output.ddc);
  2495. drm_connector_helper_add(&sor->output.connector,
  2496. &tegra_sor_connector_helper_funcs);
  2497. sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
  2498. drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
  2499. drm_encoder_helper_add(&sor->output.encoder, helpers);
  2500. drm_connector_attach_encoder(&sor->output.connector,
  2501. &sor->output.encoder);
  2502. drm_connector_register(&sor->output.connector);
  2503. err = tegra_output_init(drm, &sor->output);
  2504. if (err < 0) {
  2505. dev_err(client->dev, "failed to initialize output: %d\n", err);
  2506. return err;
  2507. }
  2508. tegra_output_find_possible_crtcs(&sor->output, drm);
  2509. if (sor->aux) {
  2510. err = drm_dp_aux_attach(sor->aux, &sor->output);
  2511. if (err < 0) {
  2512. dev_err(sor->dev, "failed to attach DP: %d\n", err);
  2513. return err;
  2514. }
  2515. }
  2516. /*
  2517. * XXX: Remove this reset once proper hand-over from firmware to
  2518. * kernel is possible.
  2519. */
  2520. if (sor->rst) {
  2521. err = pm_runtime_resume_and_get(sor->dev);
  2522. if (err < 0) {
  2523. dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
  2524. return err;
  2525. }
  2526. err = reset_control_acquire(sor->rst);
  2527. if (err < 0) {
  2528. dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
  2529. err);
  2530. goto rpm_put;
  2531. }
  2532. err = reset_control_assert(sor->rst);
  2533. if (err < 0) {
  2534. dev_err(sor->dev, "failed to assert SOR reset: %d\n",
  2535. err);
  2536. goto rpm_put;
  2537. }
  2538. }
  2539. err = clk_prepare_enable(sor->clk);
  2540. if (err < 0) {
  2541. dev_err(sor->dev, "failed to enable clock: %d\n", err);
  2542. goto rpm_put;
  2543. }
  2544. usleep_range(1000, 3000);
  2545. if (sor->rst) {
  2546. err = reset_control_deassert(sor->rst);
  2547. if (err < 0) {
  2548. dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
  2549. err);
  2550. clk_disable_unprepare(sor->clk);
  2551. goto rpm_put;
  2552. }
  2553. reset_control_release(sor->rst);
  2554. pm_runtime_put(sor->dev);
  2555. }
  2556. err = clk_prepare_enable(sor->clk_safe);
  2557. if (err < 0) {
  2558. clk_disable_unprepare(sor->clk);
  2559. return err;
  2560. }
  2561. err = clk_prepare_enable(sor->clk_dp);
  2562. if (err < 0) {
  2563. clk_disable_unprepare(sor->clk_safe);
  2564. clk_disable_unprepare(sor->clk);
  2565. return err;
  2566. }
  2567. return 0;
  2568. rpm_put:
  2569. if (sor->rst)
  2570. pm_runtime_put(sor->dev);
  2571. return err;
  2572. }
  2573. static int tegra_sor_exit(struct host1x_client *client)
  2574. {
  2575. struct tegra_sor *sor = host1x_client_to_sor(client);
  2576. int err;
  2577. tegra_output_exit(&sor->output);
  2578. if (sor->aux) {
  2579. err = drm_dp_aux_detach(sor->aux);
  2580. if (err < 0) {
  2581. dev_err(sor->dev, "failed to detach DP: %d\n", err);
  2582. return err;
  2583. }
  2584. }
  2585. clk_disable_unprepare(sor->clk_safe);
  2586. clk_disable_unprepare(sor->clk_dp);
  2587. clk_disable_unprepare(sor->clk);
  2588. return 0;
  2589. }
  2590. static int tegra_sor_runtime_suspend(struct host1x_client *client)
  2591. {
  2592. struct tegra_sor *sor = host1x_client_to_sor(client);
  2593. struct device *dev = client->dev;
  2594. int err;
  2595. if (sor->rst) {
  2596. err = reset_control_assert(sor->rst);
  2597. if (err < 0) {
  2598. dev_err(dev, "failed to assert reset: %d\n", err);
  2599. return err;
  2600. }
  2601. reset_control_release(sor->rst);
  2602. }
  2603. usleep_range(1000, 2000);
  2604. clk_disable_unprepare(sor->clk);
  2605. pm_runtime_put_sync(dev);
  2606. return 0;
  2607. }
  2608. static int tegra_sor_runtime_resume(struct host1x_client *client)
  2609. {
  2610. struct tegra_sor *sor = host1x_client_to_sor(client);
  2611. struct device *dev = client->dev;
  2612. int err;
  2613. err = pm_runtime_resume_and_get(dev);
  2614. if (err < 0) {
  2615. dev_err(dev, "failed to get runtime PM: %d\n", err);
  2616. return err;
  2617. }
  2618. err = clk_prepare_enable(sor->clk);
  2619. if (err < 0) {
  2620. dev_err(dev, "failed to enable clock: %d\n", err);
  2621. goto put_rpm;
  2622. }
  2623. usleep_range(1000, 2000);
  2624. if (sor->rst) {
  2625. err = reset_control_acquire(sor->rst);
  2626. if (err < 0) {
  2627. dev_err(dev, "failed to acquire reset: %d\n", err);
  2628. goto disable_clk;
  2629. }
  2630. err = reset_control_deassert(sor->rst);
  2631. if (err < 0) {
  2632. dev_err(dev, "failed to deassert reset: %d\n", err);
  2633. goto release_reset;
  2634. }
  2635. }
  2636. return 0;
  2637. release_reset:
  2638. reset_control_release(sor->rst);
  2639. disable_clk:
  2640. clk_disable_unprepare(sor->clk);
  2641. put_rpm:
  2642. pm_runtime_put_sync(dev);
  2643. return err;
  2644. }
  2645. static const struct host1x_client_ops sor_client_ops = {
  2646. .init = tegra_sor_init,
  2647. .exit = tegra_sor_exit,
  2648. .suspend = tegra_sor_runtime_suspend,
  2649. .resume = tegra_sor_runtime_resume,
  2650. };
  2651. static const u8 tegra124_sor_xbar_cfg[5] = {
  2652. 0, 1, 2, 3, 4
  2653. };
  2654. static const struct tegra_sor_regs tegra124_sor_regs = {
  2655. .head_state0 = 0x05,
  2656. .head_state1 = 0x07,
  2657. .head_state2 = 0x09,
  2658. .head_state3 = 0x0b,
  2659. .head_state4 = 0x0d,
  2660. .head_state5 = 0x0f,
  2661. .pll0 = 0x17,
  2662. .pll1 = 0x18,
  2663. .pll2 = 0x19,
  2664. .pll3 = 0x1a,
  2665. .dp_padctl0 = 0x5c,
  2666. .dp_padctl2 = 0x73,
  2667. };
  2668. /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
  2669. static const u8 tegra124_sor_lane_map[4] = {
  2670. 2, 1, 0, 3,
  2671. };
  2672. static const u8 tegra124_sor_voltage_swing[4][4][4] = {
  2673. {
  2674. { 0x13, 0x19, 0x1e, 0x28 },
  2675. { 0x1e, 0x25, 0x2d, },
  2676. { 0x28, 0x32, },
  2677. { 0x3c, },
  2678. }, {
  2679. { 0x12, 0x17, 0x1b, 0x25 },
  2680. { 0x1c, 0x23, 0x2a, },
  2681. { 0x25, 0x2f, },
  2682. { 0x39, }
  2683. }, {
  2684. { 0x12, 0x16, 0x1a, 0x22 },
  2685. { 0x1b, 0x20, 0x27, },
  2686. { 0x24, 0x2d, },
  2687. { 0x36, },
  2688. }, {
  2689. { 0x11, 0x14, 0x17, 0x1f },
  2690. { 0x19, 0x1e, 0x24, },
  2691. { 0x22, 0x2a, },
  2692. { 0x32, },
  2693. },
  2694. };
  2695. static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
  2696. {
  2697. { 0x00, 0x09, 0x13, 0x25 },
  2698. { 0x00, 0x0f, 0x1e, },
  2699. { 0x00, 0x14, },
  2700. { 0x00, },
  2701. }, {
  2702. { 0x00, 0x0a, 0x14, 0x28 },
  2703. { 0x00, 0x0f, 0x1e, },
  2704. { 0x00, 0x14, },
  2705. { 0x00 },
  2706. }, {
  2707. { 0x00, 0x0a, 0x14, 0x28 },
  2708. { 0x00, 0x0f, 0x1e, },
  2709. { 0x00, 0x14, },
  2710. { 0x00, },
  2711. }, {
  2712. { 0x00, 0x0a, 0x14, 0x28 },
  2713. { 0x00, 0x0f, 0x1e, },
  2714. { 0x00, 0x14, },
  2715. { 0x00, },
  2716. },
  2717. };
  2718. static const u8 tegra124_sor_post_cursor[4][4][4] = {
  2719. {
  2720. { 0x00, 0x00, 0x00, 0x00 },
  2721. { 0x00, 0x00, 0x00, },
  2722. { 0x00, 0x00, },
  2723. { 0x00, },
  2724. }, {
  2725. { 0x02, 0x02, 0x04, 0x05 },
  2726. { 0x02, 0x04, 0x05, },
  2727. { 0x04, 0x05, },
  2728. { 0x05, },
  2729. }, {
  2730. { 0x04, 0x05, 0x08, 0x0b },
  2731. { 0x05, 0x09, 0x0b, },
  2732. { 0x08, 0x0a, },
  2733. { 0x0b, },
  2734. }, {
  2735. { 0x05, 0x09, 0x0b, 0x12 },
  2736. { 0x09, 0x0d, 0x12, },
  2737. { 0x0b, 0x0f, },
  2738. { 0x12, },
  2739. },
  2740. };
  2741. static const u8 tegra124_sor_tx_pu[4][4][4] = {
  2742. {
  2743. { 0x20, 0x30, 0x40, 0x60 },
  2744. { 0x30, 0x40, 0x60, },
  2745. { 0x40, 0x60, },
  2746. { 0x60, },
  2747. }, {
  2748. { 0x20, 0x20, 0x30, 0x50 },
  2749. { 0x30, 0x40, 0x50, },
  2750. { 0x40, 0x50, },
  2751. { 0x60, },
  2752. }, {
  2753. { 0x20, 0x20, 0x30, 0x40, },
  2754. { 0x30, 0x30, 0x40, },
  2755. { 0x40, 0x50, },
  2756. { 0x60, },
  2757. }, {
  2758. { 0x20, 0x20, 0x20, 0x40, },
  2759. { 0x30, 0x30, 0x40, },
  2760. { 0x40, 0x40, },
  2761. { 0x60, },
  2762. },
  2763. };
  2764. static const struct tegra_sor_soc tegra124_sor = {
  2765. .supports_lvds = true,
  2766. .supports_hdmi = false,
  2767. .supports_dp = true,
  2768. .supports_audio = false,
  2769. .supports_hdcp = false,
  2770. .regs = &tegra124_sor_regs,
  2771. .has_nvdisplay = false,
  2772. .xbar_cfg = tegra124_sor_xbar_cfg,
  2773. .lane_map = tegra124_sor_lane_map,
  2774. .voltage_swing = tegra124_sor_voltage_swing,
  2775. .pre_emphasis = tegra124_sor_pre_emphasis,
  2776. .post_cursor = tegra124_sor_post_cursor,
  2777. .tx_pu = tegra124_sor_tx_pu,
  2778. };
  2779. static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
  2780. {
  2781. { 0x00, 0x08, 0x12, 0x24 },
  2782. { 0x01, 0x0e, 0x1d, },
  2783. { 0x01, 0x13, },
  2784. { 0x00, },
  2785. }, {
  2786. { 0x00, 0x08, 0x12, 0x24 },
  2787. { 0x00, 0x0e, 0x1d, },
  2788. { 0x00, 0x13, },
  2789. { 0x00 },
  2790. }, {
  2791. { 0x00, 0x08, 0x12, 0x24 },
  2792. { 0x00, 0x0e, 0x1d, },
  2793. { 0x00, 0x13, },
  2794. { 0x00, },
  2795. }, {
  2796. { 0x00, 0x08, 0x12, 0x24 },
  2797. { 0x00, 0x0e, 0x1d, },
  2798. { 0x00, 0x13, },
  2799. { 0x00, },
  2800. },
  2801. };
  2802. static const struct tegra_sor_soc tegra132_sor = {
  2803. .supports_lvds = true,
  2804. .supports_hdmi = false,
  2805. .supports_dp = true,
  2806. .supports_audio = false,
  2807. .supports_hdcp = false,
  2808. .regs = &tegra124_sor_regs,
  2809. .has_nvdisplay = false,
  2810. .xbar_cfg = tegra124_sor_xbar_cfg,
  2811. .lane_map = tegra124_sor_lane_map,
  2812. .voltage_swing = tegra124_sor_voltage_swing,
  2813. .pre_emphasis = tegra132_sor_pre_emphasis,
  2814. .post_cursor = tegra124_sor_post_cursor,
  2815. .tx_pu = tegra124_sor_tx_pu,
  2816. };
  2817. static const struct tegra_sor_regs tegra210_sor_regs = {
  2818. .head_state0 = 0x05,
  2819. .head_state1 = 0x07,
  2820. .head_state2 = 0x09,
  2821. .head_state3 = 0x0b,
  2822. .head_state4 = 0x0d,
  2823. .head_state5 = 0x0f,
  2824. .pll0 = 0x17,
  2825. .pll1 = 0x18,
  2826. .pll2 = 0x19,
  2827. .pll3 = 0x1a,
  2828. .dp_padctl0 = 0x5c,
  2829. .dp_padctl2 = 0x73,
  2830. };
  2831. static const u8 tegra210_sor_xbar_cfg[5] = {
  2832. 2, 1, 0, 3, 4
  2833. };
  2834. static const u8 tegra210_sor_lane_map[4] = {
  2835. 0, 1, 2, 3,
  2836. };
  2837. static const struct tegra_sor_soc tegra210_sor = {
  2838. .supports_lvds = false,
  2839. .supports_hdmi = false,
  2840. .supports_dp = true,
  2841. .supports_audio = false,
  2842. .supports_hdcp = false,
  2843. .regs = &tegra210_sor_regs,
  2844. .has_nvdisplay = false,
  2845. .xbar_cfg = tegra210_sor_xbar_cfg,
  2846. .lane_map = tegra210_sor_lane_map,
  2847. .voltage_swing = tegra124_sor_voltage_swing,
  2848. .pre_emphasis = tegra124_sor_pre_emphasis,
  2849. .post_cursor = tegra124_sor_post_cursor,
  2850. .tx_pu = tegra124_sor_tx_pu,
  2851. };
  2852. static const struct tegra_sor_soc tegra210_sor1 = {
  2853. .supports_lvds = false,
  2854. .supports_hdmi = true,
  2855. .supports_dp = true,
  2856. .supports_audio = true,
  2857. .supports_hdcp = true,
  2858. .regs = &tegra210_sor_regs,
  2859. .has_nvdisplay = false,
  2860. .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
  2861. .settings = tegra210_sor_hdmi_defaults,
  2862. .xbar_cfg = tegra210_sor_xbar_cfg,
  2863. .lane_map = tegra210_sor_lane_map,
  2864. .voltage_swing = tegra124_sor_voltage_swing,
  2865. .pre_emphasis = tegra124_sor_pre_emphasis,
  2866. .post_cursor = tegra124_sor_post_cursor,
  2867. .tx_pu = tegra124_sor_tx_pu,
  2868. };
  2869. static const struct tegra_sor_regs tegra186_sor_regs = {
  2870. .head_state0 = 0x151,
  2871. .head_state1 = 0x154,
  2872. .head_state2 = 0x157,
  2873. .head_state3 = 0x15a,
  2874. .head_state4 = 0x15d,
  2875. .head_state5 = 0x160,
  2876. .pll0 = 0x163,
  2877. .pll1 = 0x164,
  2878. .pll2 = 0x165,
  2879. .pll3 = 0x166,
  2880. .dp_padctl0 = 0x168,
  2881. .dp_padctl2 = 0x16a,
  2882. };
  2883. static const u8 tegra186_sor_voltage_swing[4][4][4] = {
  2884. {
  2885. { 0x13, 0x19, 0x1e, 0x28 },
  2886. { 0x1e, 0x25, 0x2d, },
  2887. { 0x28, 0x32, },
  2888. { 0x39, },
  2889. }, {
  2890. { 0x12, 0x16, 0x1b, 0x25 },
  2891. { 0x1c, 0x23, 0x2a, },
  2892. { 0x25, 0x2f, },
  2893. { 0x37, }
  2894. }, {
  2895. { 0x12, 0x16, 0x1a, 0x22 },
  2896. { 0x1b, 0x20, 0x27, },
  2897. { 0x24, 0x2d, },
  2898. { 0x35, },
  2899. }, {
  2900. { 0x11, 0x14, 0x17, 0x1f },
  2901. { 0x19, 0x1e, 0x24, },
  2902. { 0x22, 0x2a, },
  2903. { 0x32, },
  2904. },
  2905. };
  2906. static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
  2907. {
  2908. { 0x00, 0x08, 0x12, 0x24 },
  2909. { 0x01, 0x0e, 0x1d, },
  2910. { 0x01, 0x13, },
  2911. { 0x00, },
  2912. }, {
  2913. { 0x00, 0x08, 0x12, 0x24 },
  2914. { 0x00, 0x0e, 0x1d, },
  2915. { 0x00, 0x13, },
  2916. { 0x00 },
  2917. }, {
  2918. { 0x00, 0x08, 0x14, 0x24 },
  2919. { 0x00, 0x0e, 0x1d, },
  2920. { 0x00, 0x13, },
  2921. { 0x00, },
  2922. }, {
  2923. { 0x00, 0x08, 0x12, 0x24 },
  2924. { 0x00, 0x0e, 0x1d, },
  2925. { 0x00, 0x13, },
  2926. { 0x00, },
  2927. },
  2928. };
  2929. static const struct tegra_sor_soc tegra186_sor = {
  2930. .supports_lvds = false,
  2931. .supports_hdmi = true,
  2932. .supports_dp = true,
  2933. .supports_audio = true,
  2934. .supports_hdcp = true,
  2935. .regs = &tegra186_sor_regs,
  2936. .has_nvdisplay = true,
  2937. .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
  2938. .settings = tegra186_sor_hdmi_defaults,
  2939. .xbar_cfg = tegra124_sor_xbar_cfg,
  2940. .lane_map = tegra124_sor_lane_map,
  2941. .voltage_swing = tegra186_sor_voltage_swing,
  2942. .pre_emphasis = tegra186_sor_pre_emphasis,
  2943. .post_cursor = tegra124_sor_post_cursor,
  2944. .tx_pu = tegra124_sor_tx_pu,
  2945. };
  2946. static const struct tegra_sor_regs tegra194_sor_regs = {
  2947. .head_state0 = 0x151,
  2948. .head_state1 = 0x155,
  2949. .head_state2 = 0x159,
  2950. .head_state3 = 0x15d,
  2951. .head_state4 = 0x161,
  2952. .head_state5 = 0x165,
  2953. .pll0 = 0x169,
  2954. .pll1 = 0x16a,
  2955. .pll2 = 0x16b,
  2956. .pll3 = 0x16c,
  2957. .dp_padctl0 = 0x16e,
  2958. .dp_padctl2 = 0x16f,
  2959. };
  2960. static const struct tegra_sor_soc tegra194_sor = {
  2961. .supports_lvds = false,
  2962. .supports_hdmi = true,
  2963. .supports_dp = true,
  2964. .supports_audio = true,
  2965. .supports_hdcp = true,
  2966. .regs = &tegra194_sor_regs,
  2967. .has_nvdisplay = true,
  2968. .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
  2969. .settings = tegra194_sor_hdmi_defaults,
  2970. .xbar_cfg = tegra210_sor_xbar_cfg,
  2971. .lane_map = tegra124_sor_lane_map,
  2972. .voltage_swing = tegra186_sor_voltage_swing,
  2973. .pre_emphasis = tegra186_sor_pre_emphasis,
  2974. .post_cursor = tegra124_sor_post_cursor,
  2975. .tx_pu = tegra124_sor_tx_pu,
  2976. };
  2977. static const struct of_device_id tegra_sor_of_match[] = {
  2978. { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
  2979. { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
  2980. { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
  2981. { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
  2982. { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
  2983. { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
  2984. { },
  2985. };
  2986. MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
  2987. static int tegra_sor_parse_dt(struct tegra_sor *sor)
  2988. {
  2989. struct device_node *np = sor->dev->of_node;
  2990. u32 xbar_cfg[5];
  2991. unsigned int i;
  2992. u32 value;
  2993. int err;
  2994. if (sor->soc->has_nvdisplay) {
  2995. err = of_property_read_u32(np, "nvidia,interface", &value);
  2996. if (err < 0)
  2997. return err;
  2998. sor->index = value;
  2999. /*
  3000. * override the default that we already set for Tegra210 and
  3001. * earlier
  3002. */
  3003. sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
  3004. } else {
  3005. if (!sor->soc->supports_audio)
  3006. sor->index = 0;
  3007. else
  3008. sor->index = 1;
  3009. }
  3010. err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
  3011. if (err < 0) {
  3012. /* fall back to default per-SoC XBAR configuration */
  3013. for (i = 0; i < 5; i++)
  3014. sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
  3015. } else {
  3016. /* copy cells to SOR XBAR configuration */
  3017. for (i = 0; i < 5; i++)
  3018. sor->xbar_cfg[i] = xbar_cfg[i];
  3019. }
  3020. return 0;
  3021. }
  3022. static irqreturn_t tegra_sor_irq(int irq, void *data)
  3023. {
  3024. struct tegra_sor *sor = data;
  3025. u32 value;
  3026. value = tegra_sor_readl(sor, SOR_INT_STATUS);
  3027. tegra_sor_writel(sor, value, SOR_INT_STATUS);
  3028. if (value & SOR_INT_CODEC_SCRATCH0) {
  3029. value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
  3030. if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
  3031. unsigned int format;
  3032. format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
  3033. tegra_hda_parse_format(format, &sor->format);
  3034. if (sor->ops->audio_enable)
  3035. sor->ops->audio_enable(sor);
  3036. } else {
  3037. if (sor->ops->audio_disable)
  3038. sor->ops->audio_disable(sor);
  3039. }
  3040. }
  3041. return IRQ_HANDLED;
  3042. }
  3043. static int tegra_sor_probe(struct platform_device *pdev)
  3044. {
  3045. struct device_node *np;
  3046. struct tegra_sor *sor;
  3047. struct resource *regs;
  3048. int err;
  3049. sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
  3050. if (!sor)
  3051. return -ENOMEM;
  3052. sor->soc = of_device_get_match_data(&pdev->dev);
  3053. sor->output.dev = sor->dev = &pdev->dev;
  3054. sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
  3055. sor->soc->num_settings *
  3056. sizeof(*sor->settings),
  3057. GFP_KERNEL);
  3058. if (!sor->settings)
  3059. return -ENOMEM;
  3060. sor->num_settings = sor->soc->num_settings;
  3061. np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
  3062. if (np) {
  3063. sor->aux = drm_dp_aux_find_by_of_node(np);
  3064. of_node_put(np);
  3065. if (!sor->aux)
  3066. return -EPROBE_DEFER;
  3067. if (get_device(&sor->aux->ddc.dev)) {
  3068. if (try_module_get(sor->aux->ddc.owner))
  3069. sor->output.ddc = &sor->aux->ddc;
  3070. else
  3071. put_device(&sor->aux->ddc.dev);
  3072. }
  3073. }
  3074. if (!sor->aux) {
  3075. if (sor->soc->supports_hdmi) {
  3076. sor->ops = &tegra_sor_hdmi_ops;
  3077. sor->pad = TEGRA_IO_PAD_HDMI;
  3078. } else if (sor->soc->supports_lvds) {
  3079. dev_err(&pdev->dev, "LVDS not supported yet\n");
  3080. return -ENODEV;
  3081. } else {
  3082. dev_err(&pdev->dev, "unknown (non-DP) support\n");
  3083. return -ENODEV;
  3084. }
  3085. } else {
  3086. np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
  3087. /*
  3088. * No need to keep this around since we only use it as a check
  3089. * to see if a panel is connected (eDP) or not (DP).
  3090. */
  3091. of_node_put(np);
  3092. sor->ops = &tegra_sor_dp_ops;
  3093. sor->pad = TEGRA_IO_PAD_LVDS;
  3094. }
  3095. err = tegra_sor_parse_dt(sor);
  3096. if (err < 0)
  3097. return err;
  3098. err = tegra_output_probe(&sor->output);
  3099. if (err < 0)
  3100. return dev_err_probe(&pdev->dev, err,
  3101. "failed to probe output\n");
  3102. if (sor->ops && sor->ops->probe) {
  3103. err = sor->ops->probe(sor);
  3104. if (err < 0) {
  3105. dev_err(&pdev->dev, "failed to probe %s: %d\n",
  3106. sor->ops->name, err);
  3107. goto remove;
  3108. }
  3109. }
  3110. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3111. sor->regs = devm_ioremap_resource(&pdev->dev, regs);
  3112. if (IS_ERR(sor->regs)) {
  3113. err = PTR_ERR(sor->regs);
  3114. goto remove;
  3115. }
  3116. err = platform_get_irq(pdev, 0);
  3117. if (err < 0) {
  3118. dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
  3119. goto remove;
  3120. }
  3121. sor->irq = err;
  3122. err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
  3123. dev_name(sor->dev), sor);
  3124. if (err < 0) {
  3125. dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
  3126. goto remove;
  3127. }
  3128. sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
  3129. if (IS_ERR(sor->rst)) {
  3130. err = PTR_ERR(sor->rst);
  3131. if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
  3132. dev_err(&pdev->dev, "failed to get reset control: %d\n",
  3133. err);
  3134. goto remove;
  3135. }
  3136. /*
  3137. * At this point, the reset control is most likely being used
  3138. * by the generic power domain implementation. With any luck
  3139. * the power domain will have taken care of resetting the SOR
  3140. * and we don't have to do anything.
  3141. */
  3142. sor->rst = NULL;
  3143. }
  3144. sor->clk = devm_clk_get(&pdev->dev, NULL);
  3145. if (IS_ERR(sor->clk)) {
  3146. err = PTR_ERR(sor->clk);
  3147. dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
  3148. goto remove;
  3149. }
  3150. if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
  3151. struct device_node *np = pdev->dev.of_node;
  3152. const char *name;
  3153. /*
  3154. * For backwards compatibility with Tegra210 device trees,
  3155. * fall back to the old clock name "source" if the new "out"
  3156. * clock is not available.
  3157. */
  3158. if (of_property_match_string(np, "clock-names", "out") < 0)
  3159. name = "source";
  3160. else
  3161. name = "out";
  3162. sor->clk_out = devm_clk_get(&pdev->dev, name);
  3163. if (IS_ERR(sor->clk_out)) {
  3164. err = PTR_ERR(sor->clk_out);
  3165. dev_err(sor->dev, "failed to get %s clock: %d\n",
  3166. name, err);
  3167. goto remove;
  3168. }
  3169. } else {
  3170. /* fall back to the module clock on SOR0 (eDP/LVDS only) */
  3171. sor->clk_out = sor->clk;
  3172. }
  3173. sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
  3174. if (IS_ERR(sor->clk_parent)) {
  3175. err = PTR_ERR(sor->clk_parent);
  3176. dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
  3177. goto remove;
  3178. }
  3179. sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
  3180. if (IS_ERR(sor->clk_safe)) {
  3181. err = PTR_ERR(sor->clk_safe);
  3182. dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
  3183. goto remove;
  3184. }
  3185. sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
  3186. if (IS_ERR(sor->clk_dp)) {
  3187. err = PTR_ERR(sor->clk_dp);
  3188. dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
  3189. goto remove;
  3190. }
  3191. /*
  3192. * Starting with Tegra186, the BPMP provides an implementation for
  3193. * the pad output clock, so we have to look it up from device tree.
  3194. */
  3195. sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
  3196. if (IS_ERR(sor->clk_pad)) {
  3197. if (sor->clk_pad != ERR_PTR(-ENOENT)) {
  3198. err = PTR_ERR(sor->clk_pad);
  3199. goto remove;
  3200. }
  3201. /*
  3202. * If the pad output clock is not available, then we assume
  3203. * we're on Tegra210 or earlier and have to provide our own
  3204. * implementation.
  3205. */
  3206. sor->clk_pad = NULL;
  3207. }
  3208. /*
  3209. * The bootloader may have set up the SOR such that it's module clock
  3210. * is sourced by one of the display PLLs. However, that doesn't work
  3211. * without properly having set up other bits of the SOR.
  3212. */
  3213. err = clk_set_parent(sor->clk_out, sor->clk_safe);
  3214. if (err < 0) {
  3215. dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
  3216. goto remove;
  3217. }
  3218. platform_set_drvdata(pdev, sor);
  3219. pm_runtime_enable(&pdev->dev);
  3220. host1x_client_init(&sor->client);
  3221. sor->client.ops = &sor_client_ops;
  3222. sor->client.dev = &pdev->dev;
  3223. /*
  3224. * On Tegra210 and earlier, provide our own implementation for the
  3225. * pad output clock.
  3226. */
  3227. if (!sor->clk_pad) {
  3228. char *name;
  3229. name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
  3230. sor->index);
  3231. if (!name) {
  3232. err = -ENOMEM;
  3233. goto uninit;
  3234. }
  3235. err = host1x_client_resume(&sor->client);
  3236. if (err < 0) {
  3237. dev_err(sor->dev, "failed to resume: %d\n", err);
  3238. goto uninit;
  3239. }
  3240. sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
  3241. host1x_client_suspend(&sor->client);
  3242. }
  3243. if (IS_ERR(sor->clk_pad)) {
  3244. err = PTR_ERR(sor->clk_pad);
  3245. dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
  3246. err);
  3247. goto uninit;
  3248. }
  3249. err = __host1x_client_register(&sor->client);
  3250. if (err < 0) {
  3251. dev_err(&pdev->dev, "failed to register host1x client: %d\n",
  3252. err);
  3253. goto uninit;
  3254. }
  3255. return 0;
  3256. uninit:
  3257. host1x_client_exit(&sor->client);
  3258. pm_runtime_disable(&pdev->dev);
  3259. remove:
  3260. tegra_output_remove(&sor->output);
  3261. return err;
  3262. }
  3263. static int tegra_sor_remove(struct platform_device *pdev)
  3264. {
  3265. struct tegra_sor *sor = platform_get_drvdata(pdev);
  3266. int err;
  3267. err = host1x_client_unregister(&sor->client);
  3268. if (err < 0) {
  3269. dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
  3270. err);
  3271. return err;
  3272. }
  3273. pm_runtime_disable(&pdev->dev);
  3274. tegra_output_remove(&sor->output);
  3275. return 0;
  3276. }
  3277. static int __maybe_unused tegra_sor_suspend(struct device *dev)
  3278. {
  3279. struct tegra_sor *sor = dev_get_drvdata(dev);
  3280. int err;
  3281. err = tegra_output_suspend(&sor->output);
  3282. if (err < 0) {
  3283. dev_err(dev, "failed to suspend output: %d\n", err);
  3284. return err;
  3285. }
  3286. if (sor->hdmi_supply) {
  3287. err = regulator_disable(sor->hdmi_supply);
  3288. if (err < 0) {
  3289. tegra_output_resume(&sor->output);
  3290. return err;
  3291. }
  3292. }
  3293. return 0;
  3294. }
  3295. static int __maybe_unused tegra_sor_resume(struct device *dev)
  3296. {
  3297. struct tegra_sor *sor = dev_get_drvdata(dev);
  3298. int err;
  3299. if (sor->hdmi_supply) {
  3300. err = regulator_enable(sor->hdmi_supply);
  3301. if (err < 0)
  3302. return err;
  3303. }
  3304. err = tegra_output_resume(&sor->output);
  3305. if (err < 0) {
  3306. dev_err(dev, "failed to resume output: %d\n", err);
  3307. if (sor->hdmi_supply)
  3308. regulator_disable(sor->hdmi_supply);
  3309. return err;
  3310. }
  3311. return 0;
  3312. }
  3313. static const struct dev_pm_ops tegra_sor_pm_ops = {
  3314. SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
  3315. };
  3316. struct platform_driver tegra_sor_driver = {
  3317. .driver = {
  3318. .name = "tegra-sor",
  3319. .of_match_table = tegra_sor_of_match,
  3320. .pm = &tegra_sor_pm_ops,
  3321. },
  3322. .probe = tegra_sor_probe,
  3323. .remove = tegra_sor_remove,
  3324. };