plane.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <linux/iommu.h>
  6. #include <drm/drm_atomic.h>
  7. #include <drm/drm_atomic_helper.h>
  8. #include <drm/drm_fourcc.h>
  9. #include <drm/drm_gem_framebuffer_helper.h>
  10. #include <drm/drm_plane_helper.h>
  11. #include "dc.h"
  12. #include "plane.h"
  13. static void tegra_plane_destroy(struct drm_plane *plane)
  14. {
  15. struct tegra_plane *p = to_tegra_plane(plane);
  16. drm_plane_cleanup(plane);
  17. kfree(p);
  18. }
  19. static void tegra_plane_reset(struct drm_plane *plane)
  20. {
  21. struct tegra_plane *p = to_tegra_plane(plane);
  22. struct tegra_plane_state *state;
  23. unsigned int i;
  24. if (plane->state)
  25. __drm_atomic_helper_plane_destroy_state(plane->state);
  26. kfree(plane->state);
  27. plane->state = NULL;
  28. state = kzalloc(sizeof(*state), GFP_KERNEL);
  29. if (state) {
  30. plane->state = &state->base;
  31. plane->state->plane = plane;
  32. plane->state->zpos = p->index;
  33. plane->state->normalized_zpos = p->index;
  34. for (i = 0; i < 3; i++)
  35. state->iova[i] = DMA_MAPPING_ERROR;
  36. }
  37. }
  38. static struct drm_plane_state *
  39. tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
  40. {
  41. struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
  42. struct tegra_plane_state *copy;
  43. unsigned int i;
  44. copy = kmalloc(sizeof(*copy), GFP_KERNEL);
  45. if (!copy)
  46. return NULL;
  47. __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
  48. copy->tiling = state->tiling;
  49. copy->format = state->format;
  50. copy->swap = state->swap;
  51. copy->reflect_x = state->reflect_x;
  52. copy->reflect_y = state->reflect_y;
  53. copy->opaque = state->opaque;
  54. for (i = 0; i < 2; i++)
  55. copy->blending[i] = state->blending[i];
  56. for (i = 0; i < 3; i++) {
  57. copy->iova[i] = DMA_MAPPING_ERROR;
  58. copy->sgt[i] = NULL;
  59. }
  60. return &copy->base;
  61. }
  62. static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
  63. struct drm_plane_state *state)
  64. {
  65. __drm_atomic_helper_plane_destroy_state(state);
  66. kfree(state);
  67. }
  68. static bool tegra_plane_format_mod_supported(struct drm_plane *plane,
  69. uint32_t format,
  70. uint64_t modifier)
  71. {
  72. const struct drm_format_info *info = drm_format_info(format);
  73. if (modifier == DRM_FORMAT_MOD_LINEAR)
  74. return true;
  75. if (info->num_planes == 1)
  76. return true;
  77. return false;
  78. }
  79. const struct drm_plane_funcs tegra_plane_funcs = {
  80. .update_plane = drm_atomic_helper_update_plane,
  81. .disable_plane = drm_atomic_helper_disable_plane,
  82. .destroy = tegra_plane_destroy,
  83. .reset = tegra_plane_reset,
  84. .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
  85. .atomic_destroy_state = tegra_plane_atomic_destroy_state,
  86. .format_mod_supported = tegra_plane_format_mod_supported,
  87. };
  88. static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state)
  89. {
  90. struct iommu_domain *domain = iommu_get_domain_for_dev(dc->dev);
  91. unsigned int i;
  92. int err;
  93. for (i = 0; i < state->base.fb->format->num_planes; i++) {
  94. struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
  95. dma_addr_t phys_addr, *phys;
  96. struct sg_table *sgt;
  97. if (!domain || dc->client.group)
  98. phys = &phys_addr;
  99. else
  100. phys = NULL;
  101. sgt = host1x_bo_pin(dc->dev, &bo->base, phys);
  102. if (IS_ERR(sgt)) {
  103. err = PTR_ERR(sgt);
  104. goto unpin;
  105. }
  106. if (sgt) {
  107. err = dma_map_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
  108. if (err)
  109. goto unpin;
  110. /*
  111. * The display controller needs contiguous memory, so
  112. * fail if the buffer is discontiguous and we fail to
  113. * map its SG table to a single contiguous chunk of
  114. * I/O virtual memory.
  115. */
  116. if (sgt->nents > 1) {
  117. err = -EINVAL;
  118. goto unpin;
  119. }
  120. state->iova[i] = sg_dma_address(sgt->sgl);
  121. state->sgt[i] = sgt;
  122. } else {
  123. state->iova[i] = phys_addr;
  124. }
  125. }
  126. return 0;
  127. unpin:
  128. dev_err(dc->dev, "failed to map plane %u: %d\n", i, err);
  129. while (i--) {
  130. struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
  131. struct sg_table *sgt = state->sgt[i];
  132. if (sgt)
  133. dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
  134. host1x_bo_unpin(dc->dev, &bo->base, sgt);
  135. state->iova[i] = DMA_MAPPING_ERROR;
  136. state->sgt[i] = NULL;
  137. }
  138. return err;
  139. }
  140. static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state)
  141. {
  142. unsigned int i;
  143. for (i = 0; i < state->base.fb->format->num_planes; i++) {
  144. struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
  145. struct sg_table *sgt = state->sgt[i];
  146. if (sgt)
  147. dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
  148. host1x_bo_unpin(dc->dev, &bo->base, sgt);
  149. state->iova[i] = DMA_MAPPING_ERROR;
  150. state->sgt[i] = NULL;
  151. }
  152. }
  153. int tegra_plane_prepare_fb(struct drm_plane *plane,
  154. struct drm_plane_state *state)
  155. {
  156. struct tegra_dc *dc = to_tegra_dc(state->crtc);
  157. if (!state->fb)
  158. return 0;
  159. drm_gem_fb_prepare_fb(plane, state);
  160. return tegra_dc_pin(dc, to_tegra_plane_state(state));
  161. }
  162. void tegra_plane_cleanup_fb(struct drm_plane *plane,
  163. struct drm_plane_state *state)
  164. {
  165. struct tegra_dc *dc = to_tegra_dc(state->crtc);
  166. if (dc)
  167. tegra_dc_unpin(dc, to_tegra_plane_state(state));
  168. }
  169. int tegra_plane_state_add(struct tegra_plane *plane,
  170. struct drm_plane_state *state)
  171. {
  172. struct drm_crtc_state *crtc_state;
  173. struct tegra_dc_state *tegra;
  174. int err;
  175. /* Propagate errors from allocation or locking failures. */
  176. crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
  177. if (IS_ERR(crtc_state))
  178. return PTR_ERR(crtc_state);
  179. /* Check plane state for visibility and calculate clipping bounds */
  180. err = drm_atomic_helper_check_plane_state(state, crtc_state,
  181. 0, INT_MAX, true, true);
  182. if (err < 0)
  183. return err;
  184. tegra = to_dc_state(crtc_state);
  185. tegra->planes |= WIN_A_ACT_REQ << plane->index;
  186. return 0;
  187. }
  188. int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
  189. {
  190. /* assume no swapping of fetched data */
  191. if (swap)
  192. *swap = BYTE_SWAP_NOSWAP;
  193. switch (fourcc) {
  194. case DRM_FORMAT_ARGB4444:
  195. *format = WIN_COLOR_DEPTH_B4G4R4A4;
  196. break;
  197. case DRM_FORMAT_ARGB1555:
  198. *format = WIN_COLOR_DEPTH_B5G5R5A1;
  199. break;
  200. case DRM_FORMAT_RGB565:
  201. *format = WIN_COLOR_DEPTH_B5G6R5;
  202. break;
  203. case DRM_FORMAT_RGBA5551:
  204. *format = WIN_COLOR_DEPTH_A1B5G5R5;
  205. break;
  206. case DRM_FORMAT_ARGB8888:
  207. *format = WIN_COLOR_DEPTH_B8G8R8A8;
  208. break;
  209. case DRM_FORMAT_ABGR8888:
  210. *format = WIN_COLOR_DEPTH_R8G8B8A8;
  211. break;
  212. case DRM_FORMAT_ABGR4444:
  213. *format = WIN_COLOR_DEPTH_R4G4B4A4;
  214. break;
  215. case DRM_FORMAT_ABGR1555:
  216. *format = WIN_COLOR_DEPTH_R5G5B5A;
  217. break;
  218. case DRM_FORMAT_BGRA5551:
  219. *format = WIN_COLOR_DEPTH_AR5G5B5;
  220. break;
  221. case DRM_FORMAT_XRGB1555:
  222. *format = WIN_COLOR_DEPTH_B5G5R5X1;
  223. break;
  224. case DRM_FORMAT_RGBX5551:
  225. *format = WIN_COLOR_DEPTH_X1B5G5R5;
  226. break;
  227. case DRM_FORMAT_XBGR1555:
  228. *format = WIN_COLOR_DEPTH_R5G5B5X1;
  229. break;
  230. case DRM_FORMAT_BGRX5551:
  231. *format = WIN_COLOR_DEPTH_X1R5G5B5;
  232. break;
  233. case DRM_FORMAT_BGR565:
  234. *format = WIN_COLOR_DEPTH_R5G6B5;
  235. break;
  236. case DRM_FORMAT_BGRA8888:
  237. *format = WIN_COLOR_DEPTH_A8R8G8B8;
  238. break;
  239. case DRM_FORMAT_RGBA8888:
  240. *format = WIN_COLOR_DEPTH_A8B8G8R8;
  241. break;
  242. case DRM_FORMAT_XRGB8888:
  243. *format = WIN_COLOR_DEPTH_B8G8R8X8;
  244. break;
  245. case DRM_FORMAT_XBGR8888:
  246. *format = WIN_COLOR_DEPTH_R8G8B8X8;
  247. break;
  248. case DRM_FORMAT_UYVY:
  249. *format = WIN_COLOR_DEPTH_YCbCr422;
  250. break;
  251. case DRM_FORMAT_YUYV:
  252. if (!swap)
  253. return -EINVAL;
  254. *format = WIN_COLOR_DEPTH_YCbCr422;
  255. *swap = BYTE_SWAP_SWAP2;
  256. break;
  257. case DRM_FORMAT_YUV420:
  258. *format = WIN_COLOR_DEPTH_YCbCr420P;
  259. break;
  260. case DRM_FORMAT_YUV422:
  261. *format = WIN_COLOR_DEPTH_YCbCr422P;
  262. break;
  263. default:
  264. return -EINVAL;
  265. }
  266. return 0;
  267. }
  268. bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
  269. {
  270. switch (format) {
  271. case WIN_COLOR_DEPTH_YCbCr422:
  272. case WIN_COLOR_DEPTH_YUV422:
  273. if (planar)
  274. *planar = false;
  275. return true;
  276. case WIN_COLOR_DEPTH_YCbCr420P:
  277. case WIN_COLOR_DEPTH_YUV420P:
  278. case WIN_COLOR_DEPTH_YCbCr422P:
  279. case WIN_COLOR_DEPTH_YUV422P:
  280. case WIN_COLOR_DEPTH_YCbCr422R:
  281. case WIN_COLOR_DEPTH_YUV422R:
  282. case WIN_COLOR_DEPTH_YCbCr422RA:
  283. case WIN_COLOR_DEPTH_YUV422RA:
  284. if (planar)
  285. *planar = true;
  286. return true;
  287. }
  288. if (planar)
  289. *planar = false;
  290. return false;
  291. }
  292. static bool __drm_format_has_alpha(u32 format)
  293. {
  294. switch (format) {
  295. case DRM_FORMAT_ARGB1555:
  296. case DRM_FORMAT_RGBA5551:
  297. case DRM_FORMAT_ABGR8888:
  298. case DRM_FORMAT_ARGB8888:
  299. return true;
  300. }
  301. return false;
  302. }
  303. static int tegra_plane_format_get_alpha(unsigned int opaque,
  304. unsigned int *alpha)
  305. {
  306. if (tegra_plane_format_is_yuv(opaque, NULL)) {
  307. *alpha = opaque;
  308. return 0;
  309. }
  310. switch (opaque) {
  311. case WIN_COLOR_DEPTH_B5G5R5X1:
  312. *alpha = WIN_COLOR_DEPTH_B5G5R5A1;
  313. return 0;
  314. case WIN_COLOR_DEPTH_X1B5G5R5:
  315. *alpha = WIN_COLOR_DEPTH_A1B5G5R5;
  316. return 0;
  317. case WIN_COLOR_DEPTH_R8G8B8X8:
  318. *alpha = WIN_COLOR_DEPTH_R8G8B8A8;
  319. return 0;
  320. case WIN_COLOR_DEPTH_B8G8R8X8:
  321. *alpha = WIN_COLOR_DEPTH_B8G8R8A8;
  322. return 0;
  323. case WIN_COLOR_DEPTH_B5G6R5:
  324. *alpha = opaque;
  325. return 0;
  326. }
  327. return -EINVAL;
  328. }
  329. /*
  330. * This is applicable to Tegra20 and Tegra30 only where the opaque formats can
  331. * be emulated using the alpha formats and alpha blending disabled.
  332. */
  333. static int tegra_plane_setup_opacity(struct tegra_plane *tegra,
  334. struct tegra_plane_state *state)
  335. {
  336. unsigned int format;
  337. int err;
  338. switch (state->format) {
  339. case WIN_COLOR_DEPTH_B5G5R5A1:
  340. case WIN_COLOR_DEPTH_A1B5G5R5:
  341. case WIN_COLOR_DEPTH_R8G8B8A8:
  342. case WIN_COLOR_DEPTH_B8G8R8A8:
  343. state->opaque = false;
  344. break;
  345. default:
  346. err = tegra_plane_format_get_alpha(state->format, &format);
  347. if (err < 0)
  348. return err;
  349. state->format = format;
  350. state->opaque = true;
  351. break;
  352. }
  353. return 0;
  354. }
  355. static int tegra_plane_check_transparency(struct tegra_plane *tegra,
  356. struct tegra_plane_state *state)
  357. {
  358. struct drm_plane_state *old, *plane_state;
  359. struct drm_plane *plane;
  360. old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base);
  361. /* check if zpos / transparency changed */
  362. if (old->normalized_zpos == state->base.normalized_zpos &&
  363. to_tegra_plane_state(old)->opaque == state->opaque)
  364. return 0;
  365. /* include all sibling planes into this commit */
  366. drm_for_each_plane(plane, tegra->base.dev) {
  367. struct tegra_plane *p = to_tegra_plane(plane);
  368. /* skip this plane and planes on different CRTCs */
  369. if (p == tegra || p->dc != tegra->dc)
  370. continue;
  371. plane_state = drm_atomic_get_plane_state(state->base.state,
  372. plane);
  373. if (IS_ERR(plane_state))
  374. return PTR_ERR(plane_state);
  375. }
  376. return 1;
  377. }
  378. static unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane,
  379. struct tegra_plane *other)
  380. {
  381. unsigned int index = 0, i;
  382. WARN_ON(plane == other);
  383. for (i = 0; i < 3; i++) {
  384. if (i == plane->index)
  385. continue;
  386. if (i == other->index)
  387. break;
  388. index++;
  389. }
  390. return index;
  391. }
  392. static void tegra_plane_update_transparency(struct tegra_plane *tegra,
  393. struct tegra_plane_state *state)
  394. {
  395. struct drm_plane_state *new;
  396. struct drm_plane *plane;
  397. unsigned int i;
  398. for_each_new_plane_in_state(state->base.state, plane, new, i) {
  399. struct tegra_plane *p = to_tegra_plane(plane);
  400. unsigned index;
  401. /* skip this plane and planes on different CRTCs */
  402. if (p == tegra || p->dc != tegra->dc)
  403. continue;
  404. index = tegra_plane_get_overlap_index(tegra, p);
  405. if (new->fb && __drm_format_has_alpha(new->fb->format->format))
  406. state->blending[index].alpha = true;
  407. else
  408. state->blending[index].alpha = false;
  409. if (new->normalized_zpos > state->base.normalized_zpos)
  410. state->blending[index].top = true;
  411. else
  412. state->blending[index].top = false;
  413. /*
  414. * Missing framebuffer means that plane is disabled, in this
  415. * case mark B / C window as top to be able to differentiate
  416. * windows indices order in regards to zPos for the middle
  417. * window X / Y registers programming.
  418. */
  419. if (!new->fb)
  420. state->blending[index].top = (index == 1);
  421. }
  422. }
  423. static int tegra_plane_setup_transparency(struct tegra_plane *tegra,
  424. struct tegra_plane_state *state)
  425. {
  426. struct tegra_plane_state *tegra_state;
  427. struct drm_plane_state *new;
  428. struct drm_plane *plane;
  429. int err;
  430. /*
  431. * If planes zpos / transparency changed, sibling planes blending
  432. * state may require adjustment and in this case they will be included
  433. * into this atom commit, otherwise blending state is unchanged.
  434. */
  435. err = tegra_plane_check_transparency(tegra, state);
  436. if (err <= 0)
  437. return err;
  438. /*
  439. * All planes are now in the atomic state, walk them up and update
  440. * transparency state for each plane.
  441. */
  442. drm_for_each_plane(plane, tegra->base.dev) {
  443. struct tegra_plane *p = to_tegra_plane(plane);
  444. /* skip planes on different CRTCs */
  445. if (p->dc != tegra->dc)
  446. continue;
  447. new = drm_atomic_get_new_plane_state(state->base.state, plane);
  448. tegra_state = to_tegra_plane_state(new);
  449. /*
  450. * There is no need to update blending state for the disabled
  451. * plane.
  452. */
  453. if (new->fb)
  454. tegra_plane_update_transparency(p, tegra_state);
  455. }
  456. return 0;
  457. }
  458. int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
  459. struct tegra_plane_state *state)
  460. {
  461. int err;
  462. err = tegra_plane_setup_opacity(tegra, state);
  463. if (err < 0)
  464. return err;
  465. err = tegra_plane_setup_transparency(tegra, state);
  466. if (err < 0)
  467. return err;
  468. return 0;
  469. }