hdmi.h 21 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2012 Avionic Design GmbH
  4. * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  5. */
  6. #ifndef TEGRA_HDMI_H
  7. #define TEGRA_HDMI_H 1
  8. /* register definitions */
  9. #define HDMI_CTXSW 0x00
  10. #define HDMI_NV_PDISP_SOR_STATE0 0x01
  11. #define SOR_STATE_UPDATE (1 << 0)
  12. #define HDMI_NV_PDISP_SOR_STATE1 0x02
  13. #define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
  14. #define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
  15. #define SOR_STATE_ATTACHED (1 << 3)
  16. #define HDMI_NV_PDISP_SOR_STATE2 0x03
  17. #define SOR_STATE_ASY_OWNER_NONE (0 << 0)
  18. #define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
  19. #define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
  20. #define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
  21. #define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
  22. #define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
  23. #define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
  24. #define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
  25. #define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
  26. #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
  27. #define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
  28. #define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
  29. #define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
  30. #define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
  31. #define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
  32. #define SOR_STATE_ASY_DEPOL_POS (0 << 14)
  33. #define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
  34. #define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
  35. #define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
  36. #define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
  37. #define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
  38. #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
  39. #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
  40. #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
  41. #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
  42. #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
  43. #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
  44. #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
  45. #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
  46. #define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
  47. #define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
  48. #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
  49. #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
  50. #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
  51. #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
  52. #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
  53. #define HDMI_NV_PDISP_RG_HDCP_RI 0x17
  54. #define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
  55. #define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
  56. #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
  57. #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
  58. #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
  59. #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
  60. #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
  61. #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
  62. #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
  63. #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
  64. #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
  65. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
  66. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
  67. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
  68. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
  69. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
  70. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
  71. #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
  72. #define INFOFRAME_CTRL_ENABLE (1 << 0)
  73. #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
  74. #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
  75. #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
  76. #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
  77. #define GENERIC_CTRL_ENABLE (1 << 0)
  78. #define GENERIC_CTRL_OTHER (1 << 4)
  79. #define GENERIC_CTRL_SINGLE (1 << 8)
  80. #define GENERIC_CTRL_HBLANK (1 << 12)
  81. #define GENERIC_CTRL_AUDIO (1 << 16)
  82. #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
  83. #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
  84. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
  85. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
  86. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
  87. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
  88. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
  89. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
  90. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
  91. #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
  92. #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
  93. #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
  94. #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
  95. #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
  96. #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
  97. #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
  98. #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
  99. #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
  100. #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
  101. #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
  102. #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
  103. #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
  104. #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
  105. #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
  106. #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
  107. #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
  108. #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
  109. #define ACR_ENABLE (1 << 31)
  110. #define HDMI_NV_PDISP_HDMI_CTRL 0x44
  111. #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
  112. #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
  113. #define HDMI_CTRL_ENABLE (1 << 30)
  114. #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
  115. #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
  116. #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
  117. #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
  118. #define VSYNC_WINDOW_ENABLE (1 << 31)
  119. #define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
  120. #define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
  121. #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
  122. #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
  123. #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
  124. #define HDMI_NV_PDISP_HDMI_EMU0 0x4c
  125. #define HDMI_NV_PDISP_HDMI_EMU1 0x4d
  126. #define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
  127. #define HDMI_NV_PDISP_HDMI_SPARE 0x4f
  128. #define SPARE_HW_CTS (1 << 0)
  129. #define SPARE_FORCE_SW_CTS (1 << 1)
  130. #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
  131. #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
  132. #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
  133. #define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53
  134. #define HDMI_NV_PDISP_SOR_CAP 0x54
  135. #define HDMI_NV_PDISP_SOR_PWR 0x55
  136. #define SOR_PWR_NORMAL_STATE_PD (0 << 0)
  137. #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
  138. #define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
  139. #define SOR_PWR_NORMAL_START_ALT (1 << 1)
  140. #define SOR_PWR_SAFE_STATE_PD (0 << 16)
  141. #define SOR_PWR_SAFE_STATE_PU (1 << 16)
  142. #define SOR_PWR_SETTING_NEW_DONE (0 << 31)
  143. #define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
  144. #define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
  145. #define HDMI_NV_PDISP_SOR_TEST 0x56
  146. #define HDMI_NV_PDISP_SOR_PLL0 0x57
  147. #define SOR_PLL_PWR (1 << 0)
  148. #define SOR_PLL_PDBG (1 << 1)
  149. #define SOR_PLL_VCAPD (1 << 2)
  150. #define SOR_PLL_PDPORT (1 << 3)
  151. #define SOR_PLL_RESISTORSEL (1 << 4)
  152. #define SOR_PLL_PULLDOWN (1 << 5)
  153. #define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
  154. #define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
  155. #define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
  156. #define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
  157. #define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
  158. #define HDMI_NV_PDISP_SOR_PLL1 0x58
  159. #define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
  160. #define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
  161. #define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
  162. #define SOR_PLL_PE_EN (1 << 28)
  163. #define SOR_PLL_HALF_FULL_PE (1 << 29)
  164. #define SOR_PLL_S_D_PIN_PE (1 << 30)
  165. #define HDMI_NV_PDISP_SOR_PLL2 0x59
  166. #define HDMI_NV_PDISP_SOR_CSTM 0x5a
  167. #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
  168. #define SOR_CSTM_PLLDIV (1 << 21)
  169. #define SOR_CSTM_LVDS_ENABLE (1 << 16)
  170. #define SOR_CSTM_MODE_LVDS (0 << 12)
  171. #define SOR_CSTM_MODE_TMDS (1 << 12)
  172. #define SOR_CSTM_MODE_MASK (3 << 12)
  173. #define HDMI_NV_PDISP_SOR_LVDS 0x5b
  174. #define HDMI_NV_PDISP_SOR_CRCA 0x5c
  175. #define HDMI_NV_PDISP_SOR_CRCB 0x5d
  176. #define HDMI_NV_PDISP_SOR_BLANK 0x5e
  177. #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
  178. #define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
  179. #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
  180. #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
  181. #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
  182. #define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
  183. #define SOR_SEQ_STATUS (1 << 28)
  184. #define SOR_SEQ_SWITCH (1 << 30)
  185. #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x))
  186. #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
  187. #define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
  188. #define SOR_SEQ_INST_HALT (1 << 15)
  189. #define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
  190. #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
  191. #define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
  192. #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
  193. #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
  194. #define HDMI_NV_PDISP_SOR_VCRCA0 0x72
  195. #define HDMI_NV_PDISP_SOR_VCRCA1 0x73
  196. #define HDMI_NV_PDISP_SOR_CCRCA0 0x74
  197. #define HDMI_NV_PDISP_SOR_CCRCA1 0x75
  198. #define HDMI_NV_PDISP_SOR_EDATAA0 0x76
  199. #define HDMI_NV_PDISP_SOR_EDATAA1 0x77
  200. #define HDMI_NV_PDISP_SOR_COUNTA0 0x78
  201. #define HDMI_NV_PDISP_SOR_COUNTA1 0x79
  202. #define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
  203. #define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
  204. #define HDMI_NV_PDISP_SOR_TRIG 0x7c
  205. #define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
  206. #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
  207. #define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
  208. #define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
  209. #define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
  210. #define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
  211. #define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)
  212. #define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)
  213. #define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)
  214. #define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)
  215. #define DRIVE_CURRENT_1_500_mA 0x00
  216. #define DRIVE_CURRENT_1_875_mA 0x01
  217. #define DRIVE_CURRENT_2_250_mA 0x02
  218. #define DRIVE_CURRENT_2_625_mA 0x03
  219. #define DRIVE_CURRENT_3_000_mA 0x04
  220. #define DRIVE_CURRENT_3_375_mA 0x05
  221. #define DRIVE_CURRENT_3_750_mA 0x06
  222. #define DRIVE_CURRENT_4_125_mA 0x07
  223. #define DRIVE_CURRENT_4_500_mA 0x08
  224. #define DRIVE_CURRENT_4_875_mA 0x09
  225. #define DRIVE_CURRENT_5_250_mA 0x0a
  226. #define DRIVE_CURRENT_5_625_mA 0x0b
  227. #define DRIVE_CURRENT_6_000_mA 0x0c
  228. #define DRIVE_CURRENT_6_375_mA 0x0d
  229. #define DRIVE_CURRENT_6_750_mA 0x0e
  230. #define DRIVE_CURRENT_7_125_mA 0x0f
  231. #define DRIVE_CURRENT_7_500_mA 0x10
  232. #define DRIVE_CURRENT_7_875_mA 0x11
  233. #define DRIVE_CURRENT_8_250_mA 0x12
  234. #define DRIVE_CURRENT_8_625_mA 0x13
  235. #define DRIVE_CURRENT_9_000_mA 0x14
  236. #define DRIVE_CURRENT_9_375_mA 0x15
  237. #define DRIVE_CURRENT_9_750_mA 0x16
  238. #define DRIVE_CURRENT_10_125_mA 0x17
  239. #define DRIVE_CURRENT_10_500_mA 0x18
  240. #define DRIVE_CURRENT_10_875_mA 0x19
  241. #define DRIVE_CURRENT_11_250_mA 0x1a
  242. #define DRIVE_CURRENT_11_625_mA 0x1b
  243. #define DRIVE_CURRENT_12_000_mA 0x1c
  244. #define DRIVE_CURRENT_12_375_mA 0x1d
  245. #define DRIVE_CURRENT_12_750_mA 0x1e
  246. #define DRIVE_CURRENT_13_125_mA 0x1f
  247. #define DRIVE_CURRENT_13_500_mA 0x20
  248. #define DRIVE_CURRENT_13_875_mA 0x21
  249. #define DRIVE_CURRENT_14_250_mA 0x22
  250. #define DRIVE_CURRENT_14_625_mA 0x23
  251. #define DRIVE_CURRENT_15_000_mA 0x24
  252. #define DRIVE_CURRENT_15_375_mA 0x25
  253. #define DRIVE_CURRENT_15_750_mA 0x26
  254. #define DRIVE_CURRENT_16_125_mA 0x27
  255. #define DRIVE_CURRENT_16_500_mA 0x28
  256. #define DRIVE_CURRENT_16_875_mA 0x29
  257. #define DRIVE_CURRENT_17_250_mA 0x2a
  258. #define DRIVE_CURRENT_17_625_mA 0x2b
  259. #define DRIVE_CURRENT_18_000_mA 0x2c
  260. #define DRIVE_CURRENT_18_375_mA 0x2d
  261. #define DRIVE_CURRENT_18_750_mA 0x2e
  262. #define DRIVE_CURRENT_19_125_mA 0x2f
  263. #define DRIVE_CURRENT_19_500_mA 0x30
  264. #define DRIVE_CURRENT_19_875_mA 0x31
  265. #define DRIVE_CURRENT_20_250_mA 0x32
  266. #define DRIVE_CURRENT_20_625_mA 0x33
  267. #define DRIVE_CURRENT_21_000_mA 0x34
  268. #define DRIVE_CURRENT_21_375_mA 0x35
  269. #define DRIVE_CURRENT_21_750_mA 0x36
  270. #define DRIVE_CURRENT_22_125_mA 0x37
  271. #define DRIVE_CURRENT_22_500_mA 0x38
  272. #define DRIVE_CURRENT_22_875_mA 0x39
  273. #define DRIVE_CURRENT_23_250_mA 0x3a
  274. #define DRIVE_CURRENT_23_625_mA 0x3b
  275. #define DRIVE_CURRENT_24_000_mA 0x3c
  276. #define DRIVE_CURRENT_24_375_mA 0x3d
  277. #define DRIVE_CURRENT_24_750_mA 0x3e
  278. #define DRIVE_CURRENT_0_000_mA_T114 0x00
  279. #define DRIVE_CURRENT_0_400_mA_T114 0x01
  280. #define DRIVE_CURRENT_0_800_mA_T114 0x02
  281. #define DRIVE_CURRENT_1_200_mA_T114 0x03
  282. #define DRIVE_CURRENT_1_600_mA_T114 0x04
  283. #define DRIVE_CURRENT_2_000_mA_T114 0x05
  284. #define DRIVE_CURRENT_2_400_mA_T114 0x06
  285. #define DRIVE_CURRENT_2_800_mA_T114 0x07
  286. #define DRIVE_CURRENT_3_200_mA_T114 0x08
  287. #define DRIVE_CURRENT_3_600_mA_T114 0x09
  288. #define DRIVE_CURRENT_4_000_mA_T114 0x0a
  289. #define DRIVE_CURRENT_4_400_mA_T114 0x0b
  290. #define DRIVE_CURRENT_4_800_mA_T114 0x0c
  291. #define DRIVE_CURRENT_5_200_mA_T114 0x0d
  292. #define DRIVE_CURRENT_5_600_mA_T114 0x0e
  293. #define DRIVE_CURRENT_6_000_mA_T114 0x0f
  294. #define DRIVE_CURRENT_6_400_mA_T114 0x10
  295. #define DRIVE_CURRENT_6_800_mA_T114 0x11
  296. #define DRIVE_CURRENT_7_200_mA_T114 0x12
  297. #define DRIVE_CURRENT_7_600_mA_T114 0x13
  298. #define DRIVE_CURRENT_8_000_mA_T114 0x14
  299. #define DRIVE_CURRENT_8_400_mA_T114 0x15
  300. #define DRIVE_CURRENT_8_800_mA_T114 0x16
  301. #define DRIVE_CURRENT_9_200_mA_T114 0x17
  302. #define DRIVE_CURRENT_9_600_mA_T114 0x18
  303. #define DRIVE_CURRENT_10_000_mA_T114 0x19
  304. #define DRIVE_CURRENT_10_400_mA_T114 0x1a
  305. #define DRIVE_CURRENT_10_800_mA_T114 0x1b
  306. #define DRIVE_CURRENT_11_200_mA_T114 0x1c
  307. #define DRIVE_CURRENT_11_600_mA_T114 0x1d
  308. #define DRIVE_CURRENT_12_000_mA_T114 0x1e
  309. #define DRIVE_CURRENT_12_400_mA_T114 0x1f
  310. #define DRIVE_CURRENT_12_800_mA_T114 0x20
  311. #define DRIVE_CURRENT_13_200_mA_T114 0x21
  312. #define DRIVE_CURRENT_13_600_mA_T114 0x22
  313. #define DRIVE_CURRENT_14_000_mA_T114 0x23
  314. #define DRIVE_CURRENT_14_400_mA_T114 0x24
  315. #define DRIVE_CURRENT_14_800_mA_T114 0x25
  316. #define DRIVE_CURRENT_15_200_mA_T114 0x26
  317. #define DRIVE_CURRENT_15_600_mA_T114 0x27
  318. #define DRIVE_CURRENT_16_000_mA_T114 0x28
  319. #define DRIVE_CURRENT_16_400_mA_T114 0x29
  320. #define DRIVE_CURRENT_16_800_mA_T114 0x2a
  321. #define DRIVE_CURRENT_17_200_mA_T114 0x2b
  322. #define DRIVE_CURRENT_17_600_mA_T114 0x2c
  323. #define DRIVE_CURRENT_18_000_mA_T114 0x2d
  324. #define DRIVE_CURRENT_18_400_mA_T114 0x2e
  325. #define DRIVE_CURRENT_18_800_mA_T114 0x2f
  326. #define DRIVE_CURRENT_19_200_mA_T114 0x30
  327. #define DRIVE_CURRENT_19_600_mA_T114 0x31
  328. #define DRIVE_CURRENT_20_000_mA_T114 0x32
  329. #define DRIVE_CURRENT_20_400_mA_T114 0x33
  330. #define DRIVE_CURRENT_20_800_mA_T114 0x34
  331. #define DRIVE_CURRENT_21_200_mA_T114 0x35
  332. #define DRIVE_CURRENT_21_600_mA_T114 0x36
  333. #define DRIVE_CURRENT_22_000_mA_T114 0x37
  334. #define DRIVE_CURRENT_22_400_mA_T114 0x38
  335. #define DRIVE_CURRENT_22_800_mA_T114 0x39
  336. #define DRIVE_CURRENT_23_200_mA_T114 0x3a
  337. #define DRIVE_CURRENT_23_600_mA_T114 0x3b
  338. #define DRIVE_CURRENT_24_000_mA_T114 0x3c
  339. #define DRIVE_CURRENT_24_400_mA_T114 0x3d
  340. #define DRIVE_CURRENT_24_800_mA_T114 0x3e
  341. #define DRIVE_CURRENT_25_200_mA_T114 0x3f
  342. #define DRIVE_CURRENT_25_400_mA_T114 0x40
  343. #define DRIVE_CURRENT_25_800_mA_T114 0x41
  344. #define DRIVE_CURRENT_26_200_mA_T114 0x42
  345. #define DRIVE_CURRENT_26_600_mA_T114 0x43
  346. #define DRIVE_CURRENT_27_000_mA_T114 0x44
  347. #define DRIVE_CURRENT_27_400_mA_T114 0x45
  348. #define DRIVE_CURRENT_27_800_mA_T114 0x46
  349. #define DRIVE_CURRENT_28_200_mA_T114 0x47
  350. #define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
  351. #define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
  352. #define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
  353. #define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
  354. #define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
  355. #define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
  356. #define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
  357. #define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
  358. #define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
  359. #define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
  360. #define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
  361. #define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
  362. #define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
  363. #define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
  364. #define HDMI_NV_PDISP_AUDIO_N 0x8c
  365. #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
  366. #define AUDIO_N_RESETF (1 << 20)
  367. #define AUDIO_N_GENERATE_NORMAL (0 << 24)
  368. #define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
  369. #define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
  370. #define HDMI_NV_PDISP_SOR_REFCLK 0x95
  371. #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
  372. #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
  373. #define HDMI_NV_PDISP_CRC_CONTROL 0x96
  374. #define HDMI_NV_PDISP_INPUT_CONTROL 0x97
  375. #define HDMI_SRC_DISPLAYA (0 << 0)
  376. #define HDMI_SRC_DISPLAYB (1 << 0)
  377. #define ARM_VIDEO_RANGE_FULL (0 << 1)
  378. #define ARM_VIDEO_RANGE_LIMITED (1 << 1)
  379. #define HDMI_NV_PDISP_SCRATCH 0x98
  380. #define HDMI_NV_PDISP_PE_CURRENT 0x99
  381. #define PE_CURRENT0(x) (((x) & 0xf) << 0)
  382. #define PE_CURRENT1(x) (((x) & 0xf) << 8)
  383. #define PE_CURRENT2(x) (((x) & 0xf) << 16)
  384. #define PE_CURRENT3(x) (((x) & 0xf) << 24)
  385. #define PE_CURRENT_0_0_mA 0x0
  386. #define PE_CURRENT_0_5_mA 0x1
  387. #define PE_CURRENT_1_0_mA 0x2
  388. #define PE_CURRENT_1_5_mA 0x3
  389. #define PE_CURRENT_2_0_mA 0x4
  390. #define PE_CURRENT_2_5_mA 0x5
  391. #define PE_CURRENT_3_0_mA 0x6
  392. #define PE_CURRENT_3_5_mA 0x7
  393. #define PE_CURRENT_4_0_mA 0x8
  394. #define PE_CURRENT_4_5_mA 0x9
  395. #define PE_CURRENT_5_0_mA 0xa
  396. #define PE_CURRENT_5_5_mA 0xb
  397. #define PE_CURRENT_6_0_mA 0xc
  398. #define PE_CURRENT_6_5_mA 0xd
  399. #define PE_CURRENT_7_0_mA 0xe
  400. #define PE_CURRENT_7_5_mA 0xf
  401. #define PE_CURRENT_0_mA_T114 0x0
  402. #define PE_CURRENT_1_mA_T114 0x1
  403. #define PE_CURRENT_2_mA_T114 0x2
  404. #define PE_CURRENT_3_mA_T114 0x3
  405. #define PE_CURRENT_4_mA_T114 0x4
  406. #define PE_CURRENT_5_mA_T114 0x5
  407. #define PE_CURRENT_6_mA_T114 0x6
  408. #define PE_CURRENT_7_mA_T114 0x7
  409. #define PE_CURRENT_8_mA_T114 0x8
  410. #define PE_CURRENT_9_mA_T114 0x9
  411. #define PE_CURRENT_10_mA_T114 0xa
  412. #define PE_CURRENT_11_mA_T114 0xb
  413. #define PE_CURRENT_12_mA_T114 0xc
  414. #define PE_CURRENT_13_mA_T114 0xd
  415. #define PE_CURRENT_14_mA_T114 0xe
  416. #define PE_CURRENT_15_mA_T114 0xf
  417. #define HDMI_NV_PDISP_KEY_CTRL 0x9a
  418. #define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
  419. #define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
  420. #define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
  421. #define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
  422. #define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
  423. #define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
  424. #define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
  425. #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
  426. #define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
  427. #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac
  428. #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
  429. #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
  430. #define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
  431. #define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
  432. #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0xae
  433. #define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27)
  434. #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0xba
  435. #define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)
  436. #define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff
  437. #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0xbb
  438. #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc
  439. #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd
  440. #define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1)
  441. #define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)
  442. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf
  443. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0
  444. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1
  445. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2
  446. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3
  447. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4
  448. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
  449. #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
  450. #define HDMI_NV_PDISP_INT_STATUS 0xcc
  451. #define INT_SCRATCH (1 << 3)
  452. #define INT_CP_REQUEST (1 << 2)
  453. #define INT_CODEC_SCRATCH1 (1 << 1)
  454. #define INT_CODEC_SCRATCH0 (1 << 0)
  455. #define HDMI_NV_PDISP_INT_MASK 0xcd
  456. #define HDMI_NV_PDISP_INT_ENABLE 0xce
  457. #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1
  458. #define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)
  459. #define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)
  460. #define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)
  461. #define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)
  462. #define PEAK_CURRENT_0_000_mA 0x00
  463. #define PEAK_CURRENT_0_200_mA 0x01
  464. #define PEAK_CURRENT_0_400_mA 0x02
  465. #define PEAK_CURRENT_0_600_mA 0x03
  466. #define PEAK_CURRENT_0_800_mA 0x04
  467. #define PEAK_CURRENT_1_000_mA 0x05
  468. #define PEAK_CURRENT_1_200_mA 0x06
  469. #define PEAK_CURRENT_1_400_mA 0x07
  470. #define PEAK_CURRENT_1_600_mA 0x08
  471. #define PEAK_CURRENT_1_800_mA 0x09
  472. #define PEAK_CURRENT_2_000_mA 0x0a
  473. #define PEAK_CURRENT_2_200_mA 0x0b
  474. #define PEAK_CURRENT_2_400_mA 0x0c
  475. #define PEAK_CURRENT_2_600_mA 0x0d
  476. #define PEAK_CURRENT_2_800_mA 0x0e
  477. #define PEAK_CURRENT_3_000_mA 0x0f
  478. #define PEAK_CURRENT_3_200_mA 0x10
  479. #define PEAK_CURRENT_3_400_mA 0x11
  480. #define PEAK_CURRENT_3_600_mA 0x12
  481. #define PEAK_CURRENT_3_800_mA 0x13
  482. #define PEAK_CURRENT_4_000_mA 0x14
  483. #define PEAK_CURRENT_4_200_mA 0x15
  484. #define PEAK_CURRENT_4_400_mA 0x16
  485. #define PEAK_CURRENT_4_600_mA 0x17
  486. #define PEAK_CURRENT_4_800_mA 0x18
  487. #define PEAK_CURRENT_5_000_mA 0x19
  488. #define PEAK_CURRENT_5_200_mA 0x1a
  489. #define PEAK_CURRENT_5_400_mA 0x1b
  490. #define PEAK_CURRENT_5_600_mA 0x1c
  491. #define PEAK_CURRENT_5_800_mA 0x1d
  492. #define PEAK_CURRENT_6_000_mA 0x1e
  493. #define PEAK_CURRENT_6_200_mA 0x1f
  494. #define PEAK_CURRENT_6_400_mA 0x20
  495. #define PEAK_CURRENT_6_600_mA 0x21
  496. #define PEAK_CURRENT_6_800_mA 0x22
  497. #define PEAK_CURRENT_7_000_mA 0x23
  498. #define PEAK_CURRENT_7_200_mA 0x24
  499. #define PEAK_CURRENT_7_400_mA 0x25
  500. #define PEAK_CURRENT_7_600_mA 0x26
  501. #define PEAK_CURRENT_7_800_mA 0x27
  502. #define PEAK_CURRENT_8_000_mA 0x28
  503. #define PEAK_CURRENT_8_200_mA 0x29
  504. #define PEAK_CURRENT_8_400_mA 0x2a
  505. #define PEAK_CURRENT_8_600_mA 0x2b
  506. #define PEAK_CURRENT_8_800_mA 0x2c
  507. #define PEAK_CURRENT_9_000_mA 0x2d
  508. #define PEAK_CURRENT_9_200_mA 0x2e
  509. #define PEAK_CURRENT_9_400_mA 0x2f
  510. #define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2
  511. #endif /* TEGRA_HDMI_H */