hdmi.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Avionic Design GmbH
  4. * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/debugfs.h>
  8. #include <linux/delay.h>
  9. #include <linux/hdmi.h>
  10. #include <linux/math64.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/reset.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc.h>
  18. #include <drm/drm_debugfs.h>
  19. #include <drm/drm_file.h>
  20. #include <drm/drm_fourcc.h>
  21. #include <drm/drm_probe_helper.h>
  22. #include <drm/drm_simple_kms_helper.h>
  23. #include "hda.h"
  24. #include "hdmi.h"
  25. #include "drm.h"
  26. #include "dc.h"
  27. #include "trace.h"
  28. #define HDMI_ELD_BUFFER_SIZE 96
  29. struct tmds_config {
  30. unsigned int pclk;
  31. u32 pll0;
  32. u32 pll1;
  33. u32 pe_current;
  34. u32 drive_current;
  35. u32 peak_current;
  36. };
  37. struct tegra_hdmi_config {
  38. const struct tmds_config *tmds;
  39. unsigned int num_tmds;
  40. unsigned long fuse_override_offset;
  41. u32 fuse_override_value;
  42. bool has_sor_io_peak_current;
  43. bool has_hda;
  44. bool has_hbr;
  45. };
  46. struct tegra_hdmi {
  47. struct host1x_client client;
  48. struct tegra_output output;
  49. struct device *dev;
  50. struct regulator *hdmi;
  51. struct regulator *pll;
  52. struct regulator *vdd;
  53. void __iomem *regs;
  54. unsigned int irq;
  55. struct clk *clk_parent;
  56. struct clk *clk;
  57. struct reset_control *rst;
  58. const struct tegra_hdmi_config *config;
  59. unsigned int audio_source;
  60. struct tegra_hda_format format;
  61. unsigned int pixel_clock;
  62. bool stereo;
  63. bool dvi;
  64. struct drm_info_list *debugfs_files;
  65. };
  66. static inline struct tegra_hdmi *
  67. host1x_client_to_hdmi(struct host1x_client *client)
  68. {
  69. return container_of(client, struct tegra_hdmi, client);
  70. }
  71. static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
  72. {
  73. return container_of(output, struct tegra_hdmi, output);
  74. }
  75. #define HDMI_AUDIOCLK_FREQ 216000000
  76. #define HDMI_REKEY_DEFAULT 56
  77. enum {
  78. AUTO = 0,
  79. SPDIF,
  80. HDA,
  81. };
  82. static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
  83. unsigned int offset)
  84. {
  85. u32 value = readl(hdmi->regs + (offset << 2));
  86. trace_hdmi_readl(hdmi->dev, offset, value);
  87. return value;
  88. }
  89. static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
  90. unsigned int offset)
  91. {
  92. trace_hdmi_writel(hdmi->dev, offset, value);
  93. writel(value, hdmi->regs + (offset << 2));
  94. }
  95. struct tegra_hdmi_audio_config {
  96. unsigned int n;
  97. unsigned int cts;
  98. unsigned int aval;
  99. };
  100. static const struct tmds_config tegra20_tmds_config[] = {
  101. { /* slow pixel clock modes */
  102. .pclk = 27000000,
  103. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  104. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
  105. SOR_PLL_TX_REG_LOAD(3),
  106. .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
  107. .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
  108. PE_CURRENT1(PE_CURRENT_0_0_mA) |
  109. PE_CURRENT2(PE_CURRENT_0_0_mA) |
  110. PE_CURRENT3(PE_CURRENT_0_0_mA),
  111. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
  112. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
  113. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
  114. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
  115. },
  116. { /* high pixel clock modes */
  117. .pclk = UINT_MAX,
  118. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  119. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
  120. SOR_PLL_TX_REG_LOAD(3),
  121. .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
  122. .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
  123. PE_CURRENT1(PE_CURRENT_6_0_mA) |
  124. PE_CURRENT2(PE_CURRENT_6_0_mA) |
  125. PE_CURRENT3(PE_CURRENT_6_0_mA),
  126. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
  127. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
  128. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
  129. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
  130. },
  131. };
  132. static const struct tmds_config tegra30_tmds_config[] = {
  133. { /* 480p modes */
  134. .pclk = 27000000,
  135. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  136. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
  137. SOR_PLL_TX_REG_LOAD(0),
  138. .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
  139. .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
  140. PE_CURRENT1(PE_CURRENT_0_0_mA) |
  141. PE_CURRENT2(PE_CURRENT_0_0_mA) |
  142. PE_CURRENT3(PE_CURRENT_0_0_mA),
  143. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
  144. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
  145. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
  146. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
  147. }, { /* 720p modes */
  148. .pclk = 74250000,
  149. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  150. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
  151. SOR_PLL_TX_REG_LOAD(0),
  152. .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
  153. .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
  154. PE_CURRENT1(PE_CURRENT_5_0_mA) |
  155. PE_CURRENT2(PE_CURRENT_5_0_mA) |
  156. PE_CURRENT3(PE_CURRENT_5_0_mA),
  157. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
  158. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
  159. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
  160. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
  161. }, { /* 1080p modes */
  162. .pclk = UINT_MAX,
  163. .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
  164. SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
  165. SOR_PLL_TX_REG_LOAD(0),
  166. .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
  167. .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
  168. PE_CURRENT1(PE_CURRENT_5_0_mA) |
  169. PE_CURRENT2(PE_CURRENT_5_0_mA) |
  170. PE_CURRENT3(PE_CURRENT_5_0_mA),
  171. .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
  172. DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
  173. DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
  174. DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
  175. },
  176. };
  177. static const struct tmds_config tegra114_tmds_config[] = {
  178. { /* 480p/576p / 25.2MHz/27MHz modes */
  179. .pclk = 27000000,
  180. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  181. SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
  182. .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
  183. .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
  184. PE_CURRENT1(PE_CURRENT_0_mA_T114) |
  185. PE_CURRENT2(PE_CURRENT_0_mA_T114) |
  186. PE_CURRENT3(PE_CURRENT_0_mA_T114),
  187. .drive_current =
  188. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
  189. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
  190. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
  191. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
  192. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
  193. PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
  194. PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
  195. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
  196. }, { /* 720p / 74.25MHz modes */
  197. .pclk = 74250000,
  198. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  199. SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
  200. .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
  201. SOR_PLL_TMDS_TERMADJ(0),
  202. .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
  203. PE_CURRENT1(PE_CURRENT_15_mA_T114) |
  204. PE_CURRENT2(PE_CURRENT_15_mA_T114) |
  205. PE_CURRENT3(PE_CURRENT_15_mA_T114),
  206. .drive_current =
  207. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
  208. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
  209. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
  210. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
  211. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
  212. PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
  213. PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
  214. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
  215. }, { /* 1080p / 148.5MHz modes */
  216. .pclk = 148500000,
  217. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  218. SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
  219. .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
  220. SOR_PLL_TMDS_TERMADJ(0),
  221. .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
  222. PE_CURRENT1(PE_CURRENT_10_mA_T114) |
  223. PE_CURRENT2(PE_CURRENT_10_mA_T114) |
  224. PE_CURRENT3(PE_CURRENT_10_mA_T114),
  225. .drive_current =
  226. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
  227. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
  228. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
  229. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
  230. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
  231. PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
  232. PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
  233. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
  234. }, { /* 225/297MHz modes */
  235. .pclk = UINT_MAX,
  236. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  237. SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
  238. .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
  239. | SOR_PLL_TMDS_TERM_ENABLE,
  240. .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
  241. PE_CURRENT1(PE_CURRENT_0_mA_T114) |
  242. PE_CURRENT2(PE_CURRENT_0_mA_T114) |
  243. PE_CURRENT3(PE_CURRENT_0_mA_T114),
  244. .drive_current =
  245. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
  246. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
  247. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
  248. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
  249. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
  250. PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
  251. PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
  252. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
  253. },
  254. };
  255. static const struct tmds_config tegra124_tmds_config[] = {
  256. { /* 480p/576p / 25.2MHz/27MHz modes */
  257. .pclk = 27000000,
  258. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  259. SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
  260. .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
  261. .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
  262. PE_CURRENT1(PE_CURRENT_0_mA_T114) |
  263. PE_CURRENT2(PE_CURRENT_0_mA_T114) |
  264. PE_CURRENT3(PE_CURRENT_0_mA_T114),
  265. .drive_current =
  266. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
  267. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
  268. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
  269. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
  270. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
  271. PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
  272. PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
  273. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
  274. }, { /* 720p / 74.25MHz modes */
  275. .pclk = 74250000,
  276. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  277. SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
  278. .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
  279. SOR_PLL_TMDS_TERMADJ(0),
  280. .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
  281. PE_CURRENT1(PE_CURRENT_15_mA_T114) |
  282. PE_CURRENT2(PE_CURRENT_15_mA_T114) |
  283. PE_CURRENT3(PE_CURRENT_15_mA_T114),
  284. .drive_current =
  285. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
  286. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
  287. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
  288. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
  289. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
  290. PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
  291. PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
  292. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
  293. }, { /* 1080p / 148.5MHz modes */
  294. .pclk = 148500000,
  295. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  296. SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
  297. .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
  298. SOR_PLL_TMDS_TERMADJ(0),
  299. .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
  300. PE_CURRENT1(PE_CURRENT_10_mA_T114) |
  301. PE_CURRENT2(PE_CURRENT_10_mA_T114) |
  302. PE_CURRENT3(PE_CURRENT_10_mA_T114),
  303. .drive_current =
  304. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
  305. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
  306. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
  307. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
  308. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
  309. PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
  310. PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
  311. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
  312. }, { /* 225/297MHz modes */
  313. .pclk = UINT_MAX,
  314. .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
  315. SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
  316. .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
  317. | SOR_PLL_TMDS_TERM_ENABLE,
  318. .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
  319. PE_CURRENT1(PE_CURRENT_0_mA_T114) |
  320. PE_CURRENT2(PE_CURRENT_0_mA_T114) |
  321. PE_CURRENT3(PE_CURRENT_0_mA_T114),
  322. .drive_current =
  323. DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
  324. DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
  325. DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
  326. DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
  327. .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
  328. PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
  329. PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
  330. PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
  331. },
  332. };
  333. static int
  334. tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
  335. struct tegra_hdmi_audio_config *config)
  336. {
  337. const unsigned int afreq = 128 * audio_freq;
  338. const unsigned int min_n = afreq / 1500;
  339. const unsigned int max_n = afreq / 300;
  340. const unsigned int ideal_n = afreq / 1000;
  341. int64_t min_err = (uint64_t)-1 >> 1;
  342. unsigned int min_delta = -1;
  343. int n;
  344. memset(config, 0, sizeof(*config));
  345. config->n = -1;
  346. for (n = min_n; n <= max_n; n++) {
  347. uint64_t cts_f, aval_f;
  348. unsigned int delta;
  349. int64_t cts, err;
  350. /* compute aval in 48.16 fixed point */
  351. aval_f = ((int64_t)24000000 << 16) * n;
  352. do_div(aval_f, afreq);
  353. /* It should round without any rest */
  354. if (aval_f & 0xFFFF)
  355. continue;
  356. /* Compute cts in 48.16 fixed point */
  357. cts_f = ((int64_t)pix_clock << 16) * n;
  358. do_div(cts_f, afreq);
  359. /* Round it to the nearest integer */
  360. cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
  361. delta = abs(n - ideal_n);
  362. /* Compute the absolute error */
  363. err = abs((int64_t)cts_f - cts);
  364. if (err < min_err || (err == min_err && delta < min_delta)) {
  365. config->n = n;
  366. config->cts = cts >> 16;
  367. config->aval = aval_f >> 16;
  368. min_delta = delta;
  369. min_err = err;
  370. }
  371. }
  372. return config->n != -1 ? 0 : -EINVAL;
  373. }
  374. static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
  375. {
  376. const unsigned int freqs[] = {
  377. 32000, 44100, 48000, 88200, 96000, 176400, 192000
  378. };
  379. unsigned int i;
  380. for (i = 0; i < ARRAY_SIZE(freqs); i++) {
  381. unsigned int f = freqs[i];
  382. unsigned int eight_half;
  383. unsigned int delta;
  384. u32 value;
  385. if (f > 96000)
  386. delta = 2;
  387. else if (f > 48000)
  388. delta = 6;
  389. else
  390. delta = 9;
  391. eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
  392. value = AUDIO_FS_LOW(eight_half - delta) |
  393. AUDIO_FS_HIGH(eight_half + delta);
  394. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
  395. }
  396. }
  397. static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
  398. {
  399. static const struct {
  400. unsigned int sample_rate;
  401. unsigned int offset;
  402. } regs[] = {
  403. { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
  404. { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
  405. { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
  406. { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
  407. { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
  408. { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
  409. { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
  410. };
  411. unsigned int i;
  412. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  413. if (regs[i].sample_rate == hdmi->format.sample_rate) {
  414. tegra_hdmi_writel(hdmi, value, regs[i].offset);
  415. break;
  416. }
  417. }
  418. }
  419. static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
  420. {
  421. struct tegra_hdmi_audio_config config;
  422. u32 source, value;
  423. int err;
  424. switch (hdmi->audio_source) {
  425. case HDA:
  426. if (hdmi->config->has_hda)
  427. source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
  428. else
  429. return -EINVAL;
  430. break;
  431. case SPDIF:
  432. if (hdmi->config->has_hda)
  433. source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
  434. else
  435. source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
  436. break;
  437. default:
  438. if (hdmi->config->has_hda)
  439. source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
  440. else
  441. source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
  442. break;
  443. }
  444. /*
  445. * Tegra30 and later use a slightly modified version of the register
  446. * layout to accomodate for changes related to supporting HDA as the
  447. * audio input source for HDMI. The source select field has moved to
  448. * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
  449. * per block fields remain in the AUDIO_CNTRL0 register.
  450. */
  451. if (hdmi->config->has_hda) {
  452. /*
  453. * Inject null samples into the audio FIFO for every frame in
  454. * which the codec did not receive any samples. This applies
  455. * to stereo LPCM only.
  456. *
  457. * XXX: This seems to be a remnant of MCP days when this was
  458. * used to work around issues with monitors not being able to
  459. * play back system startup sounds early. It is possibly not
  460. * needed on Linux at all.
  461. */
  462. if (hdmi->format.channels == 2)
  463. value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
  464. else
  465. value = 0;
  466. value |= source;
  467. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
  468. }
  469. /*
  470. * On Tegra20, HDA is not a supported audio source and the source
  471. * select field is part of the AUDIO_CNTRL0 register.
  472. */
  473. value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
  474. AUDIO_CNTRL0_ERROR_TOLERANCE(6);
  475. if (!hdmi->config->has_hda)
  476. value |= source;
  477. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
  478. /*
  479. * Advertise support for High Bit-Rate on Tegra114 and later.
  480. */
  481. if (hdmi->config->has_hbr) {
  482. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
  483. value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
  484. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
  485. }
  486. err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
  487. hdmi->pixel_clock, &config);
  488. if (err < 0) {
  489. dev_err(hdmi->dev,
  490. "cannot set audio to %u Hz at %u Hz pixel clock\n",
  491. hdmi->format.sample_rate, hdmi->pixel_clock);
  492. return err;
  493. }
  494. dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
  495. hdmi->pixel_clock, config.n, config.cts, config.aval);
  496. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
  497. value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
  498. AUDIO_N_VALUE(config.n - 1);
  499. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
  500. tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
  501. HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
  502. tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
  503. HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
  504. value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
  505. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
  506. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
  507. value &= ~AUDIO_N_RESETF;
  508. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
  509. if (hdmi->config->has_hda)
  510. tegra_hdmi_write_aval(hdmi, config.aval);
  511. tegra_hdmi_setup_audio_fs_tables(hdmi);
  512. return 0;
  513. }
  514. static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
  515. {
  516. u32 value;
  517. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  518. value &= ~GENERIC_CTRL_AUDIO;
  519. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  520. }
  521. static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
  522. {
  523. u32 value;
  524. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  525. value |= GENERIC_CTRL_AUDIO;
  526. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  527. }
  528. static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
  529. {
  530. size_t length = drm_eld_size(hdmi->output.connector.eld), i;
  531. u32 value;
  532. for (i = 0; i < length; i++)
  533. tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
  534. HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
  535. /*
  536. * The HDA codec will always report an ELD buffer size of 96 bytes and
  537. * the HDA codec driver will check that each byte read from the buffer
  538. * is valid. Therefore every byte must be written, even if no 96 bytes
  539. * were parsed from EDID.
  540. */
  541. for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
  542. tegra_hdmi_writel(hdmi, i << 8 | 0,
  543. HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
  544. value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
  545. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
  546. }
  547. static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
  548. {
  549. u32 value = 0;
  550. size_t i;
  551. for (i = size; i > 0; i--)
  552. value = (value << 8) | ptr[i - 1];
  553. return value;
  554. }
  555. static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
  556. size_t size)
  557. {
  558. const u8 *ptr = data;
  559. unsigned long offset;
  560. size_t i, j;
  561. u32 value;
  562. switch (ptr[0]) {
  563. case HDMI_INFOFRAME_TYPE_AVI:
  564. offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
  565. break;
  566. case HDMI_INFOFRAME_TYPE_AUDIO:
  567. offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
  568. break;
  569. case HDMI_INFOFRAME_TYPE_VENDOR:
  570. offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
  571. break;
  572. default:
  573. dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
  574. ptr[0]);
  575. return;
  576. }
  577. value = INFOFRAME_HEADER_TYPE(ptr[0]) |
  578. INFOFRAME_HEADER_VERSION(ptr[1]) |
  579. INFOFRAME_HEADER_LEN(ptr[2]);
  580. tegra_hdmi_writel(hdmi, value, offset);
  581. offset++;
  582. /*
  583. * Each subpack contains 7 bytes, divided into:
  584. * - subpack_low: bytes 0 - 3
  585. * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
  586. */
  587. for (i = 3, j = 0; i < size; i += 7, j += 8) {
  588. size_t rem = size - i, num = min_t(size_t, rem, 4);
  589. value = tegra_hdmi_subpack(&ptr[i], num);
  590. tegra_hdmi_writel(hdmi, value, offset++);
  591. num = min_t(size_t, rem - num, 3);
  592. value = tegra_hdmi_subpack(&ptr[i + 4], num);
  593. tegra_hdmi_writel(hdmi, value, offset++);
  594. }
  595. }
  596. static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
  597. struct drm_display_mode *mode)
  598. {
  599. struct hdmi_avi_infoframe frame;
  600. u8 buffer[17];
  601. ssize_t err;
  602. err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
  603. &hdmi->output.connector, mode);
  604. if (err < 0) {
  605. dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
  606. return;
  607. }
  608. err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  609. if (err < 0) {
  610. dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
  611. return;
  612. }
  613. tegra_hdmi_write_infopack(hdmi, buffer, err);
  614. }
  615. static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
  616. {
  617. u32 value;
  618. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  619. value &= ~INFOFRAME_CTRL_ENABLE;
  620. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  621. }
  622. static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
  623. {
  624. u32 value;
  625. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  626. value |= INFOFRAME_CTRL_ENABLE;
  627. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
  628. }
  629. static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
  630. {
  631. struct hdmi_audio_infoframe frame;
  632. u8 buffer[14];
  633. ssize_t err;
  634. err = hdmi_audio_infoframe_init(&frame);
  635. if (err < 0) {
  636. dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
  637. err);
  638. return;
  639. }
  640. frame.channels = hdmi->format.channels;
  641. err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
  642. if (err < 0) {
  643. dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
  644. err);
  645. return;
  646. }
  647. /*
  648. * The audio infoframe has only one set of subpack registers, so the
  649. * infoframe needs to be truncated. One set of subpack registers can
  650. * contain 7 bytes. Including the 3 byte header only the first 10
  651. * bytes can be programmed.
  652. */
  653. tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
  654. }
  655. static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
  656. {
  657. u32 value;
  658. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  659. value &= ~INFOFRAME_CTRL_ENABLE;
  660. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  661. }
  662. static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
  663. {
  664. u32 value;
  665. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  666. value |= INFOFRAME_CTRL_ENABLE;
  667. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
  668. }
  669. static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
  670. {
  671. struct hdmi_vendor_infoframe frame;
  672. u8 buffer[10];
  673. ssize_t err;
  674. hdmi_vendor_infoframe_init(&frame);
  675. frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
  676. err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
  677. if (err < 0) {
  678. dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
  679. err);
  680. return;
  681. }
  682. tegra_hdmi_write_infopack(hdmi, buffer, err);
  683. }
  684. static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
  685. {
  686. u32 value;
  687. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  688. value &= ~GENERIC_CTRL_ENABLE;
  689. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  690. }
  691. static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
  692. {
  693. u32 value;
  694. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  695. value |= GENERIC_CTRL_ENABLE;
  696. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
  697. }
  698. static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
  699. const struct tmds_config *tmds)
  700. {
  701. u32 value;
  702. tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
  703. tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
  704. tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
  705. tegra_hdmi_writel(hdmi, tmds->drive_current,
  706. HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
  707. value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
  708. value |= hdmi->config->fuse_override_value;
  709. tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
  710. if (hdmi->config->has_sor_io_peak_current)
  711. tegra_hdmi_writel(hdmi, tmds->peak_current,
  712. HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
  713. }
  714. static bool tegra_output_is_hdmi(struct tegra_output *output)
  715. {
  716. struct edid *edid;
  717. if (!output->connector.edid_blob_ptr)
  718. return false;
  719. edid = (struct edid *)output->connector.edid_blob_ptr->data;
  720. return drm_detect_hdmi_monitor(edid);
  721. }
  722. static enum drm_connector_status
  723. tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
  724. {
  725. struct tegra_output *output = connector_to_output(connector);
  726. struct tegra_hdmi *hdmi = to_hdmi(output);
  727. enum drm_connector_status status;
  728. status = tegra_output_connector_detect(connector, force);
  729. if (status == connector_status_connected)
  730. return status;
  731. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
  732. return status;
  733. }
  734. #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
  735. static const struct debugfs_reg32 tegra_hdmi_regs[] = {
  736. DEBUGFS_REG32(HDMI_CTXSW),
  737. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
  738. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
  739. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
  740. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
  741. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
  742. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
  743. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
  744. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
  745. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
  746. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
  747. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
  748. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
  749. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
  750. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
  751. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
  752. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
  753. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
  754. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
  755. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
  756. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
  757. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
  758. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
  759. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
  760. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
  761. DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
  762. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
  763. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
  764. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
  765. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
  766. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
  767. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
  768. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
  769. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
  770. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
  771. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
  772. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
  773. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
  774. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
  775. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
  776. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
  777. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
  778. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
  779. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
  780. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
  781. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
  782. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
  783. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
  784. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
  785. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
  786. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
  787. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
  788. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
  789. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
  790. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
  791. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
  792. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
  793. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
  794. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
  795. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
  796. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
  797. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
  798. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
  799. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
  800. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
  801. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
  802. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
  803. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
  804. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
  805. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
  806. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
  807. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
  808. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
  809. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
  810. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
  811. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
  812. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
  813. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
  814. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
  815. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
  816. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
  817. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
  818. DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
  819. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
  820. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
  821. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
  822. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
  823. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
  824. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
  825. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
  826. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
  827. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
  828. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
  829. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
  830. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
  831. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
  832. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
  833. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
  834. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
  835. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
  836. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
  837. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
  838. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
  839. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
  840. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
  841. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
  842. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
  843. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
  844. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
  845. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
  846. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
  847. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
  848. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
  849. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
  850. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
  851. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
  852. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
  853. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
  854. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
  855. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
  856. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
  857. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
  858. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
  859. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
  860. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
  861. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
  862. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
  863. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
  864. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
  865. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
  866. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
  867. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
  868. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
  869. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
  870. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
  871. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
  872. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
  873. DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
  874. DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
  875. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
  876. DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
  877. DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
  878. DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
  879. DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
  880. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
  881. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
  882. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
  883. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
  884. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
  885. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
  886. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
  887. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
  888. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
  889. DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
  890. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
  891. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
  892. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
  893. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
  894. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
  895. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
  896. DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
  897. DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
  898. DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
  899. DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
  900. };
  901. static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
  902. {
  903. struct drm_info_node *node = s->private;
  904. struct tegra_hdmi *hdmi = node->info_ent->data;
  905. struct drm_crtc *crtc = hdmi->output.encoder.crtc;
  906. struct drm_device *drm = node->minor->dev;
  907. unsigned int i;
  908. int err = 0;
  909. drm_modeset_lock_all(drm);
  910. if (!crtc || !crtc->state->active) {
  911. err = -EBUSY;
  912. goto unlock;
  913. }
  914. for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
  915. unsigned int offset = tegra_hdmi_regs[i].offset;
  916. seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
  917. offset, tegra_hdmi_readl(hdmi, offset));
  918. }
  919. unlock:
  920. drm_modeset_unlock_all(drm);
  921. return err;
  922. }
  923. static struct drm_info_list debugfs_files[] = {
  924. { "regs", tegra_hdmi_show_regs, 0, NULL },
  925. };
  926. static int tegra_hdmi_late_register(struct drm_connector *connector)
  927. {
  928. struct tegra_output *output = connector_to_output(connector);
  929. unsigned int i, count = ARRAY_SIZE(debugfs_files);
  930. struct drm_minor *minor = connector->dev->primary;
  931. struct dentry *root = connector->debugfs_entry;
  932. struct tegra_hdmi *hdmi = to_hdmi(output);
  933. hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
  934. GFP_KERNEL);
  935. if (!hdmi->debugfs_files)
  936. return -ENOMEM;
  937. for (i = 0; i < count; i++)
  938. hdmi->debugfs_files[i].data = hdmi;
  939. drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
  940. return 0;
  941. }
  942. static void tegra_hdmi_early_unregister(struct drm_connector *connector)
  943. {
  944. struct tegra_output *output = connector_to_output(connector);
  945. struct drm_minor *minor = connector->dev->primary;
  946. unsigned int count = ARRAY_SIZE(debugfs_files);
  947. struct tegra_hdmi *hdmi = to_hdmi(output);
  948. drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
  949. kfree(hdmi->debugfs_files);
  950. hdmi->debugfs_files = NULL;
  951. }
  952. static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
  953. .reset = drm_atomic_helper_connector_reset,
  954. .detect = tegra_hdmi_connector_detect,
  955. .fill_modes = drm_helper_probe_single_connector_modes,
  956. .destroy = tegra_output_connector_destroy,
  957. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  958. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  959. .late_register = tegra_hdmi_late_register,
  960. .early_unregister = tegra_hdmi_early_unregister,
  961. };
  962. static enum drm_mode_status
  963. tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
  964. struct drm_display_mode *mode)
  965. {
  966. struct tegra_output *output = connector_to_output(connector);
  967. struct tegra_hdmi *hdmi = to_hdmi(output);
  968. unsigned long pclk = mode->clock * 1000;
  969. enum drm_mode_status status = MODE_OK;
  970. struct clk *parent;
  971. long err;
  972. parent = clk_get_parent(hdmi->clk_parent);
  973. err = clk_round_rate(parent, pclk * 4);
  974. if (err <= 0)
  975. status = MODE_NOCLOCK;
  976. return status;
  977. }
  978. static const struct drm_connector_helper_funcs
  979. tegra_hdmi_connector_helper_funcs = {
  980. .get_modes = tegra_output_connector_get_modes,
  981. .mode_valid = tegra_hdmi_connector_mode_valid,
  982. };
  983. static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
  984. {
  985. struct tegra_output *output = encoder_to_output(encoder);
  986. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  987. struct tegra_hdmi *hdmi = to_hdmi(output);
  988. u32 value;
  989. int err;
  990. /*
  991. * The following accesses registers of the display controller, so make
  992. * sure it's only executed when the output is attached to one.
  993. */
  994. if (dc) {
  995. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  996. value &= ~HDMI_ENABLE;
  997. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  998. tegra_dc_commit(dc);
  999. }
  1000. if (!hdmi->dvi) {
  1001. if (hdmi->stereo)
  1002. tegra_hdmi_disable_stereo_infoframe(hdmi);
  1003. tegra_hdmi_disable_audio_infoframe(hdmi);
  1004. tegra_hdmi_disable_avi_infoframe(hdmi);
  1005. tegra_hdmi_disable_audio(hdmi);
  1006. }
  1007. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
  1008. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
  1009. err = host1x_client_suspend(&hdmi->client);
  1010. if (err < 0)
  1011. dev_err(hdmi->dev, "failed to suspend: %d\n", err);
  1012. }
  1013. static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
  1014. {
  1015. struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
  1016. unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
  1017. struct tegra_output *output = encoder_to_output(encoder);
  1018. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  1019. struct tegra_hdmi *hdmi = to_hdmi(output);
  1020. unsigned int pulse_start, div82;
  1021. int retries = 1000;
  1022. u32 value;
  1023. int err;
  1024. err = host1x_client_resume(&hdmi->client);
  1025. if (err < 0) {
  1026. dev_err(hdmi->dev, "failed to resume: %d\n", err);
  1027. return;
  1028. }
  1029. /*
  1030. * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
  1031. * is used for interoperability between the HDA codec driver and the
  1032. * HDMI driver.
  1033. */
  1034. tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
  1035. tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
  1036. hdmi->pixel_clock = mode->clock * 1000;
  1037. h_sync_width = mode->hsync_end - mode->hsync_start;
  1038. h_back_porch = mode->htotal - mode->hsync_end;
  1039. h_front_porch = mode->hsync_start - mode->hdisplay;
  1040. err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
  1041. if (err < 0) {
  1042. dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
  1043. err);
  1044. }
  1045. DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
  1046. /* power up sequence */
  1047. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
  1048. value &= ~SOR_PLL_PDBG;
  1049. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
  1050. usleep_range(10, 20);
  1051. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
  1052. value &= ~SOR_PLL_PWR;
  1053. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
  1054. tegra_dc_writel(dc, VSYNC_H_POSITION(1),
  1055. DC_DISP_DISP_TIMING_OPTIONS);
  1056. tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
  1057. DC_DISP_DISP_COLOR_CONTROL);
  1058. /* video_preamble uses h_pulse2 */
  1059. pulse_start = 1 + h_sync_width + h_back_porch - 10;
  1060. tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
  1061. value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
  1062. PULSE_LAST_END_A;
  1063. tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
  1064. value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
  1065. tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
  1066. value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
  1067. VSYNC_WINDOW_ENABLE;
  1068. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
  1069. if (dc->pipe)
  1070. value = HDMI_SRC_DISPLAYB;
  1071. else
  1072. value = HDMI_SRC_DISPLAYA;
  1073. if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
  1074. (mode->vdisplay == 576)))
  1075. tegra_hdmi_writel(hdmi,
  1076. value | ARM_VIDEO_RANGE_FULL,
  1077. HDMI_NV_PDISP_INPUT_CONTROL);
  1078. else
  1079. tegra_hdmi_writel(hdmi,
  1080. value | ARM_VIDEO_RANGE_LIMITED,
  1081. HDMI_NV_PDISP_INPUT_CONTROL);
  1082. div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
  1083. value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
  1084. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
  1085. hdmi->dvi = !tegra_output_is_hdmi(output);
  1086. if (!hdmi->dvi) {
  1087. /*
  1088. * Make sure that the audio format has been configured before
  1089. * enabling audio, otherwise we may try to divide by zero.
  1090. */
  1091. if (hdmi->format.sample_rate > 0) {
  1092. err = tegra_hdmi_setup_audio(hdmi);
  1093. if (err < 0)
  1094. hdmi->dvi = true;
  1095. }
  1096. }
  1097. if (hdmi->config->has_hda)
  1098. tegra_hdmi_write_eld(hdmi);
  1099. rekey = HDMI_REKEY_DEFAULT;
  1100. value = HDMI_CTRL_REKEY(rekey);
  1101. value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
  1102. h_front_porch - rekey - 18) / 32);
  1103. if (!hdmi->dvi)
  1104. value |= HDMI_CTRL_ENABLE;
  1105. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
  1106. if (!hdmi->dvi) {
  1107. tegra_hdmi_setup_avi_infoframe(hdmi, mode);
  1108. tegra_hdmi_setup_audio_infoframe(hdmi);
  1109. if (hdmi->stereo)
  1110. tegra_hdmi_setup_stereo_infoframe(hdmi);
  1111. }
  1112. /* TMDS CONFIG */
  1113. for (i = 0; i < hdmi->config->num_tmds; i++) {
  1114. if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
  1115. tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
  1116. break;
  1117. }
  1118. }
  1119. tegra_hdmi_writel(hdmi,
  1120. SOR_SEQ_PU_PC(0) |
  1121. SOR_SEQ_PU_PC_ALT(0) |
  1122. SOR_SEQ_PD_PC(8) |
  1123. SOR_SEQ_PD_PC_ALT(8),
  1124. HDMI_NV_PDISP_SOR_SEQ_CTL);
  1125. value = SOR_SEQ_INST_WAIT_TIME(1) |
  1126. SOR_SEQ_INST_WAIT_UNITS_VSYNC |
  1127. SOR_SEQ_INST_HALT |
  1128. SOR_SEQ_INST_PIN_A_LOW |
  1129. SOR_SEQ_INST_PIN_B_LOW |
  1130. SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
  1131. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
  1132. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
  1133. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
  1134. value &= ~SOR_CSTM_ROTCLK(~0);
  1135. value |= SOR_CSTM_ROTCLK(2);
  1136. value |= SOR_CSTM_PLLDIV;
  1137. value &= ~SOR_CSTM_LVDS_ENABLE;
  1138. value &= ~SOR_CSTM_MODE_MASK;
  1139. value |= SOR_CSTM_MODE_TMDS;
  1140. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
  1141. /* start SOR */
  1142. tegra_hdmi_writel(hdmi,
  1143. SOR_PWR_NORMAL_STATE_PU |
  1144. SOR_PWR_NORMAL_START_NORMAL |
  1145. SOR_PWR_SAFE_STATE_PD |
  1146. SOR_PWR_SETTING_NEW_TRIGGER,
  1147. HDMI_NV_PDISP_SOR_PWR);
  1148. tegra_hdmi_writel(hdmi,
  1149. SOR_PWR_NORMAL_STATE_PU |
  1150. SOR_PWR_NORMAL_START_NORMAL |
  1151. SOR_PWR_SAFE_STATE_PD |
  1152. SOR_PWR_SETTING_NEW_DONE,
  1153. HDMI_NV_PDISP_SOR_PWR);
  1154. do {
  1155. BUG_ON(--retries < 0);
  1156. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
  1157. } while (value & SOR_PWR_SETTING_NEW_PENDING);
  1158. value = SOR_STATE_ASY_CRCMODE_COMPLETE |
  1159. SOR_STATE_ASY_OWNER_HEAD0 |
  1160. SOR_STATE_ASY_SUBOWNER_BOTH |
  1161. SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
  1162. SOR_STATE_ASY_DEPOL_POS;
  1163. /* setup sync polarities */
  1164. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  1165. value |= SOR_STATE_ASY_HSYNCPOL_POS;
  1166. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  1167. value |= SOR_STATE_ASY_HSYNCPOL_NEG;
  1168. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  1169. value |= SOR_STATE_ASY_VSYNCPOL_POS;
  1170. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  1171. value |= SOR_STATE_ASY_VSYNCPOL_NEG;
  1172. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
  1173. value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
  1174. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
  1175. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
  1176. tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
  1177. tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
  1178. HDMI_NV_PDISP_SOR_STATE1);
  1179. tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
  1180. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  1181. value |= HDMI_ENABLE;
  1182. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  1183. tegra_dc_commit(dc);
  1184. if (!hdmi->dvi) {
  1185. tegra_hdmi_enable_avi_infoframe(hdmi);
  1186. tegra_hdmi_enable_audio_infoframe(hdmi);
  1187. tegra_hdmi_enable_audio(hdmi);
  1188. if (hdmi->stereo)
  1189. tegra_hdmi_enable_stereo_infoframe(hdmi);
  1190. }
  1191. /* TODO: add HDCP support */
  1192. }
  1193. static int
  1194. tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
  1195. struct drm_crtc_state *crtc_state,
  1196. struct drm_connector_state *conn_state)
  1197. {
  1198. struct tegra_output *output = encoder_to_output(encoder);
  1199. struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
  1200. unsigned long pclk = crtc_state->mode.clock * 1000;
  1201. struct tegra_hdmi *hdmi = to_hdmi(output);
  1202. int err;
  1203. err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
  1204. pclk, 0);
  1205. if (err < 0) {
  1206. dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
  1207. return err;
  1208. }
  1209. return err;
  1210. }
  1211. static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
  1212. .disable = tegra_hdmi_encoder_disable,
  1213. .enable = tegra_hdmi_encoder_enable,
  1214. .atomic_check = tegra_hdmi_encoder_atomic_check,
  1215. };
  1216. static int tegra_hdmi_init(struct host1x_client *client)
  1217. {
  1218. struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
  1219. struct drm_device *drm = dev_get_drvdata(client->host);
  1220. int err;
  1221. hdmi->output.dev = client->dev;
  1222. drm_connector_init_with_ddc(drm, &hdmi->output.connector,
  1223. &tegra_hdmi_connector_funcs,
  1224. DRM_MODE_CONNECTOR_HDMIA,
  1225. hdmi->output.ddc);
  1226. drm_connector_helper_add(&hdmi->output.connector,
  1227. &tegra_hdmi_connector_helper_funcs);
  1228. hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
  1229. drm_simple_encoder_init(drm, &hdmi->output.encoder,
  1230. DRM_MODE_ENCODER_TMDS);
  1231. drm_encoder_helper_add(&hdmi->output.encoder,
  1232. &tegra_hdmi_encoder_helper_funcs);
  1233. drm_connector_attach_encoder(&hdmi->output.connector,
  1234. &hdmi->output.encoder);
  1235. drm_connector_register(&hdmi->output.connector);
  1236. err = tegra_output_init(drm, &hdmi->output);
  1237. if (err < 0) {
  1238. dev_err(client->dev, "failed to initialize output: %d\n", err);
  1239. return err;
  1240. }
  1241. hdmi->output.encoder.possible_crtcs = 0x3;
  1242. err = regulator_enable(hdmi->hdmi);
  1243. if (err < 0) {
  1244. dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
  1245. err);
  1246. return err;
  1247. }
  1248. err = regulator_enable(hdmi->pll);
  1249. if (err < 0) {
  1250. dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
  1251. return err;
  1252. }
  1253. err = regulator_enable(hdmi->vdd);
  1254. if (err < 0) {
  1255. dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
  1256. return err;
  1257. }
  1258. return 0;
  1259. }
  1260. static int tegra_hdmi_exit(struct host1x_client *client)
  1261. {
  1262. struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
  1263. tegra_output_exit(&hdmi->output);
  1264. regulator_disable(hdmi->vdd);
  1265. regulator_disable(hdmi->pll);
  1266. regulator_disable(hdmi->hdmi);
  1267. return 0;
  1268. }
  1269. static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
  1270. {
  1271. struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
  1272. struct device *dev = client->dev;
  1273. int err;
  1274. err = reset_control_assert(hdmi->rst);
  1275. if (err < 0) {
  1276. dev_err(dev, "failed to assert reset: %d\n", err);
  1277. return err;
  1278. }
  1279. usleep_range(1000, 2000);
  1280. clk_disable_unprepare(hdmi->clk);
  1281. pm_runtime_put_sync(dev);
  1282. return 0;
  1283. }
  1284. static int tegra_hdmi_runtime_resume(struct host1x_client *client)
  1285. {
  1286. struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
  1287. struct device *dev = client->dev;
  1288. int err;
  1289. err = pm_runtime_resume_and_get(dev);
  1290. if (err < 0) {
  1291. dev_err(dev, "failed to get runtime PM: %d\n", err);
  1292. return err;
  1293. }
  1294. err = clk_prepare_enable(hdmi->clk);
  1295. if (err < 0) {
  1296. dev_err(dev, "failed to enable clock: %d\n", err);
  1297. goto put_rpm;
  1298. }
  1299. usleep_range(1000, 2000);
  1300. err = reset_control_deassert(hdmi->rst);
  1301. if (err < 0) {
  1302. dev_err(dev, "failed to deassert reset: %d\n", err);
  1303. goto disable_clk;
  1304. }
  1305. return 0;
  1306. disable_clk:
  1307. clk_disable_unprepare(hdmi->clk);
  1308. put_rpm:
  1309. pm_runtime_put_sync(dev);
  1310. return err;
  1311. }
  1312. static const struct host1x_client_ops hdmi_client_ops = {
  1313. .init = tegra_hdmi_init,
  1314. .exit = tegra_hdmi_exit,
  1315. .suspend = tegra_hdmi_runtime_suspend,
  1316. .resume = tegra_hdmi_runtime_resume,
  1317. };
  1318. static const struct tegra_hdmi_config tegra20_hdmi_config = {
  1319. .tmds = tegra20_tmds_config,
  1320. .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
  1321. .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
  1322. .fuse_override_value = 1 << 31,
  1323. .has_sor_io_peak_current = false,
  1324. .has_hda = false,
  1325. .has_hbr = false,
  1326. };
  1327. static const struct tegra_hdmi_config tegra30_hdmi_config = {
  1328. .tmds = tegra30_tmds_config,
  1329. .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
  1330. .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
  1331. .fuse_override_value = 1 << 31,
  1332. .has_sor_io_peak_current = false,
  1333. .has_hda = true,
  1334. .has_hbr = false,
  1335. };
  1336. static const struct tegra_hdmi_config tegra114_hdmi_config = {
  1337. .tmds = tegra114_tmds_config,
  1338. .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
  1339. .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
  1340. .fuse_override_value = 1 << 31,
  1341. .has_sor_io_peak_current = true,
  1342. .has_hda = true,
  1343. .has_hbr = true,
  1344. };
  1345. static const struct tegra_hdmi_config tegra124_hdmi_config = {
  1346. .tmds = tegra124_tmds_config,
  1347. .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
  1348. .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
  1349. .fuse_override_value = 1 << 31,
  1350. .has_sor_io_peak_current = true,
  1351. .has_hda = true,
  1352. .has_hbr = true,
  1353. };
  1354. static const struct of_device_id tegra_hdmi_of_match[] = {
  1355. { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
  1356. { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
  1357. { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
  1358. { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
  1359. { },
  1360. };
  1361. MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
  1362. static irqreturn_t tegra_hdmi_irq(int irq, void *data)
  1363. {
  1364. struct tegra_hdmi *hdmi = data;
  1365. u32 value;
  1366. int err;
  1367. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
  1368. tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
  1369. if (value & INT_CODEC_SCRATCH0) {
  1370. unsigned int format;
  1371. u32 value;
  1372. value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
  1373. if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
  1374. format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
  1375. tegra_hda_parse_format(format, &hdmi->format);
  1376. err = tegra_hdmi_setup_audio(hdmi);
  1377. if (err < 0) {
  1378. tegra_hdmi_disable_audio_infoframe(hdmi);
  1379. tegra_hdmi_disable_audio(hdmi);
  1380. } else {
  1381. tegra_hdmi_setup_audio_infoframe(hdmi);
  1382. tegra_hdmi_enable_audio_infoframe(hdmi);
  1383. tegra_hdmi_enable_audio(hdmi);
  1384. }
  1385. } else {
  1386. tegra_hdmi_disable_audio_infoframe(hdmi);
  1387. tegra_hdmi_disable_audio(hdmi);
  1388. }
  1389. }
  1390. return IRQ_HANDLED;
  1391. }
  1392. static int tegra_hdmi_probe(struct platform_device *pdev)
  1393. {
  1394. const char *level = KERN_ERR;
  1395. struct tegra_hdmi *hdmi;
  1396. struct resource *regs;
  1397. int err;
  1398. hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
  1399. if (!hdmi)
  1400. return -ENOMEM;
  1401. hdmi->config = of_device_get_match_data(&pdev->dev);
  1402. hdmi->dev = &pdev->dev;
  1403. hdmi->audio_source = AUTO;
  1404. hdmi->stereo = false;
  1405. hdmi->dvi = false;
  1406. hdmi->clk = devm_clk_get(&pdev->dev, NULL);
  1407. if (IS_ERR(hdmi->clk)) {
  1408. dev_err(&pdev->dev, "failed to get clock\n");
  1409. return PTR_ERR(hdmi->clk);
  1410. }
  1411. hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
  1412. if (IS_ERR(hdmi->rst)) {
  1413. dev_err(&pdev->dev, "failed to get reset\n");
  1414. return PTR_ERR(hdmi->rst);
  1415. }
  1416. hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
  1417. if (IS_ERR(hdmi->clk_parent))
  1418. return PTR_ERR(hdmi->clk_parent);
  1419. err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
  1420. if (err < 0) {
  1421. dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
  1422. return err;
  1423. }
  1424. hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
  1425. err = PTR_ERR_OR_ZERO(hdmi->hdmi);
  1426. if (err) {
  1427. if (err == -EPROBE_DEFER)
  1428. level = KERN_DEBUG;
  1429. dev_printk(level, &pdev->dev,
  1430. "failed to get HDMI regulator: %d\n", err);
  1431. return err;
  1432. }
  1433. hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
  1434. err = PTR_ERR_OR_ZERO(hdmi->pll);
  1435. if (err) {
  1436. if (err == -EPROBE_DEFER)
  1437. level = KERN_DEBUG;
  1438. dev_printk(level, &pdev->dev,
  1439. "failed to get PLL regulator: %d\n", err);
  1440. return err;
  1441. }
  1442. hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
  1443. err = PTR_ERR_OR_ZERO(hdmi->vdd);
  1444. if (err) {
  1445. if (err == -EPROBE_DEFER)
  1446. level = KERN_DEBUG;
  1447. dev_printk(level, &pdev->dev,
  1448. "failed to get VDD regulator: %d\n", err);
  1449. return err;
  1450. }
  1451. hdmi->output.dev = &pdev->dev;
  1452. err = tegra_output_probe(&hdmi->output);
  1453. if (err < 0)
  1454. return err;
  1455. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1456. hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
  1457. if (IS_ERR(hdmi->regs))
  1458. return PTR_ERR(hdmi->regs);
  1459. err = platform_get_irq(pdev, 0);
  1460. if (err < 0)
  1461. return err;
  1462. hdmi->irq = err;
  1463. err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
  1464. dev_name(hdmi->dev), hdmi);
  1465. if (err < 0) {
  1466. dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
  1467. hdmi->irq, err);
  1468. return err;
  1469. }
  1470. platform_set_drvdata(pdev, hdmi);
  1471. pm_runtime_enable(&pdev->dev);
  1472. INIT_LIST_HEAD(&hdmi->client.list);
  1473. hdmi->client.ops = &hdmi_client_ops;
  1474. hdmi->client.dev = &pdev->dev;
  1475. err = host1x_client_register(&hdmi->client);
  1476. if (err < 0) {
  1477. dev_err(&pdev->dev, "failed to register host1x client: %d\n",
  1478. err);
  1479. return err;
  1480. }
  1481. return 0;
  1482. }
  1483. static int tegra_hdmi_remove(struct platform_device *pdev)
  1484. {
  1485. struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
  1486. int err;
  1487. pm_runtime_disable(&pdev->dev);
  1488. err = host1x_client_unregister(&hdmi->client);
  1489. if (err < 0) {
  1490. dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
  1491. err);
  1492. return err;
  1493. }
  1494. tegra_output_remove(&hdmi->output);
  1495. return 0;
  1496. }
  1497. struct platform_driver tegra_hdmi_driver = {
  1498. .driver = {
  1499. .name = "tegra-hdmi",
  1500. .of_match_table = tegra_hdmi_of_match,
  1501. },
  1502. .probe = tegra_hdmi_probe,
  1503. .remove = tegra_hdmi_remove,
  1504. };