dsi.c 42 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 NVIDIA Corporation
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/debugfs.h>
  7. #include <linux/delay.h>
  8. #include <linux/host1x.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/reset.h>
  16. #include <video/mipi_display.h>
  17. #include <drm/drm_atomic_helper.h>
  18. #include <drm/drm_debugfs.h>
  19. #include <drm/drm_file.h>
  20. #include <drm/drm_mipi_dsi.h>
  21. #include <drm/drm_panel.h>
  22. #include <drm/drm_simple_kms_helper.h>
  23. #include "dc.h"
  24. #include "drm.h"
  25. #include "dsi.h"
  26. #include "mipi-phy.h"
  27. #include "trace.h"
  28. struct tegra_dsi_state {
  29. struct drm_connector_state base;
  30. struct mipi_dphy_timing timing;
  31. unsigned long period;
  32. unsigned int vrefresh;
  33. unsigned int lanes;
  34. unsigned long pclk;
  35. unsigned long bclk;
  36. enum tegra_dsi_format format;
  37. unsigned int mul;
  38. unsigned int div;
  39. };
  40. static inline struct tegra_dsi_state *
  41. to_dsi_state(struct drm_connector_state *state)
  42. {
  43. return container_of(state, struct tegra_dsi_state, base);
  44. }
  45. struct tegra_dsi {
  46. struct host1x_client client;
  47. struct tegra_output output;
  48. struct device *dev;
  49. void __iomem *regs;
  50. struct reset_control *rst;
  51. struct clk *clk_parent;
  52. struct clk *clk_lp;
  53. struct clk *clk;
  54. struct drm_info_list *debugfs_files;
  55. unsigned long flags;
  56. enum mipi_dsi_pixel_format format;
  57. unsigned int lanes;
  58. struct tegra_mipi_device *mipi;
  59. struct mipi_dsi_host host;
  60. struct regulator *vdd;
  61. unsigned int video_fifo_depth;
  62. unsigned int host_fifo_depth;
  63. /* for ganged-mode support */
  64. struct tegra_dsi *master;
  65. struct tegra_dsi *slave;
  66. };
  67. static inline struct tegra_dsi *
  68. host1x_client_to_dsi(struct host1x_client *client)
  69. {
  70. return container_of(client, struct tegra_dsi, client);
  71. }
  72. static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
  73. {
  74. return container_of(host, struct tegra_dsi, host);
  75. }
  76. static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
  77. {
  78. return container_of(output, struct tegra_dsi, output);
  79. }
  80. static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
  81. {
  82. return to_dsi_state(dsi->output.connector.state);
  83. }
  84. static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
  85. {
  86. u32 value = readl(dsi->regs + (offset << 2));
  87. trace_dsi_readl(dsi->dev, offset, value);
  88. return value;
  89. }
  90. static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
  91. unsigned int offset)
  92. {
  93. trace_dsi_writel(dsi->dev, offset, value);
  94. writel(value, dsi->regs + (offset << 2));
  95. }
  96. #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
  97. static const struct debugfs_reg32 tegra_dsi_regs[] = {
  98. DEBUGFS_REG32(DSI_INCR_SYNCPT),
  99. DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
  100. DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
  101. DEBUGFS_REG32(DSI_CTXSW),
  102. DEBUGFS_REG32(DSI_RD_DATA),
  103. DEBUGFS_REG32(DSI_WR_DATA),
  104. DEBUGFS_REG32(DSI_POWER_CONTROL),
  105. DEBUGFS_REG32(DSI_INT_ENABLE),
  106. DEBUGFS_REG32(DSI_INT_STATUS),
  107. DEBUGFS_REG32(DSI_INT_MASK),
  108. DEBUGFS_REG32(DSI_HOST_CONTROL),
  109. DEBUGFS_REG32(DSI_CONTROL),
  110. DEBUGFS_REG32(DSI_SOL_DELAY),
  111. DEBUGFS_REG32(DSI_MAX_THRESHOLD),
  112. DEBUGFS_REG32(DSI_TRIGGER),
  113. DEBUGFS_REG32(DSI_TX_CRC),
  114. DEBUGFS_REG32(DSI_STATUS),
  115. DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
  116. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
  117. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
  118. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
  119. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
  120. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
  121. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
  122. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
  123. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
  124. DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
  125. DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
  126. DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
  127. DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
  128. DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
  129. DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
  130. DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
  131. DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
  132. DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
  133. DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
  134. DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
  135. DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
  136. DEBUGFS_REG32(DSI_DCS_CMDS),
  137. DEBUGFS_REG32(DSI_PKT_LEN_0_1),
  138. DEBUGFS_REG32(DSI_PKT_LEN_2_3),
  139. DEBUGFS_REG32(DSI_PKT_LEN_4_5),
  140. DEBUGFS_REG32(DSI_PKT_LEN_6_7),
  141. DEBUGFS_REG32(DSI_PHY_TIMING_0),
  142. DEBUGFS_REG32(DSI_PHY_TIMING_1),
  143. DEBUGFS_REG32(DSI_PHY_TIMING_2),
  144. DEBUGFS_REG32(DSI_BTA_TIMING),
  145. DEBUGFS_REG32(DSI_TIMEOUT_0),
  146. DEBUGFS_REG32(DSI_TIMEOUT_1),
  147. DEBUGFS_REG32(DSI_TO_TALLY),
  148. DEBUGFS_REG32(DSI_PAD_CONTROL_0),
  149. DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
  150. DEBUGFS_REG32(DSI_PAD_CD_STATUS),
  151. DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
  152. DEBUGFS_REG32(DSI_PAD_CONTROL_1),
  153. DEBUGFS_REG32(DSI_PAD_CONTROL_2),
  154. DEBUGFS_REG32(DSI_PAD_CONTROL_3),
  155. DEBUGFS_REG32(DSI_PAD_CONTROL_4),
  156. DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
  157. DEBUGFS_REG32(DSI_GANGED_MODE_START),
  158. DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
  159. DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
  160. DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
  161. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
  162. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
  163. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
  164. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
  165. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
  166. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
  167. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
  168. DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
  169. };
  170. static int tegra_dsi_show_regs(struct seq_file *s, void *data)
  171. {
  172. struct drm_info_node *node = s->private;
  173. struct tegra_dsi *dsi = node->info_ent->data;
  174. struct drm_crtc *crtc = dsi->output.encoder.crtc;
  175. struct drm_device *drm = node->minor->dev;
  176. unsigned int i;
  177. int err = 0;
  178. drm_modeset_lock_all(drm);
  179. if (!crtc || !crtc->state->active) {
  180. err = -EBUSY;
  181. goto unlock;
  182. }
  183. for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
  184. unsigned int offset = tegra_dsi_regs[i].offset;
  185. seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
  186. offset, tegra_dsi_readl(dsi, offset));
  187. }
  188. unlock:
  189. drm_modeset_unlock_all(drm);
  190. return err;
  191. }
  192. static struct drm_info_list debugfs_files[] = {
  193. { "regs", tegra_dsi_show_regs, 0, NULL },
  194. };
  195. static int tegra_dsi_late_register(struct drm_connector *connector)
  196. {
  197. struct tegra_output *output = connector_to_output(connector);
  198. unsigned int i, count = ARRAY_SIZE(debugfs_files);
  199. struct drm_minor *minor = connector->dev->primary;
  200. struct dentry *root = connector->debugfs_entry;
  201. struct tegra_dsi *dsi = to_dsi(output);
  202. dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
  203. GFP_KERNEL);
  204. if (!dsi->debugfs_files)
  205. return -ENOMEM;
  206. for (i = 0; i < count; i++)
  207. dsi->debugfs_files[i].data = dsi;
  208. drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
  209. return 0;
  210. }
  211. static void tegra_dsi_early_unregister(struct drm_connector *connector)
  212. {
  213. struct tegra_output *output = connector_to_output(connector);
  214. unsigned int count = ARRAY_SIZE(debugfs_files);
  215. struct tegra_dsi *dsi = to_dsi(output);
  216. drm_debugfs_remove_files(dsi->debugfs_files, count,
  217. connector->dev->primary);
  218. kfree(dsi->debugfs_files);
  219. dsi->debugfs_files = NULL;
  220. }
  221. #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
  222. #define PKT_LEN0(len) (((len) & 0x07) << 0)
  223. #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
  224. #define PKT_LEN1(len) (((len) & 0x07) << 10)
  225. #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
  226. #define PKT_LEN2(len) (((len) & 0x07) << 20)
  227. #define PKT_LP (1 << 30)
  228. #define NUM_PKT_SEQ 12
  229. /*
  230. * non-burst mode with sync pulses
  231. */
  232. static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
  233. [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
  234. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  235. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  236. PKT_LP,
  237. [ 1] = 0,
  238. [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
  239. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  240. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  241. PKT_LP,
  242. [ 3] = 0,
  243. [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  244. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  245. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  246. PKT_LP,
  247. [ 5] = 0,
  248. [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  249. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  250. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
  251. [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
  252. PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
  253. PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
  254. [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  255. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  256. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
  257. PKT_LP,
  258. [ 9] = 0,
  259. [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  260. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
  261. PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
  262. [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
  263. PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
  264. PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
  265. };
  266. /*
  267. * non-burst mode with sync events
  268. */
  269. static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
  270. [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
  271. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  272. PKT_LP,
  273. [ 1] = 0,
  274. [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  275. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  276. PKT_LP,
  277. [ 3] = 0,
  278. [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  279. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  280. PKT_LP,
  281. [ 5] = 0,
  282. [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  283. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
  284. PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
  285. [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
  286. [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  287. PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
  288. PKT_LP,
  289. [ 9] = 0,
  290. [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
  291. PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
  292. PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
  293. [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
  294. };
  295. static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
  296. [ 0] = 0,
  297. [ 1] = 0,
  298. [ 2] = 0,
  299. [ 3] = 0,
  300. [ 4] = 0,
  301. [ 5] = 0,
  302. [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
  303. [ 7] = 0,
  304. [ 8] = 0,
  305. [ 9] = 0,
  306. [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
  307. [11] = 0,
  308. };
  309. static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
  310. unsigned long period,
  311. const struct mipi_dphy_timing *timing)
  312. {
  313. u32 value;
  314. value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
  315. DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
  316. DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
  317. DSI_TIMING_FIELD(timing->hsprepare, period, 1);
  318. tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
  319. value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
  320. DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
  321. DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
  322. DSI_TIMING_FIELD(timing->lpx, period, 1);
  323. tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
  324. value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
  325. DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
  326. DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
  327. tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
  328. value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
  329. DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
  330. DSI_TIMING_FIELD(timing->tago, period, 1);
  331. tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
  332. if (dsi->slave)
  333. tegra_dsi_set_phy_timing(dsi->slave, period, timing);
  334. }
  335. static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
  336. unsigned int *mulp, unsigned int *divp)
  337. {
  338. switch (format) {
  339. case MIPI_DSI_FMT_RGB666_PACKED:
  340. case MIPI_DSI_FMT_RGB888:
  341. *mulp = 3;
  342. *divp = 1;
  343. break;
  344. case MIPI_DSI_FMT_RGB565:
  345. *mulp = 2;
  346. *divp = 1;
  347. break;
  348. case MIPI_DSI_FMT_RGB666:
  349. *mulp = 9;
  350. *divp = 4;
  351. break;
  352. default:
  353. return -EINVAL;
  354. }
  355. return 0;
  356. }
  357. static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
  358. enum tegra_dsi_format *fmt)
  359. {
  360. switch (format) {
  361. case MIPI_DSI_FMT_RGB888:
  362. *fmt = TEGRA_DSI_FORMAT_24P;
  363. break;
  364. case MIPI_DSI_FMT_RGB666:
  365. *fmt = TEGRA_DSI_FORMAT_18NP;
  366. break;
  367. case MIPI_DSI_FMT_RGB666_PACKED:
  368. *fmt = TEGRA_DSI_FORMAT_18P;
  369. break;
  370. case MIPI_DSI_FMT_RGB565:
  371. *fmt = TEGRA_DSI_FORMAT_16P;
  372. break;
  373. default:
  374. return -EINVAL;
  375. }
  376. return 0;
  377. }
  378. static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
  379. unsigned int size)
  380. {
  381. u32 value;
  382. tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
  383. tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
  384. value = DSI_GANGED_MODE_CONTROL_ENABLE;
  385. tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
  386. }
  387. static void tegra_dsi_enable(struct tegra_dsi *dsi)
  388. {
  389. u32 value;
  390. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  391. value |= DSI_POWER_CONTROL_ENABLE;
  392. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  393. if (dsi->slave)
  394. tegra_dsi_enable(dsi->slave);
  395. }
  396. static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
  397. {
  398. if (dsi->master)
  399. return dsi->master->lanes + dsi->lanes;
  400. if (dsi->slave)
  401. return dsi->lanes + dsi->slave->lanes;
  402. return dsi->lanes;
  403. }
  404. static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
  405. const struct drm_display_mode *mode)
  406. {
  407. unsigned int hact, hsw, hbp, hfp, i, mul, div;
  408. struct tegra_dsi_state *state;
  409. const u32 *pkt_seq;
  410. u32 value;
  411. /* XXX: pass in state into this function? */
  412. if (dsi->master)
  413. state = tegra_dsi_get_state(dsi->master);
  414. else
  415. state = tegra_dsi_get_state(dsi);
  416. mul = state->mul;
  417. div = state->div;
  418. if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
  419. DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
  420. pkt_seq = pkt_seq_video_non_burst_sync_pulses;
  421. } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
  422. DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
  423. pkt_seq = pkt_seq_video_non_burst_sync_events;
  424. } else {
  425. DRM_DEBUG_KMS("Command mode\n");
  426. pkt_seq = pkt_seq_command_mode;
  427. }
  428. value = DSI_CONTROL_CHANNEL(0) |
  429. DSI_CONTROL_FORMAT(state->format) |
  430. DSI_CONTROL_LANES(dsi->lanes - 1) |
  431. DSI_CONTROL_SOURCE(pipe);
  432. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  433. tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
  434. value = DSI_HOST_CONTROL_HS;
  435. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  436. value = tegra_dsi_readl(dsi, DSI_CONTROL);
  437. if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
  438. value |= DSI_CONTROL_HS_CLK_CTRL;
  439. value &= ~DSI_CONTROL_TX_TRIG(3);
  440. /* enable DCS commands for command mode */
  441. if (dsi->flags & MIPI_DSI_MODE_VIDEO)
  442. value &= ~DSI_CONTROL_DCS_ENABLE;
  443. else
  444. value |= DSI_CONTROL_DCS_ENABLE;
  445. value |= DSI_CONTROL_VIDEO_ENABLE;
  446. value &= ~DSI_CONTROL_HOST_ENABLE;
  447. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  448. for (i = 0; i < NUM_PKT_SEQ; i++)
  449. tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
  450. if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
  451. /* horizontal active pixels */
  452. hact = mode->hdisplay * mul / div;
  453. /* horizontal sync width */
  454. hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
  455. /* horizontal back porch */
  456. hbp = (mode->htotal - mode->hsync_end) * mul / div;
  457. if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
  458. hbp += hsw;
  459. /* horizontal front porch */
  460. hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
  461. /* subtract packet overhead */
  462. hsw -= 10;
  463. hbp -= 14;
  464. hfp -= 8;
  465. tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
  466. tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
  467. tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
  468. tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
  469. /* set SOL delay (for non-burst mode only) */
  470. tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
  471. /* TODO: implement ganged mode */
  472. } else {
  473. u16 bytes;
  474. if (dsi->master || dsi->slave) {
  475. /*
  476. * For ganged mode, assume symmetric left-right mode.
  477. */
  478. bytes = 1 + (mode->hdisplay / 2) * mul / div;
  479. } else {
  480. /* 1 byte (DCS command) + pixel data */
  481. bytes = 1 + mode->hdisplay * mul / div;
  482. }
  483. tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
  484. tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
  485. tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
  486. tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
  487. value = MIPI_DCS_WRITE_MEMORY_START << 8 |
  488. MIPI_DCS_WRITE_MEMORY_CONTINUE;
  489. tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
  490. /* set SOL delay */
  491. if (dsi->master || dsi->slave) {
  492. unsigned long delay, bclk, bclk_ganged;
  493. unsigned int lanes = state->lanes;
  494. /* SOL to valid, valid to FIFO and FIFO write delay */
  495. delay = 4 + 4 + 2;
  496. delay = DIV_ROUND_UP(delay * mul, div * lanes);
  497. /* FIFO read delay */
  498. delay = delay + 6;
  499. bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
  500. bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
  501. value = bclk - bclk_ganged + delay + 20;
  502. } else {
  503. /* TODO: revisit for non-ganged mode */
  504. value = 8 * mul / div;
  505. }
  506. tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
  507. }
  508. if (dsi->slave) {
  509. tegra_dsi_configure(dsi->slave, pipe, mode);
  510. /*
  511. * TODO: Support modes other than symmetrical left-right
  512. * split.
  513. */
  514. tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
  515. tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
  516. mode->hdisplay / 2);
  517. }
  518. }
  519. static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
  520. {
  521. u32 value;
  522. timeout = jiffies + msecs_to_jiffies(timeout);
  523. while (time_before(jiffies, timeout)) {
  524. value = tegra_dsi_readl(dsi, DSI_STATUS);
  525. if (value & DSI_STATUS_IDLE)
  526. return 0;
  527. usleep_range(1000, 2000);
  528. }
  529. return -ETIMEDOUT;
  530. }
  531. static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
  532. {
  533. u32 value;
  534. value = tegra_dsi_readl(dsi, DSI_CONTROL);
  535. value &= ~DSI_CONTROL_VIDEO_ENABLE;
  536. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  537. if (dsi->slave)
  538. tegra_dsi_video_disable(dsi->slave);
  539. }
  540. static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
  541. {
  542. tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
  543. tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
  544. tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
  545. }
  546. static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
  547. {
  548. u32 value;
  549. value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
  550. tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
  551. return 0;
  552. }
  553. static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
  554. {
  555. u32 value;
  556. int err;
  557. /*
  558. * XXX Is this still needed? The module reset is deasserted right
  559. * before this function is called.
  560. */
  561. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
  562. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
  563. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
  564. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
  565. tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
  566. /* start calibration */
  567. tegra_dsi_pad_enable(dsi);
  568. value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
  569. DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
  570. DSI_PAD_OUT_CLK(0x0);
  571. tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
  572. value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
  573. DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
  574. tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
  575. err = tegra_mipi_start_calibration(dsi->mipi);
  576. if (err < 0)
  577. return err;
  578. return tegra_mipi_finish_calibration(dsi->mipi);
  579. }
  580. static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
  581. unsigned int vrefresh)
  582. {
  583. unsigned int timeout;
  584. u32 value;
  585. /* one frame high-speed transmission timeout */
  586. timeout = (bclk / vrefresh) / 512;
  587. value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
  588. tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
  589. /* 2 ms peripheral timeout for panel */
  590. timeout = 2 * bclk / 512 * 1000;
  591. value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
  592. tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
  593. value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
  594. tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
  595. if (dsi->slave)
  596. tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
  597. }
  598. static void tegra_dsi_disable(struct tegra_dsi *dsi)
  599. {
  600. u32 value;
  601. if (dsi->slave) {
  602. tegra_dsi_ganged_disable(dsi->slave);
  603. tegra_dsi_ganged_disable(dsi);
  604. }
  605. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  606. value &= ~DSI_POWER_CONTROL_ENABLE;
  607. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  608. if (dsi->slave)
  609. tegra_dsi_disable(dsi->slave);
  610. usleep_range(5000, 10000);
  611. }
  612. static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
  613. {
  614. u32 value;
  615. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  616. value &= ~DSI_POWER_CONTROL_ENABLE;
  617. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  618. usleep_range(300, 1000);
  619. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  620. value |= DSI_POWER_CONTROL_ENABLE;
  621. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  622. usleep_range(300, 1000);
  623. value = tegra_dsi_readl(dsi, DSI_TRIGGER);
  624. if (value)
  625. tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
  626. if (dsi->slave)
  627. tegra_dsi_soft_reset(dsi->slave);
  628. }
  629. static void tegra_dsi_connector_reset(struct drm_connector *connector)
  630. {
  631. struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
  632. if (!state)
  633. return;
  634. if (connector->state) {
  635. __drm_atomic_helper_connector_destroy_state(connector->state);
  636. kfree(connector->state);
  637. }
  638. __drm_atomic_helper_connector_reset(connector, &state->base);
  639. }
  640. static struct drm_connector_state *
  641. tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
  642. {
  643. struct tegra_dsi_state *state = to_dsi_state(connector->state);
  644. struct tegra_dsi_state *copy;
  645. copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
  646. if (!copy)
  647. return NULL;
  648. __drm_atomic_helper_connector_duplicate_state(connector,
  649. &copy->base);
  650. return &copy->base;
  651. }
  652. static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
  653. .reset = tegra_dsi_connector_reset,
  654. .detect = tegra_output_connector_detect,
  655. .fill_modes = drm_helper_probe_single_connector_modes,
  656. .destroy = tegra_output_connector_destroy,
  657. .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
  658. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  659. .late_register = tegra_dsi_late_register,
  660. .early_unregister = tegra_dsi_early_unregister,
  661. };
  662. static enum drm_mode_status
  663. tegra_dsi_connector_mode_valid(struct drm_connector *connector,
  664. struct drm_display_mode *mode)
  665. {
  666. return MODE_OK;
  667. }
  668. static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
  669. .get_modes = tegra_output_connector_get_modes,
  670. .mode_valid = tegra_dsi_connector_mode_valid,
  671. };
  672. static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
  673. {
  674. int err;
  675. if (dsi->slave)
  676. tegra_dsi_unprepare(dsi->slave);
  677. err = tegra_mipi_disable(dsi->mipi);
  678. if (err < 0)
  679. dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
  680. err);
  681. err = host1x_client_suspend(&dsi->client);
  682. if (err < 0)
  683. dev_err(dsi->dev, "failed to suspend: %d\n", err);
  684. }
  685. static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
  686. {
  687. struct tegra_output *output = encoder_to_output(encoder);
  688. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  689. struct tegra_dsi *dsi = to_dsi(output);
  690. u32 value;
  691. int err;
  692. if (output->panel)
  693. drm_panel_disable(output->panel);
  694. tegra_dsi_video_disable(dsi);
  695. /*
  696. * The following accesses registers of the display controller, so make
  697. * sure it's only executed when the output is attached to one.
  698. */
  699. if (dc) {
  700. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  701. value &= ~DSI_ENABLE;
  702. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  703. tegra_dc_commit(dc);
  704. }
  705. err = tegra_dsi_wait_idle(dsi, 100);
  706. if (err < 0)
  707. dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
  708. tegra_dsi_soft_reset(dsi);
  709. if (output->panel)
  710. drm_panel_unprepare(output->panel);
  711. tegra_dsi_disable(dsi);
  712. tegra_dsi_unprepare(dsi);
  713. }
  714. static int tegra_dsi_prepare(struct tegra_dsi *dsi)
  715. {
  716. int err;
  717. err = host1x_client_resume(&dsi->client);
  718. if (err < 0) {
  719. dev_err(dsi->dev, "failed to resume: %d\n", err);
  720. return err;
  721. }
  722. err = tegra_mipi_enable(dsi->mipi);
  723. if (err < 0)
  724. dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
  725. err);
  726. err = tegra_dsi_pad_calibrate(dsi);
  727. if (err < 0)
  728. dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
  729. if (dsi->slave)
  730. tegra_dsi_prepare(dsi->slave);
  731. return 0;
  732. }
  733. static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
  734. {
  735. struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
  736. struct tegra_output *output = encoder_to_output(encoder);
  737. struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
  738. struct tegra_dsi *dsi = to_dsi(output);
  739. struct tegra_dsi_state *state;
  740. u32 value;
  741. int err;
  742. err = tegra_dsi_prepare(dsi);
  743. if (err < 0) {
  744. dev_err(dsi->dev, "failed to prepare: %d\n", err);
  745. return;
  746. }
  747. state = tegra_dsi_get_state(dsi);
  748. tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
  749. /*
  750. * The D-PHY timing fields are expressed in byte-clock cycles, so
  751. * multiply the period by 8.
  752. */
  753. tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
  754. if (output->panel)
  755. drm_panel_prepare(output->panel);
  756. tegra_dsi_configure(dsi, dc->pipe, mode);
  757. /* enable display controller */
  758. value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
  759. value |= DSI_ENABLE;
  760. tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
  761. tegra_dc_commit(dc);
  762. /* enable DSI controller */
  763. tegra_dsi_enable(dsi);
  764. if (output->panel)
  765. drm_panel_enable(output->panel);
  766. }
  767. static int
  768. tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
  769. struct drm_crtc_state *crtc_state,
  770. struct drm_connector_state *conn_state)
  771. {
  772. struct tegra_output *output = encoder_to_output(encoder);
  773. struct tegra_dsi_state *state = to_dsi_state(conn_state);
  774. struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
  775. struct tegra_dsi *dsi = to_dsi(output);
  776. unsigned int scdiv;
  777. unsigned long plld;
  778. int err;
  779. state->pclk = crtc_state->mode.clock * 1000;
  780. err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
  781. if (err < 0)
  782. return err;
  783. state->lanes = tegra_dsi_get_lanes(dsi);
  784. err = tegra_dsi_get_format(dsi->format, &state->format);
  785. if (err < 0)
  786. return err;
  787. state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
  788. /* compute byte clock */
  789. state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
  790. DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
  791. state->lanes);
  792. DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
  793. state->vrefresh);
  794. DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
  795. /*
  796. * Compute bit clock and round up to the next MHz.
  797. */
  798. plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
  799. state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
  800. err = mipi_dphy_timing_get_default(&state->timing, state->period);
  801. if (err < 0)
  802. return err;
  803. err = mipi_dphy_timing_validate(&state->timing, state->period);
  804. if (err < 0) {
  805. dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
  806. return err;
  807. }
  808. /*
  809. * We divide the frequency by two here, but we make up for that by
  810. * setting the shift clock divider (further below) to half of the
  811. * correct value.
  812. */
  813. plld /= 2;
  814. /*
  815. * Derive pixel clock from bit clock using the shift clock divider.
  816. * Note that this is only half of what we would expect, but we need
  817. * that to make up for the fact that we divided the bit clock by a
  818. * factor of two above.
  819. *
  820. * It's not clear exactly why this is necessary, but the display is
  821. * not working properly otherwise. Perhaps the PLLs cannot generate
  822. * frequencies sufficiently high.
  823. */
  824. scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
  825. err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
  826. plld, scdiv);
  827. if (err < 0) {
  828. dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
  829. return err;
  830. }
  831. return err;
  832. }
  833. static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
  834. .disable = tegra_dsi_encoder_disable,
  835. .enable = tegra_dsi_encoder_enable,
  836. .atomic_check = tegra_dsi_encoder_atomic_check,
  837. };
  838. static int tegra_dsi_init(struct host1x_client *client)
  839. {
  840. struct drm_device *drm = dev_get_drvdata(client->host);
  841. struct tegra_dsi *dsi = host1x_client_to_dsi(client);
  842. int err;
  843. /* Gangsters must not register their own outputs. */
  844. if (!dsi->master) {
  845. dsi->output.dev = client->dev;
  846. drm_connector_init(drm, &dsi->output.connector,
  847. &tegra_dsi_connector_funcs,
  848. DRM_MODE_CONNECTOR_DSI);
  849. drm_connector_helper_add(&dsi->output.connector,
  850. &tegra_dsi_connector_helper_funcs);
  851. dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
  852. drm_simple_encoder_init(drm, &dsi->output.encoder,
  853. DRM_MODE_ENCODER_DSI);
  854. drm_encoder_helper_add(&dsi->output.encoder,
  855. &tegra_dsi_encoder_helper_funcs);
  856. drm_connector_attach_encoder(&dsi->output.connector,
  857. &dsi->output.encoder);
  858. drm_connector_register(&dsi->output.connector);
  859. err = tegra_output_init(drm, &dsi->output);
  860. if (err < 0)
  861. dev_err(dsi->dev, "failed to initialize output: %d\n",
  862. err);
  863. dsi->output.encoder.possible_crtcs = 0x3;
  864. }
  865. return 0;
  866. }
  867. static int tegra_dsi_exit(struct host1x_client *client)
  868. {
  869. struct tegra_dsi *dsi = host1x_client_to_dsi(client);
  870. tegra_output_exit(&dsi->output);
  871. return 0;
  872. }
  873. static int tegra_dsi_runtime_suspend(struct host1x_client *client)
  874. {
  875. struct tegra_dsi *dsi = host1x_client_to_dsi(client);
  876. struct device *dev = client->dev;
  877. int err;
  878. if (dsi->rst) {
  879. err = reset_control_assert(dsi->rst);
  880. if (err < 0) {
  881. dev_err(dev, "failed to assert reset: %d\n", err);
  882. return err;
  883. }
  884. }
  885. usleep_range(1000, 2000);
  886. clk_disable_unprepare(dsi->clk_lp);
  887. clk_disable_unprepare(dsi->clk);
  888. regulator_disable(dsi->vdd);
  889. pm_runtime_put_sync(dev);
  890. return 0;
  891. }
  892. static int tegra_dsi_runtime_resume(struct host1x_client *client)
  893. {
  894. struct tegra_dsi *dsi = host1x_client_to_dsi(client);
  895. struct device *dev = client->dev;
  896. int err;
  897. err = pm_runtime_resume_and_get(dev);
  898. if (err < 0) {
  899. dev_err(dev, "failed to get runtime PM: %d\n", err);
  900. return err;
  901. }
  902. err = regulator_enable(dsi->vdd);
  903. if (err < 0) {
  904. dev_err(dev, "failed to enable VDD supply: %d\n", err);
  905. goto put_rpm;
  906. }
  907. err = clk_prepare_enable(dsi->clk);
  908. if (err < 0) {
  909. dev_err(dev, "cannot enable DSI clock: %d\n", err);
  910. goto disable_vdd;
  911. }
  912. err = clk_prepare_enable(dsi->clk_lp);
  913. if (err < 0) {
  914. dev_err(dev, "cannot enable low-power clock: %d\n", err);
  915. goto disable_clk;
  916. }
  917. usleep_range(1000, 2000);
  918. if (dsi->rst) {
  919. err = reset_control_deassert(dsi->rst);
  920. if (err < 0) {
  921. dev_err(dev, "cannot assert reset: %d\n", err);
  922. goto disable_clk_lp;
  923. }
  924. }
  925. return 0;
  926. disable_clk_lp:
  927. clk_disable_unprepare(dsi->clk_lp);
  928. disable_clk:
  929. clk_disable_unprepare(dsi->clk);
  930. disable_vdd:
  931. regulator_disable(dsi->vdd);
  932. put_rpm:
  933. pm_runtime_put_sync(dev);
  934. return err;
  935. }
  936. static const struct host1x_client_ops dsi_client_ops = {
  937. .init = tegra_dsi_init,
  938. .exit = tegra_dsi_exit,
  939. .suspend = tegra_dsi_runtime_suspend,
  940. .resume = tegra_dsi_runtime_resume,
  941. };
  942. static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
  943. {
  944. struct clk *parent;
  945. int err;
  946. parent = clk_get_parent(dsi->clk);
  947. if (!parent)
  948. return -EINVAL;
  949. err = clk_set_parent(parent, dsi->clk_parent);
  950. if (err < 0)
  951. return err;
  952. return 0;
  953. }
  954. static const char * const error_report[16] = {
  955. "SoT Error",
  956. "SoT Sync Error",
  957. "EoT Sync Error",
  958. "Escape Mode Entry Command Error",
  959. "Low-Power Transmit Sync Error",
  960. "Peripheral Timeout Error",
  961. "False Control Error",
  962. "Contention Detected",
  963. "ECC Error, single-bit",
  964. "ECC Error, multi-bit",
  965. "Checksum Error",
  966. "DSI Data Type Not Recognized",
  967. "DSI VC ID Invalid",
  968. "Invalid Transmission Length",
  969. "Reserved",
  970. "DSI Protocol Violation",
  971. };
  972. static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
  973. const struct mipi_dsi_msg *msg,
  974. size_t count)
  975. {
  976. u8 *rx = msg->rx_buf;
  977. unsigned int i, j, k;
  978. size_t size = 0;
  979. u16 errors;
  980. u32 value;
  981. /* read and parse packet header */
  982. value = tegra_dsi_readl(dsi, DSI_RD_DATA);
  983. switch (value & 0x3f) {
  984. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  985. errors = (value >> 8) & 0xffff;
  986. dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
  987. errors);
  988. for (i = 0; i < ARRAY_SIZE(error_report); i++)
  989. if (errors & BIT(i))
  990. dev_dbg(dsi->dev, " %2u: %s\n", i,
  991. error_report[i]);
  992. break;
  993. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  994. rx[0] = (value >> 8) & 0xff;
  995. size = 1;
  996. break;
  997. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  998. rx[0] = (value >> 8) & 0xff;
  999. rx[1] = (value >> 16) & 0xff;
  1000. size = 2;
  1001. break;
  1002. case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
  1003. size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
  1004. break;
  1005. case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
  1006. size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
  1007. break;
  1008. default:
  1009. dev_err(dsi->dev, "unhandled response type: %02x\n",
  1010. value & 0x3f);
  1011. return -EPROTO;
  1012. }
  1013. size = min(size, msg->rx_len);
  1014. if (msg->rx_buf && size > 0) {
  1015. for (i = 0, j = 0; i < count - 1; i++, j += 4) {
  1016. u8 *rx = msg->rx_buf + j;
  1017. value = tegra_dsi_readl(dsi, DSI_RD_DATA);
  1018. for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
  1019. rx[j + k] = (value >> (k << 3)) & 0xff;
  1020. }
  1021. }
  1022. return size;
  1023. }
  1024. static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
  1025. {
  1026. tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
  1027. timeout = jiffies + msecs_to_jiffies(timeout);
  1028. while (time_before(jiffies, timeout)) {
  1029. u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
  1030. if ((value & DSI_TRIGGER_HOST) == 0)
  1031. return 0;
  1032. usleep_range(1000, 2000);
  1033. }
  1034. DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
  1035. return -ETIMEDOUT;
  1036. }
  1037. static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
  1038. unsigned long timeout)
  1039. {
  1040. timeout = jiffies + msecs_to_jiffies(250);
  1041. while (time_before(jiffies, timeout)) {
  1042. u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
  1043. u8 count = value & 0x1f;
  1044. if (count > 0)
  1045. return count;
  1046. usleep_range(1000, 2000);
  1047. }
  1048. DRM_DEBUG_KMS("peripheral returned no data\n");
  1049. return -ETIMEDOUT;
  1050. }
  1051. static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
  1052. const void *buffer, size_t size)
  1053. {
  1054. const u8 *buf = buffer;
  1055. size_t i, j;
  1056. u32 value;
  1057. for (j = 0; j < size; j += 4) {
  1058. value = 0;
  1059. for (i = 0; i < 4 && j + i < size; i++)
  1060. value |= buf[j + i] << (i << 3);
  1061. tegra_dsi_writel(dsi, value, DSI_WR_DATA);
  1062. }
  1063. }
  1064. static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
  1065. const struct mipi_dsi_msg *msg)
  1066. {
  1067. struct tegra_dsi *dsi = host_to_tegra(host);
  1068. struct mipi_dsi_packet packet;
  1069. const u8 *header;
  1070. size_t count;
  1071. ssize_t err;
  1072. u32 value;
  1073. err = mipi_dsi_create_packet(&packet, msg);
  1074. if (err < 0)
  1075. return err;
  1076. header = packet.header;
  1077. /* maximum FIFO depth is 1920 words */
  1078. if (packet.size > dsi->video_fifo_depth * 4)
  1079. return -ENOSPC;
  1080. /* reset underflow/overflow flags */
  1081. value = tegra_dsi_readl(dsi, DSI_STATUS);
  1082. if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
  1083. value = DSI_HOST_CONTROL_FIFO_RESET;
  1084. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  1085. usleep_range(10, 20);
  1086. }
  1087. value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
  1088. value |= DSI_POWER_CONTROL_ENABLE;
  1089. tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
  1090. usleep_range(5000, 10000);
  1091. value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
  1092. DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
  1093. if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
  1094. value |= DSI_HOST_CONTROL_HS;
  1095. /*
  1096. * The host FIFO has a maximum of 64 words, so larger transmissions
  1097. * need to use the video FIFO.
  1098. */
  1099. if (packet.size > dsi->host_fifo_depth * 4)
  1100. value |= DSI_HOST_CONTROL_FIFO_SEL;
  1101. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  1102. /*
  1103. * For reads and messages with explicitly requested ACK, generate a
  1104. * BTA sequence after the transmission of the packet.
  1105. */
  1106. if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
  1107. (msg->rx_buf && msg->rx_len > 0)) {
  1108. value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
  1109. value |= DSI_HOST_CONTROL_PKT_BTA;
  1110. tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
  1111. }
  1112. value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
  1113. tegra_dsi_writel(dsi, value, DSI_CONTROL);
  1114. /* write packet header, ECC is generated by hardware */
  1115. value = header[2] << 16 | header[1] << 8 | header[0];
  1116. tegra_dsi_writel(dsi, value, DSI_WR_DATA);
  1117. /* write payload (if any) */
  1118. if (packet.payload_length > 0)
  1119. tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
  1120. packet.payload_length);
  1121. err = tegra_dsi_transmit(dsi, 250);
  1122. if (err < 0)
  1123. return err;
  1124. if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
  1125. (msg->rx_buf && msg->rx_len > 0)) {
  1126. err = tegra_dsi_wait_for_response(dsi, 250);
  1127. if (err < 0)
  1128. return err;
  1129. count = err;
  1130. value = tegra_dsi_readl(dsi, DSI_RD_DATA);
  1131. switch (value) {
  1132. case 0x84:
  1133. /*
  1134. dev_dbg(dsi->dev, "ACK\n");
  1135. */
  1136. break;
  1137. case 0x87:
  1138. /*
  1139. dev_dbg(dsi->dev, "ESCAPE\n");
  1140. */
  1141. break;
  1142. default:
  1143. dev_err(dsi->dev, "unknown status: %08x\n", value);
  1144. break;
  1145. }
  1146. if (count > 1) {
  1147. err = tegra_dsi_read_response(dsi, msg, count);
  1148. if (err < 0)
  1149. dev_err(dsi->dev,
  1150. "failed to parse response: %zd\n",
  1151. err);
  1152. else {
  1153. /*
  1154. * For read commands, return the number of
  1155. * bytes returned by the peripheral.
  1156. */
  1157. count = err;
  1158. }
  1159. }
  1160. } else {
  1161. /*
  1162. * For write commands, we have transmitted the 4-byte header
  1163. * plus the variable-length payload.
  1164. */
  1165. count = 4 + packet.payload_length;
  1166. }
  1167. return count;
  1168. }
  1169. static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
  1170. {
  1171. struct clk *parent;
  1172. int err;
  1173. /* make sure both DSI controllers share the same PLL */
  1174. parent = clk_get_parent(dsi->slave->clk);
  1175. if (!parent)
  1176. return -EINVAL;
  1177. err = clk_set_parent(parent, dsi->clk_parent);
  1178. if (err < 0)
  1179. return err;
  1180. return 0;
  1181. }
  1182. static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
  1183. struct mipi_dsi_device *device)
  1184. {
  1185. struct tegra_dsi *dsi = host_to_tegra(host);
  1186. dsi->flags = device->mode_flags;
  1187. dsi->format = device->format;
  1188. dsi->lanes = device->lanes;
  1189. if (dsi->slave) {
  1190. int err;
  1191. dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
  1192. dev_name(&device->dev));
  1193. err = tegra_dsi_ganged_setup(dsi);
  1194. if (err < 0) {
  1195. dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
  1196. err);
  1197. return err;
  1198. }
  1199. }
  1200. /*
  1201. * Slaves don't have a panel associated with them, so they provide
  1202. * merely the second channel.
  1203. */
  1204. if (!dsi->master) {
  1205. struct tegra_output *output = &dsi->output;
  1206. output->panel = of_drm_find_panel(device->dev.of_node);
  1207. if (IS_ERR(output->panel))
  1208. output->panel = NULL;
  1209. if (output->panel && output->connector.dev)
  1210. drm_helper_hpd_irq_event(output->connector.dev);
  1211. }
  1212. return 0;
  1213. }
  1214. static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
  1215. struct mipi_dsi_device *device)
  1216. {
  1217. struct tegra_dsi *dsi = host_to_tegra(host);
  1218. struct tegra_output *output = &dsi->output;
  1219. if (output->panel && &device->dev == output->panel->dev) {
  1220. output->panel = NULL;
  1221. if (output->connector.dev)
  1222. drm_helper_hpd_irq_event(output->connector.dev);
  1223. }
  1224. return 0;
  1225. }
  1226. static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
  1227. .attach = tegra_dsi_host_attach,
  1228. .detach = tegra_dsi_host_detach,
  1229. .transfer = tegra_dsi_host_transfer,
  1230. };
  1231. static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
  1232. {
  1233. struct device_node *np;
  1234. np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
  1235. if (np) {
  1236. struct platform_device *gangster = of_find_device_by_node(np);
  1237. dsi->slave = platform_get_drvdata(gangster);
  1238. of_node_put(np);
  1239. if (!dsi->slave) {
  1240. put_device(&gangster->dev);
  1241. return -EPROBE_DEFER;
  1242. }
  1243. dsi->slave->master = dsi;
  1244. }
  1245. return 0;
  1246. }
  1247. static int tegra_dsi_probe(struct platform_device *pdev)
  1248. {
  1249. struct tegra_dsi *dsi;
  1250. struct resource *regs;
  1251. int err;
  1252. dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
  1253. if (!dsi)
  1254. return -ENOMEM;
  1255. dsi->output.dev = dsi->dev = &pdev->dev;
  1256. dsi->video_fifo_depth = 1920;
  1257. dsi->host_fifo_depth = 64;
  1258. err = tegra_dsi_ganged_probe(dsi);
  1259. if (err < 0)
  1260. return err;
  1261. err = tegra_output_probe(&dsi->output);
  1262. if (err < 0)
  1263. return err;
  1264. dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
  1265. /*
  1266. * Assume these values by default. When a DSI peripheral driver
  1267. * attaches to the DSI host, the parameters will be taken from
  1268. * the attached device.
  1269. */
  1270. dsi->flags = MIPI_DSI_MODE_VIDEO;
  1271. dsi->format = MIPI_DSI_FMT_RGB888;
  1272. dsi->lanes = 4;
  1273. if (!pdev->dev.pm_domain) {
  1274. dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
  1275. if (IS_ERR(dsi->rst))
  1276. return PTR_ERR(dsi->rst);
  1277. }
  1278. dsi->clk = devm_clk_get(&pdev->dev, NULL);
  1279. if (IS_ERR(dsi->clk)) {
  1280. dev_err(&pdev->dev, "cannot get DSI clock\n");
  1281. return PTR_ERR(dsi->clk);
  1282. }
  1283. dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
  1284. if (IS_ERR(dsi->clk_lp)) {
  1285. dev_err(&pdev->dev, "cannot get low-power clock\n");
  1286. return PTR_ERR(dsi->clk_lp);
  1287. }
  1288. dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
  1289. if (IS_ERR(dsi->clk_parent)) {
  1290. dev_err(&pdev->dev, "cannot get parent clock\n");
  1291. return PTR_ERR(dsi->clk_parent);
  1292. }
  1293. dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
  1294. if (IS_ERR(dsi->vdd)) {
  1295. dev_err(&pdev->dev, "cannot get VDD supply\n");
  1296. return PTR_ERR(dsi->vdd);
  1297. }
  1298. err = tegra_dsi_setup_clocks(dsi);
  1299. if (err < 0) {
  1300. dev_err(&pdev->dev, "cannot setup clocks\n");
  1301. return err;
  1302. }
  1303. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1304. dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
  1305. if (IS_ERR(dsi->regs))
  1306. return PTR_ERR(dsi->regs);
  1307. dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
  1308. if (IS_ERR(dsi->mipi))
  1309. return PTR_ERR(dsi->mipi);
  1310. dsi->host.ops = &tegra_dsi_host_ops;
  1311. dsi->host.dev = &pdev->dev;
  1312. err = mipi_dsi_host_register(&dsi->host);
  1313. if (err < 0) {
  1314. dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
  1315. goto mipi_free;
  1316. }
  1317. platform_set_drvdata(pdev, dsi);
  1318. pm_runtime_enable(&pdev->dev);
  1319. INIT_LIST_HEAD(&dsi->client.list);
  1320. dsi->client.ops = &dsi_client_ops;
  1321. dsi->client.dev = &pdev->dev;
  1322. err = host1x_client_register(&dsi->client);
  1323. if (err < 0) {
  1324. dev_err(&pdev->dev, "failed to register host1x client: %d\n",
  1325. err);
  1326. goto unregister;
  1327. }
  1328. return 0;
  1329. unregister:
  1330. mipi_dsi_host_unregister(&dsi->host);
  1331. mipi_free:
  1332. tegra_mipi_free(dsi->mipi);
  1333. return err;
  1334. }
  1335. static int tegra_dsi_remove(struct platform_device *pdev)
  1336. {
  1337. struct tegra_dsi *dsi = platform_get_drvdata(pdev);
  1338. int err;
  1339. pm_runtime_disable(&pdev->dev);
  1340. err = host1x_client_unregister(&dsi->client);
  1341. if (err < 0) {
  1342. dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
  1343. err);
  1344. return err;
  1345. }
  1346. tegra_output_remove(&dsi->output);
  1347. mipi_dsi_host_unregister(&dsi->host);
  1348. tegra_mipi_free(dsi->mipi);
  1349. return 0;
  1350. }
  1351. static const struct of_device_id tegra_dsi_of_match[] = {
  1352. { .compatible = "nvidia,tegra210-dsi", },
  1353. { .compatible = "nvidia,tegra132-dsi", },
  1354. { .compatible = "nvidia,tegra124-dsi", },
  1355. { .compatible = "nvidia,tegra114-dsi", },
  1356. { },
  1357. };
  1358. MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
  1359. struct platform_driver tegra_dsi_driver = {
  1360. .driver = {
  1361. .name = "tegra-dsi",
  1362. .of_match_table = tegra_dsi_of_match,
  1363. },
  1364. .probe = tegra_dsi_probe,
  1365. .remove = tegra_dsi_remove,
  1366. };