dpaux.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 NVIDIA Corporation
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/pinctrl/pinconf-generic.h>
  12. #include <linux/pinctrl/pinctrl.h>
  13. #include <linux/pinctrl/pinmux.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/reset.h>
  18. #include <linux/workqueue.h>
  19. #include <drm/drm_dp_helper.h>
  20. #include <drm/drm_panel.h>
  21. #include "dp.h"
  22. #include "dpaux.h"
  23. #include "drm.h"
  24. #include "trace.h"
  25. static DEFINE_MUTEX(dpaux_lock);
  26. static LIST_HEAD(dpaux_list);
  27. struct tegra_dpaux_soc {
  28. unsigned int cmh;
  29. unsigned int drvz;
  30. unsigned int drvi;
  31. };
  32. struct tegra_dpaux {
  33. struct drm_dp_aux aux;
  34. struct device *dev;
  35. const struct tegra_dpaux_soc *soc;
  36. void __iomem *regs;
  37. int irq;
  38. struct tegra_output *output;
  39. struct reset_control *rst;
  40. struct clk *clk_parent;
  41. struct clk *clk;
  42. struct regulator *vdd;
  43. struct completion complete;
  44. struct work_struct work;
  45. struct list_head list;
  46. #ifdef CONFIG_GENERIC_PINCONF
  47. struct pinctrl_dev *pinctrl;
  48. struct pinctrl_desc desc;
  49. #endif
  50. };
  51. static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
  52. {
  53. return container_of(aux, struct tegra_dpaux, aux);
  54. }
  55. static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
  56. {
  57. return container_of(work, struct tegra_dpaux, work);
  58. }
  59. static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
  60. unsigned int offset)
  61. {
  62. u32 value = readl(dpaux->regs + (offset << 2));
  63. trace_dpaux_readl(dpaux->dev, offset, value);
  64. return value;
  65. }
  66. static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
  67. u32 value, unsigned int offset)
  68. {
  69. trace_dpaux_writel(dpaux->dev, offset, value);
  70. writel(value, dpaux->regs + (offset << 2));
  71. }
  72. static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
  73. size_t size)
  74. {
  75. size_t i, j;
  76. for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
  77. size_t num = min_t(size_t, size - i * 4, 4);
  78. u32 value = 0;
  79. for (j = 0; j < num; j++)
  80. value |= buffer[i * 4 + j] << (j * 8);
  81. tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
  82. }
  83. }
  84. static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
  85. size_t size)
  86. {
  87. size_t i, j;
  88. for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
  89. size_t num = min_t(size_t, size - i * 4, 4);
  90. u32 value;
  91. value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
  92. for (j = 0; j < num; j++)
  93. buffer[i * 4 + j] = value >> (j * 8);
  94. }
  95. }
  96. static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
  97. struct drm_dp_aux_msg *msg)
  98. {
  99. unsigned long timeout = msecs_to_jiffies(250);
  100. struct tegra_dpaux *dpaux = to_dpaux(aux);
  101. unsigned long status;
  102. ssize_t ret = 0;
  103. u8 reply = 0;
  104. u32 value;
  105. /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
  106. if (msg->size > 16)
  107. return -EINVAL;
  108. /*
  109. * Allow zero-sized messages only for I2C, in which case they specify
  110. * address-only transactions.
  111. */
  112. if (msg->size < 1) {
  113. switch (msg->request & ~DP_AUX_I2C_MOT) {
  114. case DP_AUX_I2C_WRITE_STATUS_UPDATE:
  115. case DP_AUX_I2C_WRITE:
  116. case DP_AUX_I2C_READ:
  117. value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
  118. break;
  119. default:
  120. return -EINVAL;
  121. }
  122. } else {
  123. /* For non-zero-sized messages, set the CMDLEN field. */
  124. value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
  125. }
  126. switch (msg->request & ~DP_AUX_I2C_MOT) {
  127. case DP_AUX_I2C_WRITE:
  128. if (msg->request & DP_AUX_I2C_MOT)
  129. value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
  130. else
  131. value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
  132. break;
  133. case DP_AUX_I2C_READ:
  134. if (msg->request & DP_AUX_I2C_MOT)
  135. value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
  136. else
  137. value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
  138. break;
  139. case DP_AUX_I2C_WRITE_STATUS_UPDATE:
  140. if (msg->request & DP_AUX_I2C_MOT)
  141. value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
  142. else
  143. value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
  144. break;
  145. case DP_AUX_NATIVE_WRITE:
  146. value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
  147. break;
  148. case DP_AUX_NATIVE_READ:
  149. value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
  150. break;
  151. default:
  152. return -EINVAL;
  153. }
  154. tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
  155. tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
  156. if ((msg->request & DP_AUX_I2C_READ) == 0) {
  157. tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
  158. ret = msg->size;
  159. }
  160. /* start transaction */
  161. value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
  162. value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
  163. tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
  164. status = wait_for_completion_timeout(&dpaux->complete, timeout);
  165. if (!status)
  166. return -ETIMEDOUT;
  167. /* read status and clear errors */
  168. value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
  169. tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
  170. if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
  171. return -ETIMEDOUT;
  172. if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
  173. (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
  174. (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
  175. return -EIO;
  176. switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
  177. case 0x00:
  178. reply = DP_AUX_NATIVE_REPLY_ACK;
  179. break;
  180. case 0x01:
  181. reply = DP_AUX_NATIVE_REPLY_NACK;
  182. break;
  183. case 0x02:
  184. reply = DP_AUX_NATIVE_REPLY_DEFER;
  185. break;
  186. case 0x04:
  187. reply = DP_AUX_I2C_REPLY_NACK;
  188. break;
  189. case 0x08:
  190. reply = DP_AUX_I2C_REPLY_DEFER;
  191. break;
  192. }
  193. if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
  194. if (msg->request & DP_AUX_I2C_READ) {
  195. size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
  196. /*
  197. * There might be a smarter way to do this, but since
  198. * the DP helpers will already retry transactions for
  199. * an -EBUSY return value, simply reuse that instead.
  200. */
  201. if (count != msg->size) {
  202. ret = -EBUSY;
  203. goto out;
  204. }
  205. tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
  206. ret = count;
  207. }
  208. }
  209. msg->reply = reply;
  210. out:
  211. return ret;
  212. }
  213. static void tegra_dpaux_hotplug(struct work_struct *work)
  214. {
  215. struct tegra_dpaux *dpaux = work_to_dpaux(work);
  216. if (dpaux->output)
  217. drm_helper_hpd_irq_event(dpaux->output->connector.dev);
  218. }
  219. static irqreturn_t tegra_dpaux_irq(int irq, void *data)
  220. {
  221. struct tegra_dpaux *dpaux = data;
  222. irqreturn_t ret = IRQ_HANDLED;
  223. u32 value;
  224. /* clear interrupts */
  225. value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
  226. tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
  227. if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
  228. schedule_work(&dpaux->work);
  229. if (value & DPAUX_INTR_IRQ_EVENT) {
  230. /* TODO: handle this */
  231. }
  232. if (value & DPAUX_INTR_AUX_DONE)
  233. complete(&dpaux->complete);
  234. return ret;
  235. }
  236. enum tegra_dpaux_functions {
  237. DPAUX_PADCTL_FUNC_AUX,
  238. DPAUX_PADCTL_FUNC_I2C,
  239. DPAUX_PADCTL_FUNC_OFF,
  240. };
  241. static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
  242. {
  243. u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
  244. value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
  245. tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
  246. }
  247. static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
  248. {
  249. u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
  250. value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
  251. tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
  252. }
  253. static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
  254. {
  255. u32 value;
  256. switch (function) {
  257. case DPAUX_PADCTL_FUNC_AUX:
  258. value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
  259. DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
  260. DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
  261. DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
  262. DPAUX_HYBRID_PADCTL_MODE_AUX;
  263. break;
  264. case DPAUX_PADCTL_FUNC_I2C:
  265. value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
  266. DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
  267. DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
  268. DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
  269. DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
  270. DPAUX_HYBRID_PADCTL_MODE_I2C;
  271. break;
  272. case DPAUX_PADCTL_FUNC_OFF:
  273. tegra_dpaux_pad_power_down(dpaux);
  274. return 0;
  275. default:
  276. return -ENOTSUPP;
  277. }
  278. tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
  279. tegra_dpaux_pad_power_up(dpaux);
  280. return 0;
  281. }
  282. #ifdef CONFIG_GENERIC_PINCONF
  283. static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
  284. PINCTRL_PIN(0, "DP_AUX_CHx_P"),
  285. PINCTRL_PIN(1, "DP_AUX_CHx_N"),
  286. };
  287. static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
  288. static const char * const tegra_dpaux_groups[] = {
  289. "dpaux-io",
  290. };
  291. static const char * const tegra_dpaux_functions[] = {
  292. "aux",
  293. "i2c",
  294. "off",
  295. };
  296. static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
  297. {
  298. return ARRAY_SIZE(tegra_dpaux_groups);
  299. }
  300. static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
  301. unsigned int group)
  302. {
  303. return tegra_dpaux_groups[group];
  304. }
  305. static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
  306. unsigned group, const unsigned **pins,
  307. unsigned *num_pins)
  308. {
  309. *pins = tegra_dpaux_pin_numbers;
  310. *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
  311. return 0;
  312. }
  313. static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
  314. .get_groups_count = tegra_dpaux_get_groups_count,
  315. .get_group_name = tegra_dpaux_get_group_name,
  316. .get_group_pins = tegra_dpaux_get_group_pins,
  317. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  318. .dt_free_map = pinconf_generic_dt_free_map,
  319. };
  320. static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
  321. {
  322. return ARRAY_SIZE(tegra_dpaux_functions);
  323. }
  324. static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
  325. unsigned int function)
  326. {
  327. return tegra_dpaux_functions[function];
  328. }
  329. static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
  330. unsigned int function,
  331. const char * const **groups,
  332. unsigned * const num_groups)
  333. {
  334. *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
  335. *groups = tegra_dpaux_groups;
  336. return 0;
  337. }
  338. static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
  339. unsigned int function, unsigned int group)
  340. {
  341. struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
  342. return tegra_dpaux_pad_config(dpaux, function);
  343. }
  344. static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
  345. .get_functions_count = tegra_dpaux_get_functions_count,
  346. .get_function_name = tegra_dpaux_get_function_name,
  347. .get_function_groups = tegra_dpaux_get_function_groups,
  348. .set_mux = tegra_dpaux_set_mux,
  349. };
  350. #endif
  351. static int tegra_dpaux_probe(struct platform_device *pdev)
  352. {
  353. struct tegra_dpaux *dpaux;
  354. struct resource *regs;
  355. u32 value;
  356. int err;
  357. dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
  358. if (!dpaux)
  359. return -ENOMEM;
  360. dpaux->soc = of_device_get_match_data(&pdev->dev);
  361. INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
  362. init_completion(&dpaux->complete);
  363. INIT_LIST_HEAD(&dpaux->list);
  364. dpaux->dev = &pdev->dev;
  365. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  366. dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
  367. if (IS_ERR(dpaux->regs))
  368. return PTR_ERR(dpaux->regs);
  369. dpaux->irq = platform_get_irq(pdev, 0);
  370. if (dpaux->irq < 0) {
  371. dev_err(&pdev->dev, "failed to get IRQ\n");
  372. return -ENXIO;
  373. }
  374. if (!pdev->dev.pm_domain) {
  375. dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
  376. if (IS_ERR(dpaux->rst)) {
  377. dev_err(&pdev->dev,
  378. "failed to get reset control: %ld\n",
  379. PTR_ERR(dpaux->rst));
  380. return PTR_ERR(dpaux->rst);
  381. }
  382. }
  383. dpaux->clk = devm_clk_get(&pdev->dev, NULL);
  384. if (IS_ERR(dpaux->clk)) {
  385. dev_err(&pdev->dev, "failed to get module clock: %ld\n",
  386. PTR_ERR(dpaux->clk));
  387. return PTR_ERR(dpaux->clk);
  388. }
  389. dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
  390. if (IS_ERR(dpaux->clk_parent)) {
  391. dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
  392. PTR_ERR(dpaux->clk_parent));
  393. return PTR_ERR(dpaux->clk_parent);
  394. }
  395. err = clk_set_rate(dpaux->clk_parent, 270000000);
  396. if (err < 0) {
  397. dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
  398. err);
  399. return err;
  400. }
  401. dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
  402. if (IS_ERR(dpaux->vdd)) {
  403. if (PTR_ERR(dpaux->vdd) != -ENODEV) {
  404. if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
  405. dev_err(&pdev->dev,
  406. "failed to get VDD supply: %ld\n",
  407. PTR_ERR(dpaux->vdd));
  408. return PTR_ERR(dpaux->vdd);
  409. }
  410. dpaux->vdd = NULL;
  411. }
  412. platform_set_drvdata(pdev, dpaux);
  413. pm_runtime_enable(&pdev->dev);
  414. pm_runtime_get_sync(&pdev->dev);
  415. err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
  416. dev_name(dpaux->dev), dpaux);
  417. if (err < 0) {
  418. dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
  419. dpaux->irq, err);
  420. return err;
  421. }
  422. disable_irq(dpaux->irq);
  423. dpaux->aux.transfer = tegra_dpaux_transfer;
  424. dpaux->aux.dev = &pdev->dev;
  425. err = drm_dp_aux_register(&dpaux->aux);
  426. if (err < 0)
  427. return err;
  428. /*
  429. * Assume that by default the DPAUX/I2C pads will be used for HDMI,
  430. * so power them up and configure them in I2C mode.
  431. *
  432. * The DPAUX code paths reconfigure the pads in AUX mode, but there
  433. * is no possibility to perform the I2C mode configuration in the
  434. * HDMI path.
  435. */
  436. err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
  437. if (err < 0)
  438. return err;
  439. #ifdef CONFIG_GENERIC_PINCONF
  440. dpaux->desc.name = dev_name(&pdev->dev);
  441. dpaux->desc.pins = tegra_dpaux_pins;
  442. dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
  443. dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
  444. dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
  445. dpaux->desc.owner = THIS_MODULE;
  446. dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
  447. if (IS_ERR(dpaux->pinctrl)) {
  448. dev_err(&pdev->dev, "failed to register pincontrol\n");
  449. return PTR_ERR(dpaux->pinctrl);
  450. }
  451. #endif
  452. /* enable and clear all interrupts */
  453. value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
  454. DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
  455. tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
  456. tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
  457. mutex_lock(&dpaux_lock);
  458. list_add_tail(&dpaux->list, &dpaux_list);
  459. mutex_unlock(&dpaux_lock);
  460. return 0;
  461. }
  462. static int tegra_dpaux_remove(struct platform_device *pdev)
  463. {
  464. struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
  465. cancel_work_sync(&dpaux->work);
  466. /* make sure pads are powered down when not in use */
  467. tegra_dpaux_pad_power_down(dpaux);
  468. pm_runtime_put_sync(&pdev->dev);
  469. pm_runtime_disable(&pdev->dev);
  470. drm_dp_aux_unregister(&dpaux->aux);
  471. mutex_lock(&dpaux_lock);
  472. list_del(&dpaux->list);
  473. mutex_unlock(&dpaux_lock);
  474. return 0;
  475. }
  476. #ifdef CONFIG_PM
  477. static int tegra_dpaux_suspend(struct device *dev)
  478. {
  479. struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
  480. int err = 0;
  481. if (dpaux->rst) {
  482. err = reset_control_assert(dpaux->rst);
  483. if (err < 0) {
  484. dev_err(dev, "failed to assert reset: %d\n", err);
  485. return err;
  486. }
  487. }
  488. usleep_range(1000, 2000);
  489. clk_disable_unprepare(dpaux->clk_parent);
  490. clk_disable_unprepare(dpaux->clk);
  491. return err;
  492. }
  493. static int tegra_dpaux_resume(struct device *dev)
  494. {
  495. struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
  496. int err;
  497. err = clk_prepare_enable(dpaux->clk);
  498. if (err < 0) {
  499. dev_err(dev, "failed to enable clock: %d\n", err);
  500. return err;
  501. }
  502. err = clk_prepare_enable(dpaux->clk_parent);
  503. if (err < 0) {
  504. dev_err(dev, "failed to enable parent clock: %d\n", err);
  505. goto disable_clk;
  506. }
  507. usleep_range(1000, 2000);
  508. if (dpaux->rst) {
  509. err = reset_control_deassert(dpaux->rst);
  510. if (err < 0) {
  511. dev_err(dev, "failed to deassert reset: %d\n", err);
  512. goto disable_parent;
  513. }
  514. usleep_range(1000, 2000);
  515. }
  516. return 0;
  517. disable_parent:
  518. clk_disable_unprepare(dpaux->clk_parent);
  519. disable_clk:
  520. clk_disable_unprepare(dpaux->clk);
  521. return err;
  522. }
  523. #endif
  524. static const struct dev_pm_ops tegra_dpaux_pm_ops = {
  525. SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
  526. };
  527. static const struct tegra_dpaux_soc tegra124_dpaux_soc = {
  528. .cmh = 0x02,
  529. .drvz = 0x04,
  530. .drvi = 0x18,
  531. };
  532. static const struct tegra_dpaux_soc tegra210_dpaux_soc = {
  533. .cmh = 0x02,
  534. .drvz = 0x04,
  535. .drvi = 0x30,
  536. };
  537. static const struct tegra_dpaux_soc tegra194_dpaux_soc = {
  538. .cmh = 0x02,
  539. .drvz = 0x04,
  540. .drvi = 0x2c,
  541. };
  542. static const struct of_device_id tegra_dpaux_of_match[] = {
  543. { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
  544. { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
  545. { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
  546. { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
  547. { },
  548. };
  549. MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
  550. struct platform_driver tegra_dpaux_driver = {
  551. .driver = {
  552. .name = "tegra-dpaux",
  553. .of_match_table = tegra_dpaux_of_match,
  554. .pm = &tegra_dpaux_pm_ops,
  555. },
  556. .probe = tegra_dpaux_probe,
  557. .remove = tegra_dpaux_remove,
  558. };
  559. struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
  560. {
  561. struct tegra_dpaux *dpaux;
  562. mutex_lock(&dpaux_lock);
  563. list_for_each_entry(dpaux, &dpaux_list, list)
  564. if (np == dpaux->dev->of_node) {
  565. mutex_unlock(&dpaux_lock);
  566. return &dpaux->aux;
  567. }
  568. mutex_unlock(&dpaux_lock);
  569. return NULL;
  570. }
  571. int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
  572. {
  573. struct tegra_dpaux *dpaux = to_dpaux(aux);
  574. unsigned long timeout;
  575. int err;
  576. output->connector.polled = DRM_CONNECTOR_POLL_HPD;
  577. dpaux->output = output;
  578. if (output->panel) {
  579. enum drm_connector_status status;
  580. if (dpaux->vdd) {
  581. err = regulator_enable(dpaux->vdd);
  582. if (err < 0)
  583. return err;
  584. }
  585. timeout = jiffies + msecs_to_jiffies(250);
  586. while (time_before(jiffies, timeout)) {
  587. status = drm_dp_aux_detect(aux);
  588. if (status == connector_status_connected)
  589. break;
  590. usleep_range(1000, 2000);
  591. }
  592. if (status != connector_status_connected)
  593. return -ETIMEDOUT;
  594. }
  595. enable_irq(dpaux->irq);
  596. return 0;
  597. }
  598. int drm_dp_aux_detach(struct drm_dp_aux *aux)
  599. {
  600. struct tegra_dpaux *dpaux = to_dpaux(aux);
  601. unsigned long timeout;
  602. int err;
  603. disable_irq(dpaux->irq);
  604. if (dpaux->output->panel) {
  605. enum drm_connector_status status;
  606. if (dpaux->vdd) {
  607. err = regulator_disable(dpaux->vdd);
  608. if (err < 0)
  609. return err;
  610. }
  611. timeout = jiffies + msecs_to_jiffies(250);
  612. while (time_before(jiffies, timeout)) {
  613. status = drm_dp_aux_detect(aux);
  614. if (status == connector_status_disconnected)
  615. break;
  616. usleep_range(1000, 2000);
  617. }
  618. if (status != connector_status_disconnected)
  619. return -ETIMEDOUT;
  620. dpaux->output = NULL;
  621. }
  622. return 0;
  623. }
  624. enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
  625. {
  626. struct tegra_dpaux *dpaux = to_dpaux(aux);
  627. u32 value;
  628. value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
  629. if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
  630. return connector_status_connected;
  631. return connector_status_disconnected;
  632. }
  633. int drm_dp_aux_enable(struct drm_dp_aux *aux)
  634. {
  635. struct tegra_dpaux *dpaux = to_dpaux(aux);
  636. return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
  637. }
  638. int drm_dp_aux_disable(struct drm_dp_aux *aux)
  639. {
  640. struct tegra_dpaux *dpaux = to_dpaux(aux);
  641. tegra_dpaux_pad_power_down(dpaux);
  642. return 0;
  643. }