dp.h 4.3 KB

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  1. /* SPDX-License-Identifier: MIT */
  2. /*
  3. * Copyright (C) 2013-2019 NVIDIA Corporation.
  4. * Copyright (C) 2015 Rob Clark
  5. */
  6. #ifndef DRM_TEGRA_DP_H
  7. #define DRM_TEGRA_DP_H 1
  8. #include <linux/types.h>
  9. struct drm_display_info;
  10. struct drm_display_mode;
  11. struct drm_dp_aux;
  12. struct drm_dp_link;
  13. /**
  14. * struct drm_dp_link_caps - DP link capabilities
  15. */
  16. struct drm_dp_link_caps {
  17. /**
  18. * @enhanced_framing:
  19. *
  20. * enhanced framing capability (mandatory as of DP 1.2)
  21. */
  22. bool enhanced_framing;
  23. /**
  24. * tps3_supported:
  25. *
  26. * training pattern sequence 3 supported for equalization
  27. */
  28. bool tps3_supported;
  29. /**
  30. * @fast_training:
  31. *
  32. * AUX CH handshake not required for link training
  33. */
  34. bool fast_training;
  35. /**
  36. * @channel_coding:
  37. *
  38. * ANSI 8B/10B channel coding capability
  39. */
  40. bool channel_coding;
  41. /**
  42. * @alternate_scrambler_reset:
  43. *
  44. * eDP alternate scrambler reset capability
  45. */
  46. bool alternate_scrambler_reset;
  47. };
  48. void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
  49. const struct drm_dp_link_caps *src);
  50. /**
  51. * struct drm_dp_link_ops - DP link operations
  52. */
  53. struct drm_dp_link_ops {
  54. /**
  55. * @apply_training:
  56. */
  57. int (*apply_training)(struct drm_dp_link *link);
  58. /**
  59. * @configure:
  60. */
  61. int (*configure)(struct drm_dp_link *link);
  62. };
  63. #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
  64. #define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
  65. #define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
  66. /**
  67. * struct drm_dp_link_train_set - link training settings
  68. * @voltage_swing: per-lane voltage swing
  69. * @pre_emphasis: per-lane pre-emphasis
  70. * @post_cursor: per-lane post-cursor
  71. */
  72. struct drm_dp_link_train_set {
  73. unsigned int voltage_swing[4];
  74. unsigned int pre_emphasis[4];
  75. unsigned int post_cursor[4];
  76. };
  77. /**
  78. * struct drm_dp_link_train - link training state information
  79. * @request: currently requested settings
  80. * @adjust: adjustments requested by sink
  81. * @pattern: currently requested training pattern
  82. * @clock_recovered: flag to track if clock recovery has completed
  83. * @channel_equalized: flag to track if channel equalization has completed
  84. */
  85. struct drm_dp_link_train {
  86. struct drm_dp_link_train_set request;
  87. struct drm_dp_link_train_set adjust;
  88. unsigned int pattern;
  89. bool clock_recovered;
  90. bool channel_equalized;
  91. };
  92. /**
  93. * struct drm_dp_link - DP link capabilities and configuration
  94. * @revision: DP specification revision supported on the link
  95. * @max_rate: maximum clock rate supported on the link
  96. * @max_lanes: maximum number of lanes supported on the link
  97. * @caps: capabilities supported on the link (see &drm_dp_link_caps)
  98. * @aux_rd_interval: AUX read interval to use for training (in microseconds)
  99. * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
  100. * @rate: currently configured link rate
  101. * @lanes: currently configured number of lanes
  102. * @rates: additional supported link rates in kHz (eDP 1.4)
  103. * @num_rates: number of additional supported link rates (eDP 1.4)
  104. */
  105. struct drm_dp_link {
  106. unsigned char revision;
  107. unsigned int max_rate;
  108. unsigned int max_lanes;
  109. struct drm_dp_link_caps caps;
  110. /**
  111. * @cr: clock recovery read interval
  112. * @ce: channel equalization read interval
  113. */
  114. struct {
  115. unsigned int cr;
  116. unsigned int ce;
  117. } aux_rd_interval;
  118. unsigned char edp;
  119. unsigned int rate;
  120. unsigned int lanes;
  121. unsigned long rates[DP_MAX_SUPPORTED_RATES];
  122. unsigned int num_rates;
  123. /**
  124. * @ops: DP link operations
  125. */
  126. const struct drm_dp_link_ops *ops;
  127. /**
  128. * @aux: DP AUX channel
  129. */
  130. struct drm_dp_aux *aux;
  131. /**
  132. * @train: DP link training state
  133. */
  134. struct drm_dp_link_train train;
  135. };
  136. int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
  137. int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
  138. void drm_dp_link_update_rates(struct drm_dp_link *link);
  139. int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
  140. int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
  141. int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
  142. int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
  143. int drm_dp_link_choose(struct drm_dp_link *link,
  144. const struct drm_display_mode *mode,
  145. const struct drm_display_info *info);
  146. void drm_dp_link_train_init(struct drm_dp_link_train *train);
  147. int drm_dp_link_train(struct drm_dp_link *link);
  148. #endif