dp.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876
  1. // SPDX-License-Identifier: MIT
  2. /*
  3. * Copyright (C) 2013-2019 NVIDIA Corporation
  4. * Copyright (C) 2015 Rob Clark
  5. */
  6. #include <drm/drm_crtc.h>
  7. #include <drm/drm_dp_helper.h>
  8. #include <drm/drm_print.h>
  9. #include "dp.h"
  10. static const u8 drm_dp_edp_revisions[] = { 0x11, 0x12, 0x13, 0x14 };
  11. static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
  12. {
  13. caps->enhanced_framing = false;
  14. caps->tps3_supported = false;
  15. caps->fast_training = false;
  16. caps->channel_coding = false;
  17. caps->alternate_scrambler_reset = false;
  18. }
  19. void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
  20. const struct drm_dp_link_caps *src)
  21. {
  22. dest->enhanced_framing = src->enhanced_framing;
  23. dest->tps3_supported = src->tps3_supported;
  24. dest->fast_training = src->fast_training;
  25. dest->channel_coding = src->channel_coding;
  26. dest->alternate_scrambler_reset = src->alternate_scrambler_reset;
  27. }
  28. static void drm_dp_link_reset(struct drm_dp_link *link)
  29. {
  30. unsigned int i;
  31. if (!link)
  32. return;
  33. link->revision = 0;
  34. link->max_rate = 0;
  35. link->max_lanes = 0;
  36. drm_dp_link_caps_reset(&link->caps);
  37. link->aux_rd_interval.cr = 0;
  38. link->aux_rd_interval.ce = 0;
  39. link->edp = 0;
  40. link->rate = 0;
  41. link->lanes = 0;
  42. for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++)
  43. link->rates[i] = 0;
  44. link->num_rates = 0;
  45. }
  46. /**
  47. * drm_dp_link_add_rate() - add a rate to the list of supported rates
  48. * @link: the link to add the rate to
  49. * @rate: the rate to add
  50. *
  51. * Add a link rate to the list of supported link rates.
  52. *
  53. * Returns:
  54. * 0 on success or one of the following negative error codes on failure:
  55. * - ENOSPC if the maximum number of supported rates has been reached
  56. * - EEXISTS if the link already supports this rate
  57. *
  58. * See also:
  59. * drm_dp_link_remove_rate()
  60. */
  61. int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate)
  62. {
  63. unsigned int i, pivot;
  64. if (link->num_rates == DP_MAX_SUPPORTED_RATES)
  65. return -ENOSPC;
  66. for (pivot = 0; pivot < link->num_rates; pivot++)
  67. if (rate <= link->rates[pivot])
  68. break;
  69. if (pivot != link->num_rates && rate == link->rates[pivot])
  70. return -EEXIST;
  71. for (i = link->num_rates; i > pivot; i--)
  72. link->rates[i] = link->rates[i - 1];
  73. link->rates[pivot] = rate;
  74. link->num_rates++;
  75. return 0;
  76. }
  77. /**
  78. * drm_dp_link_remove_rate() - remove a rate from the list of supported rates
  79. * @link: the link from which to remove the rate
  80. * @rate: the rate to remove
  81. *
  82. * Removes a link rate from the list of supported link rates.
  83. *
  84. * Returns:
  85. * 0 on success or one of the following negative error codes on failure:
  86. * - EINVAL if the specified rate is not among the supported rates
  87. *
  88. * See also:
  89. * drm_dp_link_add_rate()
  90. */
  91. int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate)
  92. {
  93. unsigned int i;
  94. for (i = 0; i < link->num_rates; i++)
  95. if (rate == link->rates[i])
  96. break;
  97. if (i == link->num_rates)
  98. return -EINVAL;
  99. link->num_rates--;
  100. while (i < link->num_rates) {
  101. link->rates[i] = link->rates[i + 1];
  102. i++;
  103. }
  104. return 0;
  105. }
  106. /**
  107. * drm_dp_link_update_rates() - normalize the supported link rates array
  108. * @link: the link for which to normalize the supported link rates
  109. *
  110. * Users should call this function after they've manually modified the array
  111. * of supported link rates. This function removes any stale entries, compacts
  112. * the array and updates the supported link rate count. Note that calling the
  113. * drm_dp_link_remove_rate() function already does this janitorial work.
  114. *
  115. * See also:
  116. * drm_dp_link_add_rate(), drm_dp_link_remove_rate()
  117. */
  118. void drm_dp_link_update_rates(struct drm_dp_link *link)
  119. {
  120. unsigned int i, count = 0;
  121. for (i = 0; i < link->num_rates; i++) {
  122. if (link->rates[i] != 0)
  123. link->rates[count++] = link->rates[i];
  124. }
  125. for (i = count; i < link->num_rates; i++)
  126. link->rates[i] = 0;
  127. link->num_rates = count;
  128. }
  129. /**
  130. * drm_dp_link_probe() - probe a DisplayPort link for capabilities
  131. * @aux: DisplayPort AUX channel
  132. * @link: pointer to structure in which to return link capabilities
  133. *
  134. * The structure filled in by this function can usually be passed directly
  135. * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
  136. * configure the link based on the link's capabilities.
  137. *
  138. * Returns 0 on success or a negative error code on failure.
  139. */
  140. int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
  141. {
  142. u8 dpcd[DP_RECEIVER_CAP_SIZE], value;
  143. unsigned int rd_interval;
  144. int err;
  145. drm_dp_link_reset(link);
  146. err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd));
  147. if (err < 0)
  148. return err;
  149. link->revision = dpcd[DP_DPCD_REV];
  150. link->max_rate = drm_dp_max_link_rate(dpcd);
  151. link->max_lanes = drm_dp_max_lane_count(dpcd);
  152. link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
  153. link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
  154. link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
  155. link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd);
  156. if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
  157. link->caps.alternate_scrambler_reset = true;
  158. err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value);
  159. if (err < 0)
  160. return err;
  161. if (value >= ARRAY_SIZE(drm_dp_edp_revisions))
  162. DRM_ERROR("unsupported eDP version: %02x\n", value);
  163. else
  164. link->edp = drm_dp_edp_revisions[value];
  165. }
  166. /*
  167. * The DPCD stores the AUX read interval in units of 4 ms. There are
  168. * two special cases:
  169. *
  170. * 1) if the TRAINING_AUX_RD_INTERVAL field is 0, the clock recovery
  171. * and channel equalization should use 100 us or 400 us AUX read
  172. * intervals, respectively
  173. *
  174. * 2) for DP v1.4 and above, clock recovery should always use 100 us
  175. * AUX read intervals
  176. */
  177. rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
  178. DP_TRAINING_AUX_RD_MASK;
  179. if (rd_interval > 4) {
  180. DRM_DEBUG_KMS("AUX interval %u out of range (max. 4)\n",
  181. rd_interval);
  182. rd_interval = 4;
  183. }
  184. rd_interval *= 4 * USEC_PER_MSEC;
  185. if (rd_interval == 0 || link->revision >= DP_DPCD_REV_14)
  186. link->aux_rd_interval.cr = 100;
  187. if (rd_interval == 0)
  188. link->aux_rd_interval.ce = 400;
  189. link->rate = link->max_rate;
  190. link->lanes = link->max_lanes;
  191. /* Parse SUPPORTED_LINK_RATES from eDP 1.4 */
  192. if (link->edp >= 0x14) {
  193. u8 supported_rates[DP_MAX_SUPPORTED_RATES * 2];
  194. unsigned int i;
  195. u16 rate;
  196. err = drm_dp_dpcd_read(aux, DP_SUPPORTED_LINK_RATES,
  197. supported_rates,
  198. sizeof(supported_rates));
  199. if (err < 0)
  200. return err;
  201. for (i = 0; i < DP_MAX_SUPPORTED_RATES; i++) {
  202. rate = supported_rates[i * 2 + 1] << 8 |
  203. supported_rates[i * 2 + 0];
  204. drm_dp_link_add_rate(link, rate * 200);
  205. }
  206. }
  207. return 0;
  208. }
  209. /**
  210. * drm_dp_link_power_up() - power up a DisplayPort link
  211. * @aux: DisplayPort AUX channel
  212. * @link: pointer to a structure containing the link configuration
  213. *
  214. * Returns 0 on success or a negative error code on failure.
  215. */
  216. int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
  217. {
  218. u8 value;
  219. int err;
  220. /* DP_SET_POWER register is only available on DPCD v1.1 and later */
  221. if (link->revision < 0x11)
  222. return 0;
  223. err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
  224. if (err < 0)
  225. return err;
  226. value &= ~DP_SET_POWER_MASK;
  227. value |= DP_SET_POWER_D0;
  228. err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
  229. if (err < 0)
  230. return err;
  231. /*
  232. * According to the DP 1.1 specification, a "Sink Device must exit the
  233. * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
  234. * Control Field" (register 0x600).
  235. */
  236. usleep_range(1000, 2000);
  237. return 0;
  238. }
  239. /**
  240. * drm_dp_link_power_down() - power down a DisplayPort link
  241. * @aux: DisplayPort AUX channel
  242. * @link: pointer to a structure containing the link configuration
  243. *
  244. * Returns 0 on success or a negative error code on failure.
  245. */
  246. int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
  247. {
  248. u8 value;
  249. int err;
  250. /* DP_SET_POWER register is only available on DPCD v1.1 and later */
  251. if (link->revision < 0x11)
  252. return 0;
  253. err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
  254. if (err < 0)
  255. return err;
  256. value &= ~DP_SET_POWER_MASK;
  257. value |= DP_SET_POWER_D3;
  258. err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
  259. if (err < 0)
  260. return err;
  261. return 0;
  262. }
  263. /**
  264. * drm_dp_link_configure() - configure a DisplayPort link
  265. * @aux: DisplayPort AUX channel
  266. * @link: pointer to a structure containing the link configuration
  267. *
  268. * Returns 0 on success or a negative error code on failure.
  269. */
  270. int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
  271. {
  272. u8 values[2], value;
  273. int err;
  274. if (link->ops && link->ops->configure) {
  275. err = link->ops->configure(link);
  276. if (err < 0) {
  277. DRM_ERROR("failed to configure DP link: %d\n", err);
  278. return err;
  279. }
  280. }
  281. values[0] = drm_dp_link_rate_to_bw_code(link->rate);
  282. values[1] = link->lanes;
  283. if (link->caps.enhanced_framing)
  284. values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  285. err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
  286. if (err < 0)
  287. return err;
  288. if (link->caps.channel_coding)
  289. value = DP_SET_ANSI_8B10B;
  290. else
  291. value = 0;
  292. err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value);
  293. if (err < 0)
  294. return err;
  295. if (link->caps.alternate_scrambler_reset) {
  296. err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET,
  297. DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
  298. if (err < 0)
  299. return err;
  300. }
  301. return 0;
  302. }
  303. /**
  304. * drm_dp_link_choose() - choose the lowest possible configuration for a mode
  305. * @link: DRM DP link object
  306. * @mode: DRM display mode
  307. * @info: DRM display information
  308. *
  309. * According to the eDP specification, a source should select a configuration
  310. * with the lowest number of lanes and the lowest possible link rate that can
  311. * match the bitrate requirements of a video mode. However it must ensure not
  312. * to exceed the capabilities of the sink.
  313. *
  314. * Returns: 0 on success or a negative error code on failure.
  315. */
  316. int drm_dp_link_choose(struct drm_dp_link *link,
  317. const struct drm_display_mode *mode,
  318. const struct drm_display_info *info)
  319. {
  320. /* available link symbol clock rates */
  321. static const unsigned int rates[3] = { 162000, 270000, 540000 };
  322. /* available number of lanes */
  323. static const unsigned int lanes[3] = { 1, 2, 4 };
  324. unsigned long requirement, capacity;
  325. unsigned int rate = link->max_rate;
  326. unsigned int i, j;
  327. /* bandwidth requirement */
  328. requirement = mode->clock * info->bpc * 3;
  329. for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) {
  330. for (j = 0; j < ARRAY_SIZE(rates) && rates[j] <= rate; j++) {
  331. /*
  332. * Capacity for this combination of lanes and rate,
  333. * factoring in the ANSI 8B/10B encoding.
  334. *
  335. * Link rates in the DRM DP helpers are really link
  336. * symbol frequencies, so a tenth of the actual rate
  337. * of the link.
  338. */
  339. capacity = lanes[i] * (rates[j] * 10) * 8 / 10;
  340. if (capacity >= requirement) {
  341. DRM_DEBUG_KMS("using %u lanes at %u kHz (%lu/%lu kbps)\n",
  342. lanes[i], rates[j], requirement,
  343. capacity);
  344. link->lanes = lanes[i];
  345. link->rate = rates[j];
  346. return 0;
  347. }
  348. }
  349. }
  350. return -ERANGE;
  351. }
  352. /**
  353. * DOC: Link training
  354. *
  355. * These functions contain common logic and helpers to implement DisplayPort
  356. * link training.
  357. */
  358. /**
  359. * drm_dp_link_train_init() - initialize DisplayPort link training state
  360. * @train: DisplayPort link training state
  361. */
  362. void drm_dp_link_train_init(struct drm_dp_link_train *train)
  363. {
  364. struct drm_dp_link_train_set *request = &train->request;
  365. struct drm_dp_link_train_set *adjust = &train->adjust;
  366. unsigned int i;
  367. for (i = 0; i < 4; i++) {
  368. request->voltage_swing[i] = 0;
  369. adjust->voltage_swing[i] = 0;
  370. request->pre_emphasis[i] = 0;
  371. adjust->pre_emphasis[i] = 0;
  372. request->post_cursor[i] = 0;
  373. adjust->post_cursor[i] = 0;
  374. }
  375. train->pattern = DP_TRAINING_PATTERN_DISABLE;
  376. train->clock_recovered = false;
  377. train->channel_equalized = false;
  378. }
  379. static bool drm_dp_link_train_valid(const struct drm_dp_link_train *train)
  380. {
  381. return train->clock_recovered && train->channel_equalized;
  382. }
  383. static int drm_dp_link_apply_training(struct drm_dp_link *link)
  384. {
  385. struct drm_dp_link_train_set *request = &link->train.request;
  386. unsigned int lanes = link->lanes, *vs, *pe, *pc, i;
  387. struct drm_dp_aux *aux = link->aux;
  388. u8 values[4], pattern = 0;
  389. int err;
  390. err = link->ops->apply_training(link);
  391. if (err < 0) {
  392. DRM_ERROR("failed to apply link training: %d\n", err);
  393. return err;
  394. }
  395. vs = request->voltage_swing;
  396. pe = request->pre_emphasis;
  397. pc = request->post_cursor;
  398. /* write currently selected voltage-swing and pre-emphasis levels */
  399. for (i = 0; i < lanes; i++)
  400. values[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL(vs[i]) |
  401. DP_TRAIN_PRE_EMPHASIS_LEVEL(pe[i]);
  402. err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, lanes);
  403. if (err < 0) {
  404. DRM_ERROR("failed to set training parameters: %d\n", err);
  405. return err;
  406. }
  407. /* write currently selected post-cursor level (if supported) */
  408. if (link->revision >= 0x12 && link->rate == 540000) {
  409. values[0] = values[1] = 0;
  410. for (i = 0; i < lanes; i++)
  411. values[i / 2] |= DP_LANE_POST_CURSOR(i, pc[i]);
  412. err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_1_SET2, values,
  413. DIV_ROUND_UP(lanes, 2));
  414. if (err < 0) {
  415. DRM_ERROR("failed to set post-cursor: %d\n", err);
  416. return err;
  417. }
  418. }
  419. /* write link pattern */
  420. if (link->train.pattern != DP_TRAINING_PATTERN_DISABLE)
  421. pattern |= DP_LINK_SCRAMBLING_DISABLE;
  422. pattern |= link->train.pattern;
  423. err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
  424. if (err < 0) {
  425. DRM_ERROR("failed to set training pattern: %d\n", err);
  426. return err;
  427. }
  428. return 0;
  429. }
  430. static void drm_dp_link_train_wait(struct drm_dp_link *link)
  431. {
  432. unsigned long min = 0;
  433. switch (link->train.pattern) {
  434. case DP_TRAINING_PATTERN_1:
  435. min = link->aux_rd_interval.cr;
  436. break;
  437. case DP_TRAINING_PATTERN_2:
  438. case DP_TRAINING_PATTERN_3:
  439. min = link->aux_rd_interval.ce;
  440. break;
  441. default:
  442. break;
  443. }
  444. if (min > 0)
  445. usleep_range(min, 2 * min);
  446. }
  447. static void drm_dp_link_get_adjustments(struct drm_dp_link *link,
  448. u8 status[DP_LINK_STATUS_SIZE])
  449. {
  450. struct drm_dp_link_train_set *adjust = &link->train.adjust;
  451. unsigned int i;
  452. for (i = 0; i < link->lanes; i++) {
  453. adjust->voltage_swing[i] =
  454. drm_dp_get_adjust_request_voltage(status, i) >>
  455. DP_TRAIN_VOLTAGE_SWING_SHIFT;
  456. adjust->pre_emphasis[i] =
  457. drm_dp_get_adjust_request_pre_emphasis(status, i) >>
  458. DP_TRAIN_PRE_EMPHASIS_SHIFT;
  459. adjust->post_cursor[i] =
  460. drm_dp_get_adjust_request_post_cursor(status, i);
  461. }
  462. }
  463. static void drm_dp_link_train_adjust(struct drm_dp_link_train *train)
  464. {
  465. struct drm_dp_link_train_set *request = &train->request;
  466. struct drm_dp_link_train_set *adjust = &train->adjust;
  467. unsigned int i;
  468. for (i = 0; i < 4; i++)
  469. if (request->voltage_swing[i] != adjust->voltage_swing[i])
  470. request->voltage_swing[i] = adjust->voltage_swing[i];
  471. for (i = 0; i < 4; i++)
  472. if (request->pre_emphasis[i] != adjust->pre_emphasis[i])
  473. request->pre_emphasis[i] = adjust->pre_emphasis[i];
  474. for (i = 0; i < 4; i++)
  475. if (request->post_cursor[i] != adjust->post_cursor[i])
  476. request->post_cursor[i] = adjust->post_cursor[i];
  477. }
  478. static int drm_dp_link_recover_clock(struct drm_dp_link *link)
  479. {
  480. u8 status[DP_LINK_STATUS_SIZE];
  481. int err;
  482. err = drm_dp_link_apply_training(link);
  483. if (err < 0)
  484. return err;
  485. drm_dp_link_train_wait(link);
  486. err = drm_dp_dpcd_read_link_status(link->aux, status);
  487. if (err < 0) {
  488. DRM_ERROR("failed to read link status: %d\n", err);
  489. return err;
  490. }
  491. if (!drm_dp_clock_recovery_ok(status, link->lanes))
  492. drm_dp_link_get_adjustments(link, status);
  493. else
  494. link->train.clock_recovered = true;
  495. return 0;
  496. }
  497. static int drm_dp_link_clock_recovery(struct drm_dp_link *link)
  498. {
  499. unsigned int repeat;
  500. int err;
  501. /* start clock recovery using training pattern 1 */
  502. link->train.pattern = DP_TRAINING_PATTERN_1;
  503. for (repeat = 1; repeat < 5; repeat++) {
  504. err = drm_dp_link_recover_clock(link);
  505. if (err < 0) {
  506. DRM_ERROR("failed to recover clock: %d\n", err);
  507. return err;
  508. }
  509. if (link->train.clock_recovered)
  510. break;
  511. drm_dp_link_train_adjust(&link->train);
  512. }
  513. return 0;
  514. }
  515. static int drm_dp_link_equalize_channel(struct drm_dp_link *link)
  516. {
  517. struct drm_dp_aux *aux = link->aux;
  518. u8 status[DP_LINK_STATUS_SIZE];
  519. int err;
  520. err = drm_dp_link_apply_training(link);
  521. if (err < 0)
  522. return err;
  523. drm_dp_link_train_wait(link);
  524. err = drm_dp_dpcd_read_link_status(aux, status);
  525. if (err < 0) {
  526. DRM_ERROR("failed to read link status: %d\n", err);
  527. return err;
  528. }
  529. if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
  530. DRM_ERROR("clock recovery lost while equalizing channel\n");
  531. link->train.clock_recovered = false;
  532. return 0;
  533. }
  534. if (!drm_dp_channel_eq_ok(status, link->lanes))
  535. drm_dp_link_get_adjustments(link, status);
  536. else
  537. link->train.channel_equalized = true;
  538. return 0;
  539. }
  540. static int drm_dp_link_channel_equalization(struct drm_dp_link *link)
  541. {
  542. unsigned int repeat;
  543. int err;
  544. /* start channel equalization using pattern 2 or 3 */
  545. if (link->caps.tps3_supported)
  546. link->train.pattern = DP_TRAINING_PATTERN_3;
  547. else
  548. link->train.pattern = DP_TRAINING_PATTERN_2;
  549. for (repeat = 1; repeat < 5; repeat++) {
  550. err = drm_dp_link_equalize_channel(link);
  551. if (err < 0) {
  552. DRM_ERROR("failed to equalize channel: %d\n", err);
  553. return err;
  554. }
  555. if (link->train.channel_equalized)
  556. break;
  557. drm_dp_link_train_adjust(&link->train);
  558. }
  559. return 0;
  560. }
  561. static int drm_dp_link_downgrade(struct drm_dp_link *link)
  562. {
  563. switch (link->rate) {
  564. case 162000:
  565. return -EINVAL;
  566. case 270000:
  567. link->rate = 162000;
  568. break;
  569. case 540000:
  570. link->rate = 270000;
  571. return 0;
  572. }
  573. return 0;
  574. }
  575. static void drm_dp_link_train_disable(struct drm_dp_link *link)
  576. {
  577. int err;
  578. link->train.pattern = DP_TRAINING_PATTERN_DISABLE;
  579. err = drm_dp_link_apply_training(link);
  580. if (err < 0)
  581. DRM_ERROR("failed to disable link training: %d\n", err);
  582. }
  583. static int drm_dp_link_train_full(struct drm_dp_link *link)
  584. {
  585. int err;
  586. retry:
  587. DRM_DEBUG_KMS("full-training link: %u lane%s at %u MHz\n",
  588. link->lanes, (link->lanes > 1) ? "s" : "",
  589. link->rate / 100);
  590. err = drm_dp_link_configure(link->aux, link);
  591. if (err < 0) {
  592. DRM_ERROR("failed to configure DP link: %d\n", err);
  593. return err;
  594. }
  595. err = drm_dp_link_clock_recovery(link);
  596. if (err < 0) {
  597. DRM_ERROR("clock recovery failed: %d\n", err);
  598. goto out;
  599. }
  600. if (!link->train.clock_recovered) {
  601. DRM_ERROR("clock recovery failed, downgrading link\n");
  602. err = drm_dp_link_downgrade(link);
  603. if (err < 0)
  604. goto out;
  605. goto retry;
  606. }
  607. DRM_DEBUG_KMS("clock recovery succeeded\n");
  608. err = drm_dp_link_channel_equalization(link);
  609. if (err < 0) {
  610. DRM_ERROR("channel equalization failed: %d\n", err);
  611. goto out;
  612. }
  613. if (!link->train.channel_equalized) {
  614. DRM_ERROR("channel equalization failed, downgrading link\n");
  615. err = drm_dp_link_downgrade(link);
  616. if (err < 0)
  617. goto out;
  618. goto retry;
  619. }
  620. DRM_DEBUG_KMS("channel equalization succeeded\n");
  621. out:
  622. drm_dp_link_train_disable(link);
  623. return err;
  624. }
  625. static int drm_dp_link_train_fast(struct drm_dp_link *link)
  626. {
  627. u8 status[DP_LINK_STATUS_SIZE];
  628. int err;
  629. DRM_DEBUG_KMS("fast-training link: %u lane%s at %u MHz\n",
  630. link->lanes, (link->lanes > 1) ? "s" : "",
  631. link->rate / 100);
  632. err = drm_dp_link_configure(link->aux, link);
  633. if (err < 0) {
  634. DRM_ERROR("failed to configure DP link: %d\n", err);
  635. return err;
  636. }
  637. /* transmit training pattern 1 for 500 microseconds */
  638. link->train.pattern = DP_TRAINING_PATTERN_1;
  639. err = drm_dp_link_apply_training(link);
  640. if (err < 0)
  641. goto out;
  642. usleep_range(500, 1000);
  643. /* transmit training pattern 2 or 3 for 500 microseconds */
  644. if (link->caps.tps3_supported)
  645. link->train.pattern = DP_TRAINING_PATTERN_3;
  646. else
  647. link->train.pattern = DP_TRAINING_PATTERN_2;
  648. err = drm_dp_link_apply_training(link);
  649. if (err < 0)
  650. goto out;
  651. usleep_range(500, 1000);
  652. err = drm_dp_dpcd_read_link_status(link->aux, status);
  653. if (err < 0) {
  654. DRM_ERROR("failed to read link status: %d\n", err);
  655. goto out;
  656. }
  657. if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
  658. DRM_ERROR("clock recovery failed\n");
  659. err = -EIO;
  660. }
  661. if (!drm_dp_channel_eq_ok(status, link->lanes)) {
  662. DRM_ERROR("channel equalization failed\n");
  663. err = -EIO;
  664. }
  665. out:
  666. drm_dp_link_train_disable(link);
  667. return err;
  668. }
  669. /**
  670. * drm_dp_link_train() - perform DisplayPort link training
  671. * @link: a DP link object
  672. *
  673. * Uses the context stored in the DP link object to perform link training. It
  674. * is expected that drivers will call drm_dp_link_probe() to obtain the link
  675. * capabilities before performing link training.
  676. *
  677. * If the sink supports fast link training (no AUX CH handshake) and valid
  678. * training settings are available, this function will try to perform fast
  679. * link training and fall back to full link training on failure.
  680. *
  681. * Returns: 0 on success or a negative error code on failure.
  682. */
  683. int drm_dp_link_train(struct drm_dp_link *link)
  684. {
  685. int err;
  686. drm_dp_link_train_init(&link->train);
  687. if (link->caps.fast_training) {
  688. if (drm_dp_link_train_valid(&link->train)) {
  689. err = drm_dp_link_train_fast(link);
  690. if (err < 0)
  691. DRM_ERROR("fast link training failed: %d\n",
  692. err);
  693. else
  694. return 0;
  695. } else {
  696. DRM_DEBUG_KMS("training parameters not available\n");
  697. }
  698. } else {
  699. DRM_DEBUG_KMS("fast link training not supported\n");
  700. }
  701. err = drm_dp_link_train_full(link);
  702. if (err < 0)
  703. DRM_ERROR("full link training failed: %d\n", err);
  704. return err;
  705. }