dc.h 25 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2012 Avionic Design GmbH
  4. * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  5. */
  6. #ifndef TEGRA_DC_H
  7. #define TEGRA_DC_H 1
  8. #include <linux/host1x.h>
  9. #include <drm/drm_crtc.h>
  10. #include "drm.h"
  11. struct tegra_output;
  12. struct tegra_dc_state {
  13. struct drm_crtc_state base;
  14. struct clk *clk;
  15. unsigned long pclk;
  16. unsigned int div;
  17. u32 planes;
  18. };
  19. static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  20. {
  21. if (state)
  22. return container_of(state, struct tegra_dc_state, base);
  23. return NULL;
  24. }
  25. struct tegra_dc_stats {
  26. unsigned long frames;
  27. unsigned long vblank;
  28. unsigned long underflow;
  29. unsigned long overflow;
  30. };
  31. struct tegra_windowgroup_soc {
  32. unsigned int index;
  33. unsigned int dc;
  34. const unsigned int *windows;
  35. unsigned int num_windows;
  36. };
  37. struct tegra_dc_soc_info {
  38. bool supports_background_color;
  39. bool supports_interlacing;
  40. bool supports_cursor;
  41. bool supports_block_linear;
  42. bool has_legacy_blending;
  43. unsigned int pitch_align;
  44. bool has_powergate;
  45. bool coupled_pm;
  46. bool has_nvdisplay;
  47. const struct tegra_windowgroup_soc *wgrps;
  48. unsigned int num_wgrps;
  49. const u32 *primary_formats;
  50. unsigned int num_primary_formats;
  51. const u32 *overlay_formats;
  52. unsigned int num_overlay_formats;
  53. const u64 *modifiers;
  54. bool has_win_a_without_filters;
  55. bool has_win_c_without_vert_filter;
  56. };
  57. struct tegra_dc {
  58. struct host1x_client client;
  59. struct host1x_syncpt *syncpt;
  60. struct device *dev;
  61. struct drm_crtc base;
  62. unsigned int powergate;
  63. int pipe;
  64. struct clk *clk;
  65. struct reset_control *rst;
  66. void __iomem *regs;
  67. int irq;
  68. struct tegra_output *rgb;
  69. struct tegra_dc_stats stats;
  70. struct list_head list;
  71. struct drm_info_list *debugfs_files;
  72. const struct tegra_dc_soc_info *soc;
  73. };
  74. static inline struct tegra_dc *
  75. host1x_client_to_dc(struct host1x_client *client)
  76. {
  77. return container_of(client, struct tegra_dc, client);
  78. }
  79. static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
  80. {
  81. return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
  82. }
  83. static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
  84. unsigned int offset)
  85. {
  86. trace_dc_writel(dc->dev, offset, value);
  87. writel(value, dc->regs + (offset << 2));
  88. }
  89. static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
  90. {
  91. u32 value = readl(dc->regs + (offset << 2));
  92. trace_dc_readl(dc->dev, offset, value);
  93. return value;
  94. }
  95. struct tegra_dc_window {
  96. struct {
  97. unsigned int x;
  98. unsigned int y;
  99. unsigned int w;
  100. unsigned int h;
  101. } src;
  102. struct {
  103. unsigned int x;
  104. unsigned int y;
  105. unsigned int w;
  106. unsigned int h;
  107. } dst;
  108. unsigned int bits_per_pixel;
  109. unsigned int stride[2];
  110. unsigned long base[3];
  111. unsigned int zpos;
  112. bool reflect_x;
  113. bool reflect_y;
  114. struct tegra_bo_tiling tiling;
  115. u32 format;
  116. u32 swap;
  117. };
  118. /* from dc.c */
  119. bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
  120. void tegra_dc_commit(struct tegra_dc *dc);
  121. int tegra_dc_state_setup_clock(struct tegra_dc *dc,
  122. struct drm_crtc_state *crtc_state,
  123. struct clk *clk, unsigned long pclk,
  124. unsigned int div);
  125. /* from rgb.c */
  126. int tegra_dc_rgb_probe(struct tegra_dc *dc);
  127. int tegra_dc_rgb_remove(struct tegra_dc *dc);
  128. int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
  129. int tegra_dc_rgb_exit(struct tegra_dc *dc);
  130. #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
  131. #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
  132. #define SYNCPT_CNTRL_NO_STALL (1 << 8)
  133. #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
  134. #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
  135. #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
  136. #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
  137. #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
  138. #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
  139. #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
  140. #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
  141. #define DC_CMD_WIN_C_INCR_SYNCPT 0x018
  142. #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
  143. #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
  144. #define DC_CMD_CONT_SYNCPT_VSYNC 0x028
  145. #define SYNCPT_VSYNC_ENABLE (1 << 8)
  146. #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
  147. #define DC_CMD_DISPLAY_COMMAND 0x032
  148. #define DISP_CTRL_MODE_STOP (0 << 5)
  149. #define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
  150. #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
  151. #define DISP_CTRL_MODE_MASK (3 << 5)
  152. #define DC_CMD_SIGNAL_RAISE 0x033
  153. #define DC_CMD_DISPLAY_POWER_CONTROL 0x036
  154. #define PW0_ENABLE (1 << 0)
  155. #define PW1_ENABLE (1 << 2)
  156. #define PW2_ENABLE (1 << 4)
  157. #define PW3_ENABLE (1 << 6)
  158. #define PW4_ENABLE (1 << 8)
  159. #define PM0_ENABLE (1 << 16)
  160. #define PM1_ENABLE (1 << 18)
  161. #define DC_CMD_INT_STATUS 0x037
  162. #define DC_CMD_INT_MASK 0x038
  163. #define DC_CMD_INT_ENABLE 0x039
  164. #define DC_CMD_INT_TYPE 0x03a
  165. #define DC_CMD_INT_POLARITY 0x03b
  166. #define CTXSW_INT (1 << 0)
  167. #define FRAME_END_INT (1 << 1)
  168. #define VBLANK_INT (1 << 2)
  169. #define V_PULSE3_INT (1 << 4)
  170. #define V_PULSE2_INT (1 << 5)
  171. #define REGION_CRC_INT (1 << 6)
  172. #define REG_TMOUT_INT (1 << 7)
  173. #define WIN_A_UF_INT (1 << 8)
  174. #define WIN_B_UF_INT (1 << 9)
  175. #define WIN_C_UF_INT (1 << 10)
  176. #define MSF_INT (1 << 12)
  177. #define WIN_A_OF_INT (1 << 14)
  178. #define WIN_B_OF_INT (1 << 15)
  179. #define WIN_C_OF_INT (1 << 16)
  180. #define HEAD_UF_INT (1 << 23)
  181. #define SD3_BUCKET_WALK_DONE_INT (1 << 24)
  182. #define DSC_OBUF_UF_INT (1 << 26)
  183. #define DSC_RBUF_UF_INT (1 << 27)
  184. #define DSC_BBUF_UF_INT (1 << 28)
  185. #define DSC_TO_UF_INT (1 << 29)
  186. #define DC_CMD_SIGNAL_RAISE1 0x03c
  187. #define DC_CMD_SIGNAL_RAISE2 0x03d
  188. #define DC_CMD_SIGNAL_RAISE3 0x03e
  189. #define DC_CMD_STATE_ACCESS 0x040
  190. #define READ_MUX (1 << 0)
  191. #define WRITE_MUX (1 << 2)
  192. #define DC_CMD_STATE_CONTROL 0x041
  193. #define GENERAL_ACT_REQ (1 << 0)
  194. #define WIN_A_ACT_REQ (1 << 1)
  195. #define WIN_B_ACT_REQ (1 << 2)
  196. #define WIN_C_ACT_REQ (1 << 3)
  197. #define CURSOR_ACT_REQ (1 << 7)
  198. #define GENERAL_UPDATE (1 << 8)
  199. #define WIN_A_UPDATE (1 << 9)
  200. #define WIN_B_UPDATE (1 << 10)
  201. #define WIN_C_UPDATE (1 << 11)
  202. #define CURSOR_UPDATE (1 << 15)
  203. #define COMMON_ACTREQ (1 << 16)
  204. #define COMMON_UPDATE (1 << 17)
  205. #define NC_HOST_TRIG (1 << 24)
  206. #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
  207. #define WINDOW_A_SELECT (1 << 4)
  208. #define WINDOW_B_SELECT (1 << 5)
  209. #define WINDOW_C_SELECT (1 << 6)
  210. #define DC_CMD_REG_ACT_CONTROL 0x043
  211. #define DC_COM_CRC_CONTROL 0x300
  212. #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
  213. #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
  214. #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
  215. #define DC_COM_CRC_CONTROL_WAIT (1 << 1)
  216. #define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
  217. #define DC_COM_CRC_CHECKSUM 0x301
  218. #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
  219. #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
  220. #define LVS_OUTPUT_POLARITY_LOW (1 << 28)
  221. #define LHS_OUTPUT_POLARITY_LOW (1 << 30)
  222. #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
  223. #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
  224. #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
  225. #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
  226. #define DC_COM_PIN_MISC_CONTROL 0x31b
  227. #define DC_COM_PIN_PM0_CONTROL 0x31c
  228. #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
  229. #define DC_COM_PIN_PM1_CONTROL 0x31e
  230. #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
  231. #define DC_COM_SPI_CONTROL 0x320
  232. #define DC_COM_SPI_START_BYTE 0x321
  233. #define DC_COM_HSPI_WRITE_DATA_AB 0x322
  234. #define DC_COM_HSPI_WRITE_DATA_CD 0x323
  235. #define DC_COM_HSPI_CS_DC 0x324
  236. #define DC_COM_SCRATCH_REGISTER_A 0x325
  237. #define DC_COM_SCRATCH_REGISTER_B 0x326
  238. #define DC_COM_GPIO_CTRL 0x327
  239. #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
  240. #define DC_COM_CRC_CHECKSUM_LATCHED 0x329
  241. #define DC_COM_RG_UNDERFLOW 0x365
  242. #define UNDERFLOW_MODE_RED (1 << 8)
  243. #define UNDERFLOW_REPORT_ENABLE (1 << 0)
  244. #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
  245. #define H_PULSE0_ENABLE (1 << 8)
  246. #define H_PULSE1_ENABLE (1 << 10)
  247. #define H_PULSE2_ENABLE (1 << 12)
  248. #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
  249. #define DC_DISP_DISP_WIN_OPTIONS 0x402
  250. #define HDMI_ENABLE (1 << 30)
  251. #define DSI_ENABLE (1 << 29)
  252. #define SOR1_TIMING_CYA (1 << 27)
  253. #define CURSOR_ENABLE (1 << 16)
  254. #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
  255. #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
  256. #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
  257. #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
  258. #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
  259. #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
  260. #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
  261. #define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
  262. #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
  263. #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
  264. #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
  265. #define DC_DISP_DISP_TIMING_OPTIONS 0x405
  266. #define VSYNC_H_POSITION(x) ((x) & 0xfff)
  267. #define DC_DISP_REF_TO_SYNC 0x406
  268. #define DC_DISP_SYNC_WIDTH 0x407
  269. #define DC_DISP_BACK_PORCH 0x408
  270. #define DC_DISP_ACTIVE 0x409
  271. #define DC_DISP_FRONT_PORCH 0x40a
  272. #define DC_DISP_H_PULSE0_CONTROL 0x40b
  273. #define DC_DISP_H_PULSE0_POSITION_A 0x40c
  274. #define DC_DISP_H_PULSE0_POSITION_B 0x40d
  275. #define DC_DISP_H_PULSE0_POSITION_C 0x40e
  276. #define DC_DISP_H_PULSE0_POSITION_D 0x40f
  277. #define DC_DISP_H_PULSE1_CONTROL 0x410
  278. #define DC_DISP_H_PULSE1_POSITION_A 0x411
  279. #define DC_DISP_H_PULSE1_POSITION_B 0x412
  280. #define DC_DISP_H_PULSE1_POSITION_C 0x413
  281. #define DC_DISP_H_PULSE1_POSITION_D 0x414
  282. #define DC_DISP_H_PULSE2_CONTROL 0x415
  283. #define DC_DISP_H_PULSE2_POSITION_A 0x416
  284. #define DC_DISP_H_PULSE2_POSITION_B 0x417
  285. #define DC_DISP_H_PULSE2_POSITION_C 0x418
  286. #define DC_DISP_H_PULSE2_POSITION_D 0x419
  287. #define DC_DISP_V_PULSE0_CONTROL 0x41a
  288. #define DC_DISP_V_PULSE0_POSITION_A 0x41b
  289. #define DC_DISP_V_PULSE0_POSITION_B 0x41c
  290. #define DC_DISP_V_PULSE0_POSITION_C 0x41d
  291. #define DC_DISP_V_PULSE1_CONTROL 0x41e
  292. #define DC_DISP_V_PULSE1_POSITION_A 0x41f
  293. #define DC_DISP_V_PULSE1_POSITION_B 0x420
  294. #define DC_DISP_V_PULSE1_POSITION_C 0x421
  295. #define DC_DISP_V_PULSE2_CONTROL 0x422
  296. #define DC_DISP_V_PULSE2_POSITION_A 0x423
  297. #define DC_DISP_V_PULSE3_CONTROL 0x424
  298. #define DC_DISP_V_PULSE3_POSITION_A 0x425
  299. #define DC_DISP_M0_CONTROL 0x426
  300. #define DC_DISP_M1_CONTROL 0x427
  301. #define DC_DISP_DI_CONTROL 0x428
  302. #define DC_DISP_PP_CONTROL 0x429
  303. #define DC_DISP_PP_SELECT_A 0x42a
  304. #define DC_DISP_PP_SELECT_B 0x42b
  305. #define DC_DISP_PP_SELECT_C 0x42c
  306. #define DC_DISP_PP_SELECT_D 0x42d
  307. #define PULSE_MODE_NORMAL (0 << 3)
  308. #define PULSE_MODE_ONE_CLOCK (1 << 3)
  309. #define PULSE_POLARITY_HIGH (0 << 4)
  310. #define PULSE_POLARITY_LOW (1 << 4)
  311. #define PULSE_QUAL_ALWAYS (0 << 6)
  312. #define PULSE_QUAL_VACTIVE (2 << 6)
  313. #define PULSE_QUAL_VACTIVE1 (3 << 6)
  314. #define PULSE_LAST_START_A (0 << 8)
  315. #define PULSE_LAST_END_A (1 << 8)
  316. #define PULSE_LAST_START_B (2 << 8)
  317. #define PULSE_LAST_END_B (3 << 8)
  318. #define PULSE_LAST_START_C (4 << 8)
  319. #define PULSE_LAST_END_C (5 << 8)
  320. #define PULSE_LAST_START_D (6 << 8)
  321. #define PULSE_LAST_END_D (7 << 8)
  322. #define PULSE_START(x) (((x) & 0xfff) << 0)
  323. #define PULSE_END(x) (((x) & 0xfff) << 16)
  324. #define DC_DISP_DISP_CLOCK_CONTROL 0x42e
  325. #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
  326. #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
  327. #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
  328. #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
  329. #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
  330. #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
  331. #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
  332. #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
  333. #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
  334. #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
  335. #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
  336. #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
  337. #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
  338. #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
  339. #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
  340. #define DISP_DATA_FORMAT_DF1P1C (0 << 0)
  341. #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
  342. #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
  343. #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
  344. #define DISP_DATA_FORMAT_DF2S (4 << 0)
  345. #define DISP_DATA_FORMAT_DF3S (5 << 0)
  346. #define DISP_DATA_FORMAT_DFSPI (6 << 0)
  347. #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
  348. #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
  349. #define DISP_ALIGNMENT_MSB (0 << 8)
  350. #define DISP_ALIGNMENT_LSB (1 << 8)
  351. #define DISP_ORDER_RED_BLUE (0 << 9)
  352. #define DISP_ORDER_BLUE_RED (1 << 9)
  353. #define DC_DISP_DISP_COLOR_CONTROL 0x430
  354. #define BASE_COLOR_SIZE666 ( 0 << 0)
  355. #define BASE_COLOR_SIZE111 ( 1 << 0)
  356. #define BASE_COLOR_SIZE222 ( 2 << 0)
  357. #define BASE_COLOR_SIZE333 ( 3 << 0)
  358. #define BASE_COLOR_SIZE444 ( 4 << 0)
  359. #define BASE_COLOR_SIZE555 ( 5 << 0)
  360. #define BASE_COLOR_SIZE565 ( 6 << 0)
  361. #define BASE_COLOR_SIZE332 ( 7 << 0)
  362. #define BASE_COLOR_SIZE888 ( 8 << 0)
  363. #define BASE_COLOR_SIZE101010 (10 << 0)
  364. #define BASE_COLOR_SIZE121212 (12 << 0)
  365. #define DITHER_CONTROL_MASK (3 << 8)
  366. #define DITHER_CONTROL_DISABLE (0 << 8)
  367. #define DITHER_CONTROL_ORDERED (2 << 8)
  368. #define DITHER_CONTROL_ERRDIFF (3 << 8)
  369. #define BASE_COLOR_SIZE_MASK (0xf << 0)
  370. #define BASE_COLOR_SIZE_666 ( 0 << 0)
  371. #define BASE_COLOR_SIZE_111 ( 1 << 0)
  372. #define BASE_COLOR_SIZE_222 ( 2 << 0)
  373. #define BASE_COLOR_SIZE_333 ( 3 << 0)
  374. #define BASE_COLOR_SIZE_444 ( 4 << 0)
  375. #define BASE_COLOR_SIZE_555 ( 5 << 0)
  376. #define BASE_COLOR_SIZE_565 ( 6 << 0)
  377. #define BASE_COLOR_SIZE_332 ( 7 << 0)
  378. #define BASE_COLOR_SIZE_888 ( 8 << 0)
  379. #define BASE_COLOR_SIZE_101010 ( 10 << 0)
  380. #define BASE_COLOR_SIZE_121212 ( 12 << 0)
  381. #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
  382. #define SC1_H_QUALIFIER_NONE (1 << 16)
  383. #define SC0_H_QUALIFIER_NONE (1 << 0)
  384. #define DC_DISP_DATA_ENABLE_OPTIONS 0x432
  385. #define DE_SELECT_ACTIVE_BLANK (0 << 0)
  386. #define DE_SELECT_ACTIVE (1 << 0)
  387. #define DE_SELECT_ACTIVE_IS (2 << 0)
  388. #define DE_CONTROL_ONECLK (0 << 2)
  389. #define DE_CONTROL_NORMAL (1 << 2)
  390. #define DE_CONTROL_EARLY_EXT (2 << 2)
  391. #define DE_CONTROL_EARLY (3 << 2)
  392. #define DE_CONTROL_ACTIVE_BLANK (4 << 2)
  393. #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
  394. #define DC_DISP_LCD_SPI_OPTIONS 0x434
  395. #define DC_DISP_BORDER_COLOR 0x435
  396. #define DC_DISP_COLOR_KEY0_LOWER 0x436
  397. #define DC_DISP_COLOR_KEY0_UPPER 0x437
  398. #define DC_DISP_COLOR_KEY1_LOWER 0x438
  399. #define DC_DISP_COLOR_KEY1_UPPER 0x439
  400. #define DC_DISP_CURSOR_FOREGROUND 0x43c
  401. #define DC_DISP_CURSOR_BACKGROUND 0x43d
  402. #define DC_DISP_CURSOR_START_ADDR 0x43e
  403. #define CURSOR_CLIP_DISPLAY (0 << 28)
  404. #define CURSOR_CLIP_WIN_A (1 << 28)
  405. #define CURSOR_CLIP_WIN_B (2 << 28)
  406. #define CURSOR_CLIP_WIN_C (3 << 28)
  407. #define CURSOR_SIZE_32x32 (0 << 24)
  408. #define CURSOR_SIZE_64x64 (1 << 24)
  409. #define CURSOR_SIZE_128x128 (2 << 24)
  410. #define CURSOR_SIZE_256x256 (3 << 24)
  411. #define DC_DISP_CURSOR_START_ADDR_NS 0x43f
  412. #define DC_DISP_CURSOR_POSITION 0x440
  413. #define DC_DISP_CURSOR_POSITION_NS 0x441
  414. #define DC_DISP_INIT_SEQ_CONTROL 0x442
  415. #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
  416. #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
  417. #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
  418. #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
  419. #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
  420. #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
  421. #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
  422. #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
  423. #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
  424. #define DC_DISP_DAC_CRT_CTRL 0x4c0
  425. #define DC_DISP_DISP_MISC_CONTROL 0x4c1
  426. #define DC_DISP_SD_CONTROL 0x4c2
  427. #define DC_DISP_SD_CSC_COEFF 0x4c3
  428. #define DC_DISP_SD_LUT(x) (0x4c4 + (x))
  429. #define DC_DISP_SD_FLICKER_CONTROL 0x4cd
  430. #define DC_DISP_DC_PIXEL_COUNT 0x4ce
  431. #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
  432. #define DC_DISP_SD_BL_PARAMETERS 0x4d7
  433. #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
  434. #define DC_DISP_SD_BL_CONTROL 0x4dc
  435. #define DC_DISP_SD_HW_K_VALUES 0x4dd
  436. #define DC_DISP_SD_MAN_K_VALUES 0x4de
  437. #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
  438. #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
  439. #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
  440. #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
  441. #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
  442. #define DC_DISP_INTERLACE_CONTROL 0x4e5
  443. #define INTERLACE_STATUS (1 << 2)
  444. #define INTERLACE_START (1 << 1)
  445. #define INTERLACE_ENABLE (1 << 0)
  446. #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
  447. #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
  448. #define CURSOR_MODE_LEGACY (0 << 24)
  449. #define CURSOR_MODE_NORMAL (1 << 24)
  450. #define CURSOR_DST_BLEND_ZERO (0 << 16)
  451. #define CURSOR_DST_BLEND_K1 (1 << 16)
  452. #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
  453. #define CURSOR_DST_BLEND_MASK (3 << 16)
  454. #define CURSOR_SRC_BLEND_K1 (0 << 8)
  455. #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
  456. #define CURSOR_SRC_BLEND_MASK (3 << 8)
  457. #define CURSOR_ALPHA 0xff
  458. #define DC_WIN_CORE_ACT_CONTROL 0x50e
  459. #define VCOUNTER (0 << 0)
  460. #define HCOUNTER (1 << 0)
  461. #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
  462. #define LATENCY_CTL_MODE_ENABLE (1 << 2)
  463. #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
  464. #define WATERMARK_MASK 0x1fffffff
  465. #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
  466. #define PIPE_METER_INT(x) (((x) & 0xff) << 8)
  467. #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
  468. #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
  469. #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
  470. #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
  471. #define SLOTS(x) (((x) & 0xff) << 0)
  472. #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
  473. #define MODE_TWO_LINES (0 << 14)
  474. #define MODE_FOUR_LINES (1 << 14)
  475. #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
  476. #define THREAD_NUM_MASK (0x1f << 1)
  477. #define THREAD_NUM(x) (((x) & 0x1f) << 1)
  478. #define THREAD_GROUP_ENABLE (1 << 0)
  479. #define DC_WIN_H_FILTER_P(p) (0x601 + (p))
  480. #define DC_WIN_V_FILTER_P(p) (0x619 + (p))
  481. #define DC_WIN_CSC_YOF 0x611
  482. #define DC_WIN_CSC_KYRGB 0x612
  483. #define DC_WIN_CSC_KUR 0x613
  484. #define DC_WIN_CSC_KVR 0x614
  485. #define DC_WIN_CSC_KUG 0x615
  486. #define DC_WIN_CSC_KVG 0x616
  487. #define DC_WIN_CSC_KUB 0x617
  488. #define DC_WIN_CSC_KVB 0x618
  489. #define DC_WIN_WIN_OPTIONS 0x700
  490. #define H_DIRECTION (1 << 0)
  491. #define V_DIRECTION (1 << 2)
  492. #define COLOR_EXPAND (1 << 6)
  493. #define H_FILTER (1 << 8)
  494. #define V_FILTER (1 << 10)
  495. #define CSC_ENABLE (1 << 18)
  496. #define WIN_ENABLE (1 << 30)
  497. #define DC_WIN_BYTE_SWAP 0x701
  498. #define BYTE_SWAP_NOSWAP (0 << 0)
  499. #define BYTE_SWAP_SWAP2 (1 << 0)
  500. #define BYTE_SWAP_SWAP4 (2 << 0)
  501. #define BYTE_SWAP_SWAP4HW (3 << 0)
  502. #define DC_WIN_BUFFER_CONTROL 0x702
  503. #define BUFFER_CONTROL_HOST (0 << 0)
  504. #define BUFFER_CONTROL_VI (1 << 0)
  505. #define BUFFER_CONTROL_EPP (2 << 0)
  506. #define BUFFER_CONTROL_MPEGE (3 << 0)
  507. #define BUFFER_CONTROL_SB2D (4 << 0)
  508. #define DC_WIN_COLOR_DEPTH 0x703
  509. #define WIN_COLOR_DEPTH_P1 0
  510. #define WIN_COLOR_DEPTH_P2 1
  511. #define WIN_COLOR_DEPTH_P4 2
  512. #define WIN_COLOR_DEPTH_P8 3
  513. #define WIN_COLOR_DEPTH_B4G4R4A4 4
  514. #define WIN_COLOR_DEPTH_B5G5R5A1 5
  515. #define WIN_COLOR_DEPTH_B5G6R5 6
  516. #define WIN_COLOR_DEPTH_A1B5G5R5 7
  517. #define WIN_COLOR_DEPTH_B8G8R8A8 12
  518. #define WIN_COLOR_DEPTH_R8G8B8A8 13
  519. #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
  520. #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
  521. #define WIN_COLOR_DEPTH_YCbCr422 16
  522. #define WIN_COLOR_DEPTH_YUV422 17
  523. #define WIN_COLOR_DEPTH_YCbCr420P 18
  524. #define WIN_COLOR_DEPTH_YUV420P 19
  525. #define WIN_COLOR_DEPTH_YCbCr422P 20
  526. #define WIN_COLOR_DEPTH_YUV422P 21
  527. #define WIN_COLOR_DEPTH_YCbCr422R 22
  528. #define WIN_COLOR_DEPTH_YUV422R 23
  529. #define WIN_COLOR_DEPTH_YCbCr422RA 24
  530. #define WIN_COLOR_DEPTH_YUV422RA 25
  531. #define WIN_COLOR_DEPTH_R4G4B4A4 27
  532. #define WIN_COLOR_DEPTH_R5G5B5A 28
  533. #define WIN_COLOR_DEPTH_AR5G5B5 29
  534. #define WIN_COLOR_DEPTH_B5G5R5X1 30
  535. #define WIN_COLOR_DEPTH_X1B5G5R5 31
  536. #define WIN_COLOR_DEPTH_R5G5B5X1 32
  537. #define WIN_COLOR_DEPTH_X1R5G5B5 33
  538. #define WIN_COLOR_DEPTH_R5G6B5 34
  539. #define WIN_COLOR_DEPTH_A8R8G8B8 35
  540. #define WIN_COLOR_DEPTH_A8B8G8R8 36
  541. #define WIN_COLOR_DEPTH_B8G8R8X8 37
  542. #define WIN_COLOR_DEPTH_R8G8B8X8 38
  543. #define WIN_COLOR_DEPTH_X8B8G8R8 65
  544. #define WIN_COLOR_DEPTH_X8R8G8B8 66
  545. #define DC_WIN_POSITION 0x704
  546. #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
  547. #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
  548. #define DC_WIN_SIZE 0x705
  549. #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
  550. #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
  551. #define DC_WIN_PRESCALED_SIZE 0x706
  552. #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
  553. #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
  554. #define DC_WIN_H_INITIAL_DDA 0x707
  555. #define DC_WIN_V_INITIAL_DDA 0x708
  556. #define DC_WIN_DDA_INC 0x709
  557. #define H_DDA_INC(x) (((x) & 0xffff) << 0)
  558. #define V_DDA_INC(x) (((x) & 0xffff) << 16)
  559. #define DC_WIN_LINE_STRIDE 0x70a
  560. #define DC_WIN_BUF_STRIDE 0x70b
  561. #define DC_WIN_UV_BUF_STRIDE 0x70c
  562. #define DC_WIN_BUFFER_ADDR_MODE 0x70d
  563. #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
  564. #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
  565. #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
  566. #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
  567. #define DC_WIN_DV_CONTROL 0x70e
  568. #define DC_WIN_BLEND_NOKEY 0x70f
  569. #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
  570. #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
  571. #define DC_WIN_BLEND_1WIN 0x710
  572. #define BLEND_CONTROL_FIX (0 << 2)
  573. #define BLEND_CONTROL_ALPHA (1 << 2)
  574. #define BLEND_COLOR_KEY_NONE (0 << 0)
  575. #define BLEND_COLOR_KEY_0 (1 << 0)
  576. #define BLEND_COLOR_KEY_1 (2 << 0)
  577. #define BLEND_COLOR_KEY_BOTH (3 << 0)
  578. #define DC_WIN_BLEND_2WIN_X 0x711
  579. #define BLEND_CONTROL_DEPENDENT (2 << 2)
  580. #define DC_WIN_BLEND_2WIN_Y 0x712
  581. #define DC_WIN_BLEND_3WIN_XY 0x713
  582. #define DC_WIN_HP_FETCH_CONTROL 0x714
  583. #define DC_WINBUF_START_ADDR 0x800
  584. #define DC_WINBUF_START_ADDR_NS 0x801
  585. #define DC_WINBUF_START_ADDR_U 0x802
  586. #define DC_WINBUF_START_ADDR_U_NS 0x803
  587. #define DC_WINBUF_START_ADDR_V 0x804
  588. #define DC_WINBUF_START_ADDR_V_NS 0x805
  589. #define DC_WINBUF_ADDR_H_OFFSET 0x806
  590. #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
  591. #define DC_WINBUF_ADDR_V_OFFSET 0x808
  592. #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
  593. #define DC_WINBUF_UFLOW_STATUS 0x80a
  594. #define DC_WINBUF_SURFACE_KIND 0x80b
  595. #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
  596. #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
  597. #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
  598. #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
  599. #define DC_WINBUF_START_ADDR_HI 0x80d
  600. #define DC_WINBUF_CDE_CONTROL 0x82f
  601. #define ENABLE_SURFACE (1 << 0)
  602. #define DC_WINBUF_AD_UFLOW_STATUS 0xbca
  603. #define DC_WINBUF_BD_UFLOW_STATUS 0xdca
  604. #define DC_WINBUF_CD_UFLOW_STATUS 0xfca
  605. /* Tegra186 and later */
  606. #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
  607. #define PROTOCOL_MASK (0xf << 8)
  608. #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
  609. #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
  610. #define OWNER_MASK (0xf << 0)
  611. #define OWNER(x) (((x) & 0xf) << 0)
  612. #define DC_WIN_CROPPED_SIZE 0x706
  613. #define DC_WIN_PLANAR_STORAGE 0x709
  614. #define PITCH(x) (((x) >> 6) & 0x1fff)
  615. #define DC_WIN_SET_PARAMS 0x70d
  616. #define CLAMP_BEFORE_BLEND (1 << 15)
  617. #define DEGAMMA_NONE (0 << 13)
  618. #define DEGAMMA_SRGB (1 << 13)
  619. #define DEGAMMA_YUV8_10 (2 << 13)
  620. #define DEGAMMA_YUV12 (3 << 13)
  621. #define INPUT_RANGE_BYPASS (0 << 10)
  622. #define INPUT_RANGE_LIMITED (1 << 10)
  623. #define INPUT_RANGE_FULL (2 << 10)
  624. #define COLOR_SPACE_RGB (0 << 8)
  625. #define COLOR_SPACE_YUV_601 (1 << 8)
  626. #define COLOR_SPACE_YUV_709 (2 << 8)
  627. #define COLOR_SPACE_YUV_2020 (3 << 8)
  628. #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
  629. #define HORIZONTAL_TAPS_2 (1 << 3)
  630. #define HORIZONTAL_TAPS_5 (4 << 3)
  631. #define VERTICAL_TAPS_2 (1 << 0)
  632. #define VERTICAL_TAPS_5 (4 << 0)
  633. #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
  634. #define INPUT_SCALER_USE422 (1 << 2)
  635. #define INPUT_SCALER_VBYPASS (1 << 1)
  636. #define INPUT_SCALER_HBYPASS (1 << 0)
  637. #define DC_WIN_BLEND_LAYER_CONTROL 0x716
  638. #define COLOR_KEY_NONE (0 << 25)
  639. #define COLOR_KEY_SRC (1 << 25)
  640. #define COLOR_KEY_DST (2 << 25)
  641. #define BLEND_BYPASS (1 << 24)
  642. #define K2(x) (((x) & 0xff) << 16)
  643. #define K1(x) (((x) & 0xff) << 8)
  644. #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
  645. #define DC_WIN_BLEND_MATCH_SELECT 0x717
  646. #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
  647. #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
  648. #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
  649. #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
  650. #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
  651. #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
  652. #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
  653. #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
  654. #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
  655. #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
  656. #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
  657. #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
  658. #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
  659. #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
  660. #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
  661. #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
  662. #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
  663. #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
  664. #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
  665. #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
  666. #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
  667. #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
  668. #define DC_WIN_BLEND_NOMATCH_SELECT 0x718
  669. #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
  670. #define SWAP_UV (1 << 0)
  671. #define DC_WIN_WINDOW_SET_CONTROL 0x730
  672. #define CONTROL_CSC_ENABLE (1 << 5)
  673. #define DC_WINBUF_CROPPED_POINT 0x806
  674. #define OFFSET_Y(x) (((x) & 0xffff) << 16)
  675. #define OFFSET_X(x) (((x) & 0xffff) << 0)
  676. #endif /* TEGRA_DC_H */