sun8i_hdmi_phy_clk.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
  4. */
  5. #include <linux/clk-provider.h>
  6. #include "sun8i_dw_hdmi.h"
  7. struct sun8i_phy_clk {
  8. struct clk_hw hw;
  9. struct sun8i_hdmi_phy *phy;
  10. };
  11. static inline struct sun8i_phy_clk *hw_to_phy_clk(struct clk_hw *hw)
  12. {
  13. return container_of(hw, struct sun8i_phy_clk, hw);
  14. }
  15. static int sun8i_phy_clk_determine_rate(struct clk_hw *hw,
  16. struct clk_rate_request *req)
  17. {
  18. unsigned long rate = req->rate;
  19. unsigned long best_rate = 0;
  20. struct clk_hw *best_parent = NULL;
  21. struct clk_hw *parent;
  22. int best_div = 1;
  23. int i, p;
  24. for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
  25. parent = clk_hw_get_parent_by_index(hw, p);
  26. if (!parent)
  27. continue;
  28. for (i = 1; i <= 16; i++) {
  29. unsigned long ideal = rate * i;
  30. unsigned long rounded;
  31. rounded = clk_hw_round_rate(parent, ideal);
  32. if (rounded == ideal) {
  33. best_rate = rounded;
  34. best_div = i;
  35. best_parent = parent;
  36. break;
  37. }
  38. if (!best_rate ||
  39. abs(rate - rounded / i) <
  40. abs(rate - best_rate / best_div)) {
  41. best_rate = rounded;
  42. best_div = i;
  43. best_parent = parent;
  44. }
  45. }
  46. if (best_rate / best_div == rate)
  47. break;
  48. }
  49. req->rate = best_rate / best_div;
  50. req->best_parent_rate = best_rate;
  51. req->best_parent_hw = best_parent;
  52. return 0;
  53. }
  54. static unsigned long sun8i_phy_clk_recalc_rate(struct clk_hw *hw,
  55. unsigned long parent_rate)
  56. {
  57. struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
  58. u32 reg;
  59. regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, &reg);
  60. reg = ((reg >> SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT) &
  61. SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK) + 1;
  62. return parent_rate / reg;
  63. }
  64. static int sun8i_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  65. unsigned long parent_rate)
  66. {
  67. struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
  68. unsigned long best_rate = 0;
  69. u8 best_m = 0, m;
  70. for (m = 1; m <= 16; m++) {
  71. unsigned long tmp_rate = parent_rate / m;
  72. if (tmp_rate > rate)
  73. continue;
  74. if (!best_rate ||
  75. (rate - tmp_rate) < (rate - best_rate)) {
  76. best_rate = tmp_rate;
  77. best_m = m;
  78. }
  79. }
  80. regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
  81. SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
  82. SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(best_m));
  83. return 0;
  84. }
  85. static u8 sun8i_phy_clk_get_parent(struct clk_hw *hw)
  86. {
  87. struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
  88. u32 reg;
  89. regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, &reg);
  90. reg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>
  91. SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT;
  92. return reg;
  93. }
  94. static int sun8i_phy_clk_set_parent(struct clk_hw *hw, u8 index)
  95. {
  96. struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
  97. if (index > 1)
  98. return -EINVAL;
  99. regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
  100. SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
  101. index << SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT);
  102. return 0;
  103. }
  104. static const struct clk_ops sun8i_phy_clk_ops = {
  105. .determine_rate = sun8i_phy_clk_determine_rate,
  106. .recalc_rate = sun8i_phy_clk_recalc_rate,
  107. .set_rate = sun8i_phy_clk_set_rate,
  108. .get_parent = sun8i_phy_clk_get_parent,
  109. .set_parent = sun8i_phy_clk_set_parent,
  110. };
  111. int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
  112. bool second_parent)
  113. {
  114. struct clk_init_data init;
  115. struct sun8i_phy_clk *priv;
  116. const char *parents[2];
  117. parents[0] = __clk_get_name(phy->clk_pll0);
  118. if (!parents[0])
  119. return -ENODEV;
  120. if (second_parent) {
  121. parents[1] = __clk_get_name(phy->clk_pll1);
  122. if (!parents[1])
  123. return -ENODEV;
  124. }
  125. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  126. if (!priv)
  127. return -ENOMEM;
  128. init.name = "hdmi-phy-clk";
  129. init.ops = &sun8i_phy_clk_ops;
  130. init.parent_names = parents;
  131. init.num_parents = second_parent ? 2 : 1;
  132. init.flags = CLK_SET_RATE_PARENT;
  133. priv->phy = phy;
  134. priv->hw.init = &init;
  135. phy->clk_phy = devm_clk_register(dev, &priv->hw);
  136. if (IS_ERR(phy->clk_phy))
  137. return PTR_ERR(phy->clk_phy);
  138. return 0;
  139. }