sun8i_hdmi_phy.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
  4. */
  5. #include <linux/delay.h>
  6. #include <linux/of_address.h>
  7. #include <linux/of_platform.h>
  8. #include "sun8i_dw_hdmi.h"
  9. /*
  10. * Address can be actually any value. Here is set to same value as
  11. * it is set in BSP driver.
  12. */
  13. #define I2C_ADDR 0x69
  14. static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = {
  15. {
  16. 30666000, {
  17. { 0x00b3, 0x0000 },
  18. { 0x2153, 0x0000 },
  19. { 0x40f3, 0x0000 },
  20. },
  21. }, {
  22. 36800000, {
  23. { 0x00b3, 0x0000 },
  24. { 0x2153, 0x0000 },
  25. { 0x40a2, 0x0001 },
  26. },
  27. }, {
  28. 46000000, {
  29. { 0x00b3, 0x0000 },
  30. { 0x2142, 0x0001 },
  31. { 0x40a2, 0x0001 },
  32. },
  33. }, {
  34. 61333000, {
  35. { 0x0072, 0x0001 },
  36. { 0x2142, 0x0001 },
  37. { 0x40a2, 0x0001 },
  38. },
  39. }, {
  40. 73600000, {
  41. { 0x0072, 0x0001 },
  42. { 0x2142, 0x0001 },
  43. { 0x4061, 0x0002 },
  44. },
  45. }, {
  46. 92000000, {
  47. { 0x0072, 0x0001 },
  48. { 0x2145, 0x0002 },
  49. { 0x4061, 0x0002 },
  50. },
  51. }, {
  52. 122666000, {
  53. { 0x0051, 0x0002 },
  54. { 0x2145, 0x0002 },
  55. { 0x4061, 0x0002 },
  56. },
  57. }, {
  58. 147200000, {
  59. { 0x0051, 0x0002 },
  60. { 0x2145, 0x0002 },
  61. { 0x4064, 0x0003 },
  62. },
  63. }, {
  64. 184000000, {
  65. { 0x0051, 0x0002 },
  66. { 0x214c, 0x0003 },
  67. { 0x4064, 0x0003 },
  68. },
  69. }, {
  70. 226666000, {
  71. { 0x0040, 0x0003 },
  72. { 0x214c, 0x0003 },
  73. { 0x4064, 0x0003 },
  74. },
  75. }, {
  76. 272000000, {
  77. { 0x0040, 0x0003 },
  78. { 0x214c, 0x0003 },
  79. { 0x5a64, 0x0003 },
  80. },
  81. }, {
  82. 340000000, {
  83. { 0x0040, 0x0003 },
  84. { 0x3b4c, 0x0003 },
  85. { 0x5a64, 0x0003 },
  86. },
  87. }, {
  88. 594000000, {
  89. { 0x1a40, 0x0003 },
  90. { 0x3b4c, 0x0003 },
  91. { 0x5a64, 0x0003 },
  92. },
  93. }, {
  94. ~0UL, {
  95. { 0x0000, 0x0000 },
  96. { 0x0000, 0x0000 },
  97. { 0x0000, 0x0000 },
  98. },
  99. }
  100. };
  101. static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = {
  102. /* pixelclk bpp8 bpp10 bpp12 */
  103. { 27000000, { 0x0012, 0x0000, 0x0000 }, },
  104. { 74250000, { 0x0013, 0x001a, 0x001b }, },
  105. { 148500000, { 0x0019, 0x0033, 0x0034 }, },
  106. { 297000000, { 0x0019, 0x001b, 0x001b }, },
  107. { 594000000, { 0x0010, 0x001b, 0x001b }, },
  108. { ~0UL, { 0x0000, 0x0000, 0x0000 }, }
  109. };
  110. static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
  111. /*pixelclk symbol term vlev*/
  112. { 27000000, 0x8009, 0x0007, 0x02b0 },
  113. { 74250000, 0x8009, 0x0006, 0x022d },
  114. { 148500000, 0x8029, 0x0006, 0x0270 },
  115. { 297000000, 0x8039, 0x0005, 0x01ab },
  116. { 594000000, 0x8029, 0x0000, 0x008a },
  117. { ~0UL, 0x0000, 0x0000, 0x0000}
  118. };
  119. static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
  120. struct sun8i_hdmi_phy *phy,
  121. unsigned int clk_rate)
  122. {
  123. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
  124. SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
  125. SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
  126. /* power down */
  127. dw_hdmi_phy_gen2_txpwron(hdmi, 0);
  128. dw_hdmi_phy_gen2_pddq(hdmi, 1);
  129. dw_hdmi_phy_reset(hdmi);
  130. dw_hdmi_phy_gen2_pddq(hdmi, 0);
  131. dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
  132. /*
  133. * Values are taken from BSP HDMI driver. Although AW didn't
  134. * release any documentation, explanation of this values can
  135. * be found in i.MX 6Dual/6Quad Reference Manual.
  136. */
  137. if (clk_rate <= 27000000) {
  138. dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
  139. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
  140. dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
  141. dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
  142. dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
  143. dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
  144. } else if (clk_rate <= 74250000) {
  145. dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
  146. dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
  147. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
  148. dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
  149. dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
  150. dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
  151. } else if (clk_rate <= 148500000) {
  152. dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
  153. dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
  154. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
  155. dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
  156. dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
  157. dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
  158. } else {
  159. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
  160. dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
  161. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
  162. dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
  163. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
  164. dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
  165. }
  166. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
  167. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
  168. dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
  169. dw_hdmi_phy_gen2_txpwron(hdmi, 1);
  170. return 0;
  171. }
  172. static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
  173. struct sun8i_hdmi_phy *phy,
  174. unsigned int clk_rate)
  175. {
  176. u32 pll_cfg1_init;
  177. u32 pll_cfg2_init;
  178. u32 ana_cfg1_end;
  179. u32 ana_cfg2_init;
  180. u32 ana_cfg3_init;
  181. u32 b_offset = 0;
  182. u32 val;
  183. /* bandwidth / frequency independent settings */
  184. pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN |
  185. SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN |
  186. SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) |
  187. SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) |
  188. SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN |
  189. SUN8I_HDMI_PHY_PLL_CFG1_CS |
  190. SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) |
  191. SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) |
  192. SUN8I_HDMI_PHY_PLL_CFG1_BWS;
  193. pll_cfg2_init = SUN8I_HDMI_PHY_PLL_CFG2_SV_H |
  194. SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN |
  195. SUN8I_HDMI_PHY_PLL_CFG2_SDIV2;
  196. ana_cfg1_end = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) |
  197. SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT |
  198. SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT |
  199. SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT |
  200. SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT |
  201. SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL |
  202. SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG |
  203. SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS |
  204. SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN |
  205. SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK |
  206. SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL |
  207. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK |
  208. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
  209. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
  210. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
  211. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 |
  212. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
  213. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
  214. SUN8I_HDMI_PHY_ANA_CFG1_CKEN |
  215. SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
  216. SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
  217. SUN8I_HDMI_PHY_ANA_CFG1_ENBI;
  218. ana_cfg2_init = SUN8I_HDMI_PHY_ANA_CFG2_M_EN |
  219. SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK |
  220. SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN |
  221. SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) |
  222. SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1);
  223. ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) |
  224. SUN8I_HDMI_PHY_ANA_CFG3_SDAEN |
  225. SUN8I_HDMI_PHY_ANA_CFG3_SCLEN;
  226. /* bandwidth / frequency dependent settings */
  227. if (clk_rate <= 27000000) {
  228. pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
  229. SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
  230. pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
  231. SUN8I_HDMI_PHY_PLL_CFG2_S(4);
  232. ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
  233. ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
  234. SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
  235. ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) |
  236. SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5);
  237. } else if (clk_rate <= 74250000) {
  238. pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
  239. SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
  240. pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
  241. SUN8I_HDMI_PHY_PLL_CFG2_S(5);
  242. ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
  243. ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
  244. SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
  245. ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) |
  246. SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7);
  247. } else if (clk_rate <= 148500000) {
  248. pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
  249. SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
  250. pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
  251. SUN8I_HDMI_PHY_PLL_CFG2_S(6);
  252. ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
  253. SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
  254. SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2);
  255. ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) |
  256. SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9);
  257. } else {
  258. b_offset = 2;
  259. pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63);
  260. pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) |
  261. SUN8I_HDMI_PHY_PLL_CFG2_S(7);
  262. ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
  263. SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
  264. SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
  265. ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
  266. SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
  267. SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
  268. }
  269. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  270. SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
  271. /*
  272. * NOTE: We have to be careful not to overwrite PHY parent
  273. * clock selection bit and clock divider.
  274. */
  275. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
  276. (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
  277. pll_cfg1_init);
  278. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
  279. (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
  280. pll_cfg2_init);
  281. usleep_range(10000, 15000);
  282. regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG,
  283. SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2);
  284. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
  285. SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,
  286. SUN8I_HDMI_PHY_PLL_CFG1_PLLEN);
  287. msleep(100);
  288. /* get B value */
  289. regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
  290. val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >>
  291. SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT;
  292. val = min(val + b_offset, (u32)0x3f);
  293. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
  294. SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
  295. SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,
  296. SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
  297. SUN8I_HDMI_PHY_PLL_CFG1_REG_OD);
  298. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
  299. SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,
  300. val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT);
  301. msleep(100);
  302. regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end);
  303. regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init);
  304. regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init);
  305. return 0;
  306. }
  307. static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
  308. const struct drm_display_info *display,
  309. const struct drm_display_mode *mode)
  310. {
  311. struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
  312. u32 val = 0;
  313. if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  314. val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
  315. if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  316. val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
  317. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
  318. SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
  319. if (phy->variant->has_phy_clk)
  320. clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
  321. return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
  322. };
  323. static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi,
  324. struct sun8i_hdmi_phy *phy)
  325. {
  326. dw_hdmi_phy_gen2_txpwron(hdmi, 0);
  327. dw_hdmi_phy_gen2_pddq(hdmi, 1);
  328. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
  329. SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
  330. }
  331. static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi,
  332. struct sun8i_hdmi_phy *phy)
  333. {
  334. regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  335. SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
  336. SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
  337. SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
  338. regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
  339. }
  340. static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
  341. {
  342. struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
  343. phy->variant->phy_disable(hdmi, phy);
  344. }
  345. static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
  346. .init = &sun8i_hdmi_phy_config,
  347. .disable = &sun8i_hdmi_phy_disable,
  348. .read_hpd = &dw_hdmi_phy_read_hpd,
  349. .update_hpd = &dw_hdmi_phy_update_hpd,
  350. .setup_hpd = &dw_hdmi_phy_setup_hpd,
  351. };
  352. static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
  353. {
  354. /* enable read access to HDMI controller */
  355. regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
  356. SUN8I_HDMI_PHY_READ_EN_MAGIC);
  357. /* unscramble register offsets */
  358. regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
  359. SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
  360. }
  361. static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy)
  362. {
  363. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
  364. SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
  365. SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
  366. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
  367. 0xffff0000, 0x80c00000);
  368. }
  369. static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
  370. {
  371. sun8i_hdmi_phy_unlock(phy);
  372. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
  373. SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
  374. SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
  375. /*
  376. * Set PHY I2C address. It must match to the address set by
  377. * dw_hdmi_phy_set_slave_addr().
  378. */
  379. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
  380. SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
  381. SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
  382. }
  383. static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
  384. {
  385. unsigned int val;
  386. sun8i_hdmi_phy_unlock(phy);
  387. regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);
  388. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  389. SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
  390. SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
  391. udelay(5);
  392. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  393. SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,
  394. SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN);
  395. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  396. SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,
  397. SUN8I_HDMI_PHY_ANA_CFG1_ENVBS);
  398. usleep_range(10, 20);
  399. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  400. SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,
  401. SUN8I_HDMI_PHY_ANA_CFG1_LDOEN);
  402. udelay(5);
  403. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  404. SUN8I_HDMI_PHY_ANA_CFG1_CKEN,
  405. SUN8I_HDMI_PHY_ANA_CFG1_CKEN);
  406. usleep_range(40, 100);
  407. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  408. SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,
  409. SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL);
  410. usleep_range(100, 200);
  411. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  412. SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,
  413. SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG);
  414. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  415. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
  416. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
  417. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,
  418. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
  419. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
  420. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2);
  421. /* wait for calibration to finish */
  422. regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val,
  423. (val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D),
  424. 100, 2000);
  425. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  426. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,
  427. SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK);
  428. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
  429. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
  430. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
  431. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
  432. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,
  433. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
  434. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
  435. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
  436. SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK);
  437. /* enable DDC communication */
  438. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG,
  439. SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
  440. SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,
  441. SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
  442. SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
  443. /* reset PHY PLL clock parent */
  444. regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
  445. SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0);
  446. /* set HW control of CEC pins */
  447. regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
  448. /* read calibration data */
  449. regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
  450. phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2;
  451. }
  452. int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
  453. {
  454. int ret;
  455. ret = reset_control_deassert(phy->rst_phy);
  456. if (ret) {
  457. dev_err(phy->dev, "Cannot deassert phy reset control: %d\n", ret);
  458. return ret;
  459. }
  460. ret = clk_prepare_enable(phy->clk_bus);
  461. if (ret) {
  462. dev_err(phy->dev, "Cannot enable bus clock: %d\n", ret);
  463. goto err_assert_rst_phy;
  464. }
  465. ret = clk_prepare_enable(phy->clk_mod);
  466. if (ret) {
  467. dev_err(phy->dev, "Cannot enable mod clock: %d\n", ret);
  468. goto err_disable_clk_bus;
  469. }
  470. if (phy->variant->has_phy_clk) {
  471. ret = sun8i_phy_clk_create(phy, phy->dev,
  472. phy->variant->has_second_pll);
  473. if (ret) {
  474. dev_err(phy->dev, "Couldn't create the PHY clock\n");
  475. goto err_disable_clk_mod;
  476. }
  477. clk_prepare_enable(phy->clk_phy);
  478. }
  479. phy->variant->phy_init(phy);
  480. return 0;
  481. err_disable_clk_mod:
  482. clk_disable_unprepare(phy->clk_mod);
  483. err_disable_clk_bus:
  484. clk_disable_unprepare(phy->clk_bus);
  485. err_assert_rst_phy:
  486. reset_control_assert(phy->rst_phy);
  487. return ret;
  488. }
  489. void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy)
  490. {
  491. clk_disable_unprepare(phy->clk_mod);
  492. clk_disable_unprepare(phy->clk_bus);
  493. clk_disable_unprepare(phy->clk_phy);
  494. reset_control_assert(phy->rst_phy);
  495. }
  496. void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
  497. struct dw_hdmi_plat_data *plat_data)
  498. {
  499. struct sun8i_hdmi_phy_variant *variant = phy->variant;
  500. if (variant->is_custom_phy) {
  501. plat_data->phy_ops = &sun8i_hdmi_phy_ops;
  502. plat_data->phy_name = "sun8i_dw_hdmi_phy";
  503. plat_data->phy_data = phy;
  504. } else {
  505. plat_data->mpll_cfg = variant->mpll_cfg;
  506. plat_data->cur_ctr = variant->cur_ctr;
  507. plat_data->phy_config = variant->phy_cfg;
  508. }
  509. }
  510. static const struct regmap_config sun8i_hdmi_phy_regmap_config = {
  511. .reg_bits = 32,
  512. .val_bits = 32,
  513. .reg_stride = 4,
  514. .max_register = SUN8I_HDMI_PHY_CEC_REG,
  515. .name = "phy"
  516. };
  517. static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
  518. .is_custom_phy = true,
  519. .phy_init = &sun8i_hdmi_phy_init_a83t,
  520. .phy_disable = &sun8i_hdmi_phy_disable_a83t,
  521. .phy_config = &sun8i_hdmi_phy_config_a83t,
  522. };
  523. static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
  524. .has_phy_clk = true,
  525. .is_custom_phy = true,
  526. .phy_init = &sun8i_hdmi_phy_init_h3,
  527. .phy_disable = &sun8i_hdmi_phy_disable_h3,
  528. .phy_config = &sun8i_hdmi_phy_config_h3,
  529. };
  530. static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = {
  531. .has_phy_clk = true,
  532. .has_second_pll = true,
  533. .is_custom_phy = true,
  534. .phy_init = &sun8i_hdmi_phy_init_h3,
  535. .phy_disable = &sun8i_hdmi_phy_disable_h3,
  536. .phy_config = &sun8i_hdmi_phy_config_h3,
  537. };
  538. static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
  539. .has_phy_clk = true,
  540. .is_custom_phy = true,
  541. .phy_init = &sun8i_hdmi_phy_init_h3,
  542. .phy_disable = &sun8i_hdmi_phy_disable_h3,
  543. .phy_config = &sun8i_hdmi_phy_config_h3,
  544. };
  545. static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
  546. .cur_ctr = sun50i_h6_cur_ctr,
  547. .mpll_cfg = sun50i_h6_mpll_cfg,
  548. .phy_cfg = sun50i_h6_phy_config,
  549. .phy_init = &sun50i_hdmi_phy_init_h6,
  550. };
  551. static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
  552. {
  553. .compatible = "allwinner,sun8i-a83t-hdmi-phy",
  554. .data = &sun8i_a83t_hdmi_phy,
  555. },
  556. {
  557. .compatible = "allwinner,sun8i-h3-hdmi-phy",
  558. .data = &sun8i_h3_hdmi_phy,
  559. },
  560. {
  561. .compatible = "allwinner,sun8i-r40-hdmi-phy",
  562. .data = &sun8i_r40_hdmi_phy,
  563. },
  564. {
  565. .compatible = "allwinner,sun50i-a64-hdmi-phy",
  566. .data = &sun50i_a64_hdmi_phy,
  567. },
  568. {
  569. .compatible = "allwinner,sun50i-h6-hdmi-phy",
  570. .data = &sun50i_h6_hdmi_phy,
  571. },
  572. { /* sentinel */ }
  573. };
  574. int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
  575. {
  576. struct platform_device *pdev = of_find_device_by_node(node);
  577. struct sun8i_hdmi_phy *phy;
  578. if (!pdev)
  579. return -EPROBE_DEFER;
  580. phy = platform_get_drvdata(pdev);
  581. if (!phy)
  582. return -EPROBE_DEFER;
  583. hdmi->phy = phy;
  584. put_device(&pdev->dev);
  585. return 0;
  586. }
  587. static int sun8i_hdmi_phy_probe(struct platform_device *pdev)
  588. {
  589. const struct of_device_id *match;
  590. struct device *dev = &pdev->dev;
  591. struct device_node *node = dev->of_node;
  592. struct sun8i_hdmi_phy *phy;
  593. struct resource res;
  594. void __iomem *regs;
  595. int ret;
  596. match = of_match_node(sun8i_hdmi_phy_of_table, node);
  597. if (!match) {
  598. dev_err(dev, "Incompatible HDMI PHY\n");
  599. return -EINVAL;
  600. }
  601. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  602. if (!phy)
  603. return -ENOMEM;
  604. phy->variant = (struct sun8i_hdmi_phy_variant *)match->data;
  605. phy->dev = dev;
  606. ret = of_address_to_resource(node, 0, &res);
  607. if (ret) {
  608. dev_err(dev, "phy: Couldn't get our resources\n");
  609. return ret;
  610. }
  611. regs = devm_ioremap_resource(dev, &res);
  612. if (IS_ERR(regs)) {
  613. dev_err(dev, "Couldn't map the HDMI PHY registers\n");
  614. return PTR_ERR(regs);
  615. }
  616. phy->regs = devm_regmap_init_mmio(dev, regs,
  617. &sun8i_hdmi_phy_regmap_config);
  618. if (IS_ERR(phy->regs)) {
  619. dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
  620. return PTR_ERR(phy->regs);
  621. }
  622. phy->clk_bus = of_clk_get_by_name(node, "bus");
  623. if (IS_ERR(phy->clk_bus)) {
  624. dev_err(dev, "Could not get bus clock\n");
  625. return PTR_ERR(phy->clk_bus);
  626. }
  627. phy->clk_mod = of_clk_get_by_name(node, "mod");
  628. if (IS_ERR(phy->clk_mod)) {
  629. dev_err(dev, "Could not get mod clock\n");
  630. ret = PTR_ERR(phy->clk_mod);
  631. goto err_put_clk_bus;
  632. }
  633. if (phy->variant->has_phy_clk) {
  634. phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
  635. if (IS_ERR(phy->clk_pll0)) {
  636. dev_err(dev, "Could not get pll-0 clock\n");
  637. ret = PTR_ERR(phy->clk_pll0);
  638. goto err_put_clk_mod;
  639. }
  640. if (phy->variant->has_second_pll) {
  641. phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");
  642. if (IS_ERR(phy->clk_pll1)) {
  643. dev_err(dev, "Could not get pll-1 clock\n");
  644. ret = PTR_ERR(phy->clk_pll1);
  645. goto err_put_clk_pll0;
  646. }
  647. }
  648. }
  649. phy->rst_phy = of_reset_control_get_shared(node, "phy");
  650. if (IS_ERR(phy->rst_phy)) {
  651. dev_err(dev, "Could not get phy reset control\n");
  652. ret = PTR_ERR(phy->rst_phy);
  653. goto err_put_clk_pll1;
  654. }
  655. platform_set_drvdata(pdev, phy);
  656. return 0;
  657. err_put_clk_pll1:
  658. clk_put(phy->clk_pll1);
  659. err_put_clk_pll0:
  660. clk_put(phy->clk_pll0);
  661. err_put_clk_mod:
  662. clk_put(phy->clk_mod);
  663. err_put_clk_bus:
  664. clk_put(phy->clk_bus);
  665. return ret;
  666. }
  667. static int sun8i_hdmi_phy_remove(struct platform_device *pdev)
  668. {
  669. struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev);
  670. reset_control_put(phy->rst_phy);
  671. clk_put(phy->clk_pll0);
  672. clk_put(phy->clk_pll1);
  673. clk_put(phy->clk_mod);
  674. clk_put(phy->clk_bus);
  675. return 0;
  676. }
  677. struct platform_driver sun8i_hdmi_phy_driver = {
  678. .probe = sun8i_hdmi_phy_probe,
  679. .remove = sun8i_hdmi_phy_remove,
  680. .driver = {
  681. .name = "sun8i-hdmi-phy",
  682. .of_match_table = sun8i_hdmi_phy_of_table,
  683. },
  684. };