sun4i_tcon.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (C) 2015 Free Electrons
  4. * Copyright (C) 2015 NextThing Co
  5. *
  6. * Boris Brezillon <boris.brezillon@free-electrons.com>
  7. * Maxime Ripard <maxime.ripard@free-electrons.com>
  8. */
  9. #ifndef __SUN4I_TCON_H__
  10. #define __SUN4I_TCON_H__
  11. #include <drm/drm_crtc.h>
  12. #include <linux/kernel.h>
  13. #include <linux/list.h>
  14. #include <linux/reset.h>
  15. #define SUN4I_TCON_GCTL_REG 0x0
  16. #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31)
  17. #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
  18. #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
  19. #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
  20. #define SUN4I_TCON_GINT0_REG 0x4
  21. #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe))
  22. #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE BIT(27)
  23. #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE BIT(26)
  24. #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe))
  25. #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT BIT(11)
  26. #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT BIT(10)
  27. #define SUN4I_TCON_GINT1_REG 0x8
  28. #define SUN4I_TCON_FRM_CTL_REG 0x10
  29. #define SUN4I_TCON0_FRM_CTL_EN BIT(31)
  30. #define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6)
  31. #define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5)
  32. #define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4)
  33. #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
  34. #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
  35. #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
  36. #define SUN4I_TCON0_FRM_SEED_LR_REG 0x20
  37. #define SUN4I_TCON0_FRM_SEED_LG_REG 0x24
  38. #define SUN4I_TCON0_FRM_SEED_LB_REG 0x28
  39. #define SUN4I_TCON0_FRM_TBL0_REG 0x2c
  40. #define SUN4I_TCON0_FRM_TBL1_REG 0x30
  41. #define SUN4I_TCON0_FRM_TBL2_REG 0x34
  42. #define SUN4I_TCON0_FRM_TBL3_REG 0x38
  43. #define SUN4I_TCON0_CTL_REG 0x40
  44. #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31)
  45. #define SUN4I_TCON0_CTL_IF_MASK GENMASK(25, 24)
  46. #define SUN4I_TCON0_CTL_IF_8080 (1 << 24)
  47. #define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4)
  48. #define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
  49. #define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0)
  50. #define SUN4I_TCON0_DCLK_REG 0x44
  51. #define SUN4I_TCON0_DCLK_GATE_BIT (31)
  52. #define SUN4I_TCON0_DCLK_DIV_SHIFT (0)
  53. #define SUN4I_TCON0_DCLK_DIV_WIDTH (7)
  54. #define SUN4I_TCON0_BASIC0_REG 0x48
  55. #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
  56. #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
  57. #define SUN4I_TCON0_BASIC1_REG 0x4c
  58. #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
  59. #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
  60. #define SUN4I_TCON0_BASIC2_REG 0x50
  61. #define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16)
  62. #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
  63. #define SUN4I_TCON0_BASIC3_REG 0x54
  64. #define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16)
  65. #define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff)
  66. #define SUN4I_TCON0_HV_IF_REG 0x58
  67. #define SUN4I_TCON0_CPU_IF_REG 0x60
  68. #define SUN4I_TCON0_CPU_IF_MODE_MASK GENMASK(31, 28)
  69. #define SUN4I_TCON0_CPU_IF_MODE_DSI (1 << 28)
  70. #define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH BIT(16)
  71. #define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN BIT(2)
  72. #define SUN4I_TCON0_CPU_IF_TRI_EN BIT(0)
  73. #define SUN4I_TCON0_CPU_WR_REG 0x64
  74. #define SUN4I_TCON0_CPU_RD0_REG 0x68
  75. #define SUN4I_TCON0_CPU_RDA_REG 0x6c
  76. #define SUN4I_TCON0_TTL0_REG 0x70
  77. #define SUN4I_TCON0_TTL1_REG 0x74
  78. #define SUN4I_TCON0_TTL2_REG 0x78
  79. #define SUN4I_TCON0_TTL3_REG 0x7c
  80. #define SUN4I_TCON0_TTL4_REG 0x80
  81. #define SUN4I_TCON0_LVDS_IF_REG 0x84
  82. #define SUN4I_TCON0_LVDS_IF_EN BIT(31)
  83. #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26)
  84. #define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS (1 << 26)
  85. #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26)
  86. #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20)
  87. #define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 (1 << 20)
  88. #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4)
  89. #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL (1 << 4)
  90. #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4)
  91. #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0)
  92. #define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL (0xf)
  93. #define SUN4I_TCON0_LVDS_IF_DATA_POL_INV (0)
  94. #define SUN4I_TCON0_IO_POL_REG 0x88
  95. #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
  96. #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
  97. #define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26)
  98. #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
  99. #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
  100. #define SUN4I_TCON0_IO_TRI_REG 0x8c
  101. #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25)
  102. #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24)
  103. #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0)
  104. #define SUN4I_TCON1_CTL_REG 0x90
  105. #define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31)
  106. #define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20)
  107. #define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4)
  108. #define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
  109. #define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0)
  110. #define SUN4I_TCON1_BASIC0_REG 0x94
  111. #define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
  112. #define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff)
  113. #define SUN4I_TCON1_BASIC1_REG 0x98
  114. #define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16)
  115. #define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff)
  116. #define SUN4I_TCON1_BASIC2_REG 0x9c
  117. #define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16)
  118. #define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff)
  119. #define SUN4I_TCON1_BASIC3_REG 0xa0
  120. #define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
  121. #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
  122. #define SUN4I_TCON1_BASIC4_REG 0xa4
  123. #define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16)
  124. #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
  125. #define SUN4I_TCON1_BASIC5_REG 0xa8
  126. #define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16)
  127. #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
  128. #define SUN4I_TCON1_IO_POL_REG 0xf0
  129. /* there is no documentation about this bit */
  130. #define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
  131. #define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
  132. #define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
  133. #define SUN4I_TCON1_IO_TRI_REG 0xf4
  134. #define SUN4I_TCON_ECC_FIFO_REG 0xf8
  135. #define SUN4I_TCON_ECC_FIFO_EN BIT(3)
  136. #define SUN4I_TCON_CEU_CTL_REG 0x100
  137. #define SUN4I_TCON_CEU_MUL_RR_REG 0x110
  138. #define SUN4I_TCON_CEU_MUL_RG_REG 0x114
  139. #define SUN4I_TCON_CEU_MUL_RB_REG 0x118
  140. #define SUN4I_TCON_CEU_ADD_RC_REG 0x11c
  141. #define SUN4I_TCON_CEU_MUL_GR_REG 0x120
  142. #define SUN4I_TCON_CEU_MUL_GG_REG 0x124
  143. #define SUN4I_TCON_CEU_MUL_GB_REG 0x128
  144. #define SUN4I_TCON_CEU_ADD_GC_REG 0x12c
  145. #define SUN4I_TCON_CEU_MUL_BR_REG 0x130
  146. #define SUN4I_TCON_CEU_MUL_BG_REG 0x134
  147. #define SUN4I_TCON_CEU_MUL_BB_REG 0x138
  148. #define SUN4I_TCON_CEU_ADD_BC_REG 0x13c
  149. #define SUN4I_TCON_CEU_RANGE_R_REG 0x140
  150. #define SUN4I_TCON_CEU_RANGE_G_REG 0x144
  151. #define SUN4I_TCON_CEU_RANGE_B_REG 0x148
  152. #define SUN4I_TCON0_CPU_TRI0_REG 0x160
  153. #define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space) ((((space) - 1) & 0xfff) << 16)
  154. #define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size) (((size) - 1) & 0xfff)
  155. #define SUN4I_TCON0_CPU_TRI1_REG 0x164
  156. #define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num) (((num) - 1) & 0xffff)
  157. #define SUN4I_TCON0_CPU_TRI2_REG 0x168
  158. #define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay) (((delay) & 0xffff) << 16)
  159. #define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set) ((set) & 0xfff)
  160. #define SUN4I_TCON_SAFE_PERIOD_REG 0x1f0
  161. #define SUN4I_TCON_SAFE_PERIOD_NUM(num) (((num) & 0xfff) << 16)
  162. #define SUN4I_TCON_SAFE_PERIOD_MODE(mode) ((mode) & 0x3)
  163. #define SUN4I_TCON_MUX_CTRL_REG 0x200
  164. #define SUN4I_TCON0_LVDS_ANA0_REG 0x220
  165. #define SUN4I_TCON0_LVDS_ANA0_DCHS BIT(16)
  166. #define SUN4I_TCON0_LVDS_ANA0_PD (BIT(20) | BIT(21))
  167. #define SUN4I_TCON0_LVDS_ANA0_EN_MB BIT(22)
  168. #define SUN4I_TCON0_LVDS_ANA0_REG_C (BIT(24) | BIT(25))
  169. #define SUN4I_TCON0_LVDS_ANA0_REG_V (BIT(26) | BIT(27))
  170. #define SUN4I_TCON0_LVDS_ANA0_CK_EN (BIT(29) | BIT(28))
  171. #define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31)
  172. #define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30)
  173. #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24)
  174. #define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x) (((x) & 0xf) << 20)
  175. #define SUN6I_TCON0_LVDS_ANA0_C(x) (((x) & 3) << 17)
  176. #define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8)
  177. #define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4)
  178. #define SUN4I_TCON0_LVDS_ANA1_REG 0x224
  179. #define SUN4I_TCON0_LVDS_ANA1_INIT (0x1f << 26 | 0x1f << 10)
  180. #define SUN4I_TCON0_LVDS_ANA1_UPDATE (0x1f << 16 | 0x1f << 00)
  181. #define SUN4I_TCON1_FILL_CTL_REG 0x300
  182. #define SUN4I_TCON1_FILL_BEG0_REG 0x304
  183. #define SUN4I_TCON1_FILL_END0_REG 0x308
  184. #define SUN4I_TCON1_FILL_DATA0_REG 0x30c
  185. #define SUN4I_TCON1_FILL_BEG1_REG 0x310
  186. #define SUN4I_TCON1_FILL_END1_REG 0x314
  187. #define SUN4I_TCON1_FILL_DATA1_REG 0x318
  188. #define SUN4I_TCON1_FILL_BEG2_REG 0x31c
  189. #define SUN4I_TCON1_FILL_END2_REG 0x320
  190. #define SUN4I_TCON1_FILL_DATA2_REG 0x324
  191. #define SUN4I_TCON1_GAMMA_TABLE_REG 0x400
  192. #define SUN4I_TCON_MAX_CHANNELS 2
  193. struct sun4i_tcon;
  194. struct sun4i_tcon_quirks {
  195. bool has_channel_0; /* a83t does not have channel 0 on second TCON */
  196. bool has_channel_1; /* a33 does not have channel 1 */
  197. bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */
  198. bool needs_de_be_mux; /* sun6i needs mux to select backend */
  199. bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
  200. bool supports_lvds; /* Does the TCON support an LVDS output? */
  201. bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
  202. u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
  203. /* callback to handle tcon muxing options */
  204. int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
  205. /* handler for LVDS setup routine */
  206. void (*setup_lvds_phy)(struct sun4i_tcon *tcon,
  207. const struct drm_encoder *encoder);
  208. };
  209. struct sun4i_tcon {
  210. struct device *dev;
  211. struct drm_device *drm;
  212. struct regmap *regs;
  213. /* Main bus clock */
  214. struct clk *clk;
  215. /* Clocks for the TCON channels */
  216. struct clk *sclk0;
  217. struct clk *sclk1;
  218. /* Possible mux for the LVDS clock */
  219. struct clk *lvds_pll;
  220. /* Pixel clock */
  221. struct clk *dclk;
  222. u8 dclk_max_div;
  223. u8 dclk_min_div;
  224. /* Reset control */
  225. struct reset_control *lcd_rst;
  226. struct reset_control *lvds_rst;
  227. /* Platform adjustments */
  228. const struct sun4i_tcon_quirks *quirks;
  229. /* Associated crtc */
  230. struct sun4i_crtc *crtc;
  231. int id;
  232. /* TCON list management */
  233. struct list_head list;
  234. };
  235. struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
  236. struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
  237. void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
  238. void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
  239. const struct drm_encoder *encoder,
  240. const struct drm_display_mode *mode);
  241. void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
  242. const struct drm_encoder *encoder, bool enable);
  243. extern const struct of_device_id sun4i_tcon_of_table[];
  244. #endif /* __SUN4I_TCON_H__ */