sun4i_tcon.c 44 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2015 Free Electrons
  4. * Copyright (C) 2015 NextThing Co
  5. *
  6. * Maxime Ripard <maxime.ripard@free-electrons.com>
  7. */
  8. #include <linux/component.h>
  9. #include <linux/ioport.h>
  10. #include <linux/module.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/regmap.h>
  15. #include <linux/reset.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_bridge.h>
  18. #include <drm/drm_connector.h>
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_encoder.h>
  21. #include <drm/drm_modes.h>
  22. #include <drm/drm_of.h>
  23. #include <drm/drm_panel.h>
  24. #include <drm/drm_print.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_vblank.h>
  27. #include <uapi/drm/drm_mode.h>
  28. #include "sun4i_crtc.h"
  29. #include "sun4i_dotclock.h"
  30. #include "sun4i_drv.h"
  31. #include "sun4i_lvds.h"
  32. #include "sun4i_rgb.h"
  33. #include "sun4i_tcon.h"
  34. #include "sun6i_mipi_dsi.h"
  35. #include "sun8i_tcon_top.h"
  36. #include "sunxi_engine.h"
  37. static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
  38. {
  39. struct drm_connector *connector;
  40. struct drm_connector_list_iter iter;
  41. drm_connector_list_iter_begin(encoder->dev, &iter);
  42. drm_for_each_connector_iter(connector, &iter)
  43. if (connector->encoder == encoder) {
  44. drm_connector_list_iter_end(&iter);
  45. return connector;
  46. }
  47. drm_connector_list_iter_end(&iter);
  48. return NULL;
  49. }
  50. static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
  51. {
  52. struct drm_connector *connector;
  53. struct drm_display_info *info;
  54. connector = sun4i_tcon_get_connector(encoder);
  55. if (!connector)
  56. return -EINVAL;
  57. info = &connector->display_info;
  58. if (info->num_bus_formats != 1)
  59. return -EINVAL;
  60. switch (info->bus_formats[0]) {
  61. case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  62. return 18;
  63. case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
  64. case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
  65. return 24;
  66. }
  67. return -EINVAL;
  68. }
  69. static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
  70. bool enabled)
  71. {
  72. struct clk *clk;
  73. switch (channel) {
  74. case 0:
  75. WARN_ON(!tcon->quirks->has_channel_0);
  76. regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  77. SUN4I_TCON0_CTL_TCON_ENABLE,
  78. enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
  79. clk = tcon->dclk;
  80. break;
  81. case 1:
  82. WARN_ON(!tcon->quirks->has_channel_1);
  83. regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
  84. SUN4I_TCON1_CTL_TCON_ENABLE,
  85. enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
  86. clk = tcon->sclk1;
  87. break;
  88. default:
  89. DRM_WARN("Unknown channel... doing nothing\n");
  90. return;
  91. }
  92. if (enabled) {
  93. clk_prepare_enable(clk);
  94. clk_rate_exclusive_get(clk);
  95. } else {
  96. clk_rate_exclusive_put(clk);
  97. clk_disable_unprepare(clk);
  98. }
  99. }
  100. static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
  101. const struct drm_encoder *encoder)
  102. {
  103. regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
  104. SUN4I_TCON0_LVDS_ANA0_CK_EN |
  105. SUN4I_TCON0_LVDS_ANA0_REG_V |
  106. SUN4I_TCON0_LVDS_ANA0_REG_C |
  107. SUN4I_TCON0_LVDS_ANA0_EN_MB |
  108. SUN4I_TCON0_LVDS_ANA0_PD |
  109. SUN4I_TCON0_LVDS_ANA0_DCHS);
  110. udelay(2); /* delay at least 1200 ns */
  111. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
  112. SUN4I_TCON0_LVDS_ANA1_INIT,
  113. SUN4I_TCON0_LVDS_ANA1_INIT);
  114. udelay(1); /* delay at least 120 ns */
  115. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
  116. SUN4I_TCON0_LVDS_ANA1_UPDATE,
  117. SUN4I_TCON0_LVDS_ANA1_UPDATE);
  118. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
  119. SUN4I_TCON0_LVDS_ANA0_EN_MB,
  120. SUN4I_TCON0_LVDS_ANA0_EN_MB);
  121. }
  122. static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
  123. const struct drm_encoder *encoder)
  124. {
  125. u8 val;
  126. regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
  127. SUN6I_TCON0_LVDS_ANA0_C(2) |
  128. SUN6I_TCON0_LVDS_ANA0_V(3) |
  129. SUN6I_TCON0_LVDS_ANA0_PD(2) |
  130. SUN6I_TCON0_LVDS_ANA0_EN_LDO);
  131. udelay(2);
  132. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
  133. SUN6I_TCON0_LVDS_ANA0_EN_MB,
  134. SUN6I_TCON0_LVDS_ANA0_EN_MB);
  135. udelay(2);
  136. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
  137. SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
  138. SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
  139. if (sun4i_tcon_get_pixel_depth(encoder) == 18)
  140. val = 7;
  141. else
  142. val = 0xf;
  143. regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
  144. SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
  145. SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
  146. }
  147. static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
  148. const struct drm_encoder *encoder,
  149. bool enabled)
  150. {
  151. if (enabled) {
  152. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
  153. SUN4I_TCON0_LVDS_IF_EN,
  154. SUN4I_TCON0_LVDS_IF_EN);
  155. if (tcon->quirks->setup_lvds_phy)
  156. tcon->quirks->setup_lvds_phy(tcon, encoder);
  157. } else {
  158. regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
  159. SUN4I_TCON0_LVDS_IF_EN, 0);
  160. }
  161. }
  162. void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
  163. const struct drm_encoder *encoder,
  164. bool enabled)
  165. {
  166. bool is_lvds = false;
  167. int channel;
  168. switch (encoder->encoder_type) {
  169. case DRM_MODE_ENCODER_LVDS:
  170. is_lvds = true;
  171. fallthrough;
  172. case DRM_MODE_ENCODER_DSI:
  173. case DRM_MODE_ENCODER_NONE:
  174. channel = 0;
  175. break;
  176. case DRM_MODE_ENCODER_TMDS:
  177. case DRM_MODE_ENCODER_TVDAC:
  178. channel = 1;
  179. break;
  180. default:
  181. DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
  182. return;
  183. }
  184. if (is_lvds && !enabled)
  185. sun4i_tcon_lvds_set_status(tcon, encoder, false);
  186. regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
  187. SUN4I_TCON_GCTL_TCON_ENABLE,
  188. enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
  189. if (is_lvds && enabled)
  190. sun4i_tcon_lvds_set_status(tcon, encoder, true);
  191. sun4i_tcon_channel_set_status(tcon, channel, enabled);
  192. }
  193. void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
  194. {
  195. u32 mask, val = 0;
  196. DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
  197. mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
  198. SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
  199. SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
  200. if (enable)
  201. val = mask;
  202. regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
  203. }
  204. EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
  205. /*
  206. * This function is a helper for TCON output muxing. The TCON output
  207. * muxing control register in earlier SoCs (without the TCON TOP block)
  208. * are located in TCON0. This helper returns a pointer to TCON0's
  209. * sun4i_tcon structure, or NULL if not found.
  210. */
  211. static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
  212. {
  213. struct sun4i_drv *drv = drm->dev_private;
  214. struct sun4i_tcon *tcon;
  215. list_for_each_entry(tcon, &drv->tcon_list, list)
  216. if (tcon->id == 0)
  217. return tcon;
  218. dev_warn(drm->dev,
  219. "TCON0 not found, display output muxing may not work\n");
  220. return NULL;
  221. }
  222. static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
  223. const struct drm_encoder *encoder)
  224. {
  225. int ret = -ENOTSUPP;
  226. if (tcon->quirks->set_mux)
  227. ret = tcon->quirks->set_mux(tcon, encoder);
  228. DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
  229. encoder->name, encoder->crtc->name, ret);
  230. }
  231. static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
  232. int channel)
  233. {
  234. int delay = mode->vtotal - mode->vdisplay;
  235. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  236. delay /= 2;
  237. if (channel == 1)
  238. delay -= 2;
  239. delay = min(delay, 30);
  240. DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
  241. return delay;
  242. }
  243. static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
  244. const struct drm_display_mode *mode)
  245. {
  246. /* Configure the dot clock */
  247. clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
  248. /* Set the resolution */
  249. regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
  250. SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
  251. SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
  252. }
  253. static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
  254. const struct drm_connector *connector)
  255. {
  256. u32 bus_format = 0;
  257. u32 val = 0;
  258. /* XXX Would this ever happen? */
  259. if (!connector)
  260. return;
  261. /*
  262. * FIXME: Undocumented bits
  263. *
  264. * The whole dithering process and these parameters are not
  265. * explained in the vendor documents or BSP kernel code.
  266. */
  267. regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
  268. regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
  269. regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
  270. regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
  271. regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
  272. regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
  273. regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
  274. regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
  275. regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
  276. regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
  277. /* Do dithering if panel only supports 6 bits per color */
  278. if (connector->display_info.bpc == 6)
  279. val |= SUN4I_TCON0_FRM_CTL_EN;
  280. if (connector->display_info.num_bus_formats == 1)
  281. bus_format = connector->display_info.bus_formats[0];
  282. /* Check the connection format */
  283. switch (bus_format) {
  284. case MEDIA_BUS_FMT_RGB565_1X16:
  285. /* R and B components are only 5 bits deep */
  286. val |= SUN4I_TCON0_FRM_CTL_MODE_R;
  287. val |= SUN4I_TCON0_FRM_CTL_MODE_B;
  288. fallthrough;
  289. case MEDIA_BUS_FMT_RGB666_1X18:
  290. case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
  291. /* Fall through: enable dithering */
  292. val |= SUN4I_TCON0_FRM_CTL_EN;
  293. break;
  294. }
  295. /* Write dithering settings */
  296. regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
  297. }
  298. static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
  299. const struct drm_encoder *encoder,
  300. const struct drm_display_mode *mode)
  301. {
  302. /* TODO support normal CPU interface modes */
  303. struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
  304. struct mipi_dsi_device *device = dsi->device;
  305. u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
  306. u8 lanes = device->lanes;
  307. u32 block_space, start_delay;
  308. u32 tcon_div;
  309. tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
  310. tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
  311. sun4i_tcon0_mode_set_common(tcon, mode);
  312. /* Set dithering if needed */
  313. sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
  314. regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  315. SUN4I_TCON0_CTL_IF_MASK,
  316. SUN4I_TCON0_CTL_IF_8080);
  317. regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
  318. SUN4I_TCON_ECC_FIFO_EN);
  319. regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
  320. SUN4I_TCON0_CPU_IF_MODE_DSI |
  321. SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH |
  322. SUN4I_TCON0_CPU_IF_TRI_FIFO_EN |
  323. SUN4I_TCON0_CPU_IF_TRI_EN);
  324. /*
  325. * This looks suspicious, but it works...
  326. *
  327. * The datasheet says that this should be set higher than 20 *
  328. * pixel cycle, but it's not clear what a pixel cycle is.
  329. */
  330. regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
  331. tcon_div &= GENMASK(6, 0);
  332. block_space = mode->htotal * bpp / (tcon_div * lanes);
  333. block_space -= mode->hdisplay + 40;
  334. regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
  335. SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) |
  336. SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay));
  337. regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
  338. SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay));
  339. start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1);
  340. start_delay = start_delay * mode->crtc_htotal * 149;
  341. start_delay = start_delay / (mode->crtc_clock / 1000) / 8;
  342. regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
  343. SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
  344. SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay));
  345. /*
  346. * The Allwinner BSP has a comment that the period should be
  347. * the display clock * 15, but uses an hardcoded 3000...
  348. */
  349. regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
  350. SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
  351. SUN4I_TCON_SAFE_PERIOD_MODE(3));
  352. /* Enable the output on the pins */
  353. regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
  354. 0xe0000000);
  355. }
  356. static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
  357. const struct drm_encoder *encoder,
  358. const struct drm_display_mode *mode)
  359. {
  360. unsigned int bp;
  361. u8 clk_delay;
  362. u32 reg, val = 0;
  363. WARN_ON(!tcon->quirks->has_channel_0);
  364. tcon->dclk_min_div = 7;
  365. tcon->dclk_max_div = 7;
  366. sun4i_tcon0_mode_set_common(tcon, mode);
  367. /* Set dithering if needed */
  368. sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
  369. /* Adjust clock delay */
  370. clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
  371. regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  372. SUN4I_TCON0_CTL_CLK_DELAY_MASK,
  373. SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
  374. /*
  375. * This is called a backporch in the register documentation,
  376. * but it really is the back porch + hsync
  377. */
  378. bp = mode->crtc_htotal - mode->crtc_hsync_start;
  379. DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
  380. mode->crtc_htotal, bp);
  381. /* Set horizontal display timings */
  382. regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
  383. SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
  384. SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
  385. /*
  386. * This is called a backporch in the register documentation,
  387. * but it really is the back porch + hsync
  388. */
  389. bp = mode->crtc_vtotal - mode->crtc_vsync_start;
  390. DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
  391. mode->crtc_vtotal, bp);
  392. /* Set vertical display timings */
  393. regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
  394. SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
  395. SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
  396. reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
  397. if (sun4i_tcon_get_pixel_depth(encoder) == 24)
  398. reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
  399. else
  400. reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
  401. regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
  402. /* Setup the polarity of the various signals */
  403. if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
  404. val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
  405. if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
  406. val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
  407. regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
  408. /* Map output pins to channel 0 */
  409. regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
  410. SUN4I_TCON_GCTL_IOMAP_MASK,
  411. SUN4I_TCON_GCTL_IOMAP_TCON0);
  412. /* Enable the output on the pins */
  413. regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
  414. }
  415. static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
  416. const struct drm_encoder *encoder,
  417. const struct drm_display_mode *mode)
  418. {
  419. struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
  420. const struct drm_display_info *info = &connector->display_info;
  421. unsigned int bp, hsync, vsync;
  422. u8 clk_delay;
  423. u32 val = 0;
  424. WARN_ON(!tcon->quirks->has_channel_0);
  425. tcon->dclk_min_div = tcon->quirks->dclk_min_div;
  426. tcon->dclk_max_div = 127;
  427. sun4i_tcon0_mode_set_common(tcon, mode);
  428. /* Set dithering if needed */
  429. sun4i_tcon0_mode_set_dithering(tcon, connector);
  430. /* Adjust clock delay */
  431. clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
  432. regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  433. SUN4I_TCON0_CTL_CLK_DELAY_MASK,
  434. SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
  435. /*
  436. * This is called a backporch in the register documentation,
  437. * but it really is the back porch + hsync
  438. */
  439. bp = mode->crtc_htotal - mode->crtc_hsync_start;
  440. DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
  441. mode->crtc_htotal, bp);
  442. /* Set horizontal display timings */
  443. regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
  444. SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
  445. SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
  446. /*
  447. * This is called a backporch in the register documentation,
  448. * but it really is the back porch + hsync
  449. */
  450. bp = mode->crtc_vtotal - mode->crtc_vsync_start;
  451. DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
  452. mode->crtc_vtotal, bp);
  453. /* Set vertical display timings */
  454. regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
  455. SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
  456. SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
  457. /* Set Hsync and Vsync length */
  458. hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
  459. vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
  460. DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
  461. regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
  462. SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
  463. SUN4I_TCON0_BASIC3_H_SYNC(hsync));
  464. /* Setup the polarity of the various signals */
  465. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  466. val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
  467. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  468. val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
  469. if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
  470. val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
  471. if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
  472. val |= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
  473. regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
  474. SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
  475. SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
  476. SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE |
  477. SUN4I_TCON0_IO_POL_DE_NEGATIVE,
  478. val);
  479. /* Map output pins to channel 0 */
  480. regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
  481. SUN4I_TCON_GCTL_IOMAP_MASK,
  482. SUN4I_TCON_GCTL_IOMAP_TCON0);
  483. /* Enable the output on the pins */
  484. regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
  485. }
  486. static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
  487. const struct drm_display_mode *mode)
  488. {
  489. unsigned int bp, hsync, vsync, vtotal;
  490. u8 clk_delay;
  491. u32 val;
  492. WARN_ON(!tcon->quirks->has_channel_1);
  493. /* Configure the dot clock */
  494. clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
  495. /* Adjust clock delay */
  496. clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
  497. regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
  498. SUN4I_TCON1_CTL_CLK_DELAY_MASK,
  499. SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
  500. /* Set interlaced mode */
  501. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  502. val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
  503. else
  504. val = 0;
  505. regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
  506. SUN4I_TCON1_CTL_INTERLACE_ENABLE,
  507. val);
  508. /* Set the input resolution */
  509. regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
  510. SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
  511. SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
  512. /* Set the upscaling resolution */
  513. regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
  514. SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
  515. SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
  516. /* Set the output resolution */
  517. regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
  518. SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
  519. SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
  520. /* Set horizontal display timings */
  521. bp = mode->crtc_htotal - mode->crtc_hsync_start;
  522. DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
  523. mode->htotal, bp);
  524. regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
  525. SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
  526. SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
  527. bp = mode->crtc_vtotal - mode->crtc_vsync_start;
  528. DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
  529. mode->crtc_vtotal, bp);
  530. /*
  531. * The vertical resolution needs to be doubled in all
  532. * cases. We could use crtc_vtotal and always multiply by two,
  533. * but that leads to a rounding error in interlace when vtotal
  534. * is odd.
  535. *
  536. * This happens with TV's PAL for example, where vtotal will
  537. * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
  538. * 624, which apparently confuses the hardware.
  539. *
  540. * To work around this, we will always use vtotal, and
  541. * multiply by two only if we're not in interlace.
  542. */
  543. vtotal = mode->vtotal;
  544. if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
  545. vtotal = vtotal * 2;
  546. /* Set vertical display timings */
  547. regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
  548. SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
  549. SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
  550. /* Set Hsync and Vsync length */
  551. hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
  552. vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
  553. DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
  554. regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
  555. SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
  556. SUN4I_TCON1_BASIC5_H_SYNC(hsync));
  557. /* Setup the polarity of multiple signals */
  558. if (tcon->quirks->polarity_in_ch0) {
  559. val = 0;
  560. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  561. val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
  562. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  563. val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
  564. regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
  565. } else {
  566. /* according to vendor driver, this bit must be always set */
  567. val = SUN4I_TCON1_IO_POL_UNKNOWN;
  568. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  569. val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
  570. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  571. val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
  572. regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
  573. }
  574. /* Map output pins to channel 1 */
  575. regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
  576. SUN4I_TCON_GCTL_IOMAP_MASK,
  577. SUN4I_TCON_GCTL_IOMAP_TCON1);
  578. }
  579. void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
  580. const struct drm_encoder *encoder,
  581. const struct drm_display_mode *mode)
  582. {
  583. switch (encoder->encoder_type) {
  584. case DRM_MODE_ENCODER_DSI:
  585. /* DSI is tied to special case of CPU interface */
  586. sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
  587. break;
  588. case DRM_MODE_ENCODER_LVDS:
  589. sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
  590. break;
  591. case DRM_MODE_ENCODER_NONE:
  592. sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
  593. sun4i_tcon_set_mux(tcon, 0, encoder);
  594. break;
  595. case DRM_MODE_ENCODER_TVDAC:
  596. case DRM_MODE_ENCODER_TMDS:
  597. sun4i_tcon1_mode_set(tcon, mode);
  598. sun4i_tcon_set_mux(tcon, 1, encoder);
  599. break;
  600. default:
  601. DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
  602. }
  603. }
  604. EXPORT_SYMBOL(sun4i_tcon_mode_set);
  605. static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
  606. struct sun4i_crtc *scrtc)
  607. {
  608. unsigned long flags;
  609. spin_lock_irqsave(&dev->event_lock, flags);
  610. if (scrtc->event) {
  611. drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
  612. drm_crtc_vblank_put(&scrtc->crtc);
  613. scrtc->event = NULL;
  614. }
  615. spin_unlock_irqrestore(&dev->event_lock, flags);
  616. }
  617. static irqreturn_t sun4i_tcon_handler(int irq, void *private)
  618. {
  619. struct sun4i_tcon *tcon = private;
  620. struct drm_device *drm = tcon->drm;
  621. struct sun4i_crtc *scrtc = tcon->crtc;
  622. struct sunxi_engine *engine = scrtc->engine;
  623. unsigned int status;
  624. regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
  625. if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
  626. SUN4I_TCON_GINT0_VBLANK_INT(1) |
  627. SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
  628. return IRQ_NONE;
  629. drm_crtc_handle_vblank(&scrtc->crtc);
  630. sun4i_tcon_finish_page_flip(drm, scrtc);
  631. /* Acknowledge the interrupt */
  632. regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
  633. SUN4I_TCON_GINT0_VBLANK_INT(0) |
  634. SUN4I_TCON_GINT0_VBLANK_INT(1) |
  635. SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
  636. 0);
  637. if (engine->ops->vblank_quirk)
  638. engine->ops->vblank_quirk(engine);
  639. return IRQ_HANDLED;
  640. }
  641. static int sun4i_tcon_init_clocks(struct device *dev,
  642. struct sun4i_tcon *tcon)
  643. {
  644. tcon->clk = devm_clk_get(dev, "ahb");
  645. if (IS_ERR(tcon->clk)) {
  646. dev_err(dev, "Couldn't get the TCON bus clock\n");
  647. return PTR_ERR(tcon->clk);
  648. }
  649. clk_prepare_enable(tcon->clk);
  650. if (tcon->quirks->has_channel_0) {
  651. tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
  652. if (IS_ERR(tcon->sclk0)) {
  653. dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
  654. return PTR_ERR(tcon->sclk0);
  655. }
  656. }
  657. clk_prepare_enable(tcon->sclk0);
  658. if (tcon->quirks->has_channel_1) {
  659. tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
  660. if (IS_ERR(tcon->sclk1)) {
  661. dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
  662. return PTR_ERR(tcon->sclk1);
  663. }
  664. }
  665. return 0;
  666. }
  667. static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
  668. {
  669. clk_disable_unprepare(tcon->sclk0);
  670. clk_disable_unprepare(tcon->clk);
  671. }
  672. static int sun4i_tcon_init_irq(struct device *dev,
  673. struct sun4i_tcon *tcon)
  674. {
  675. struct platform_device *pdev = to_platform_device(dev);
  676. int irq, ret;
  677. irq = platform_get_irq(pdev, 0);
  678. if (irq < 0)
  679. return irq;
  680. ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
  681. dev_name(dev), tcon);
  682. if (ret) {
  683. dev_err(dev, "Couldn't request the IRQ\n");
  684. return ret;
  685. }
  686. return 0;
  687. }
  688. static const struct regmap_config sun4i_tcon_regmap_config = {
  689. .reg_bits = 32,
  690. .val_bits = 32,
  691. .reg_stride = 4,
  692. .max_register = 0x800,
  693. };
  694. static int sun4i_tcon_init_regmap(struct device *dev,
  695. struct sun4i_tcon *tcon)
  696. {
  697. struct platform_device *pdev = to_platform_device(dev);
  698. struct resource *res;
  699. void __iomem *regs;
  700. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  701. regs = devm_ioremap_resource(dev, res);
  702. if (IS_ERR(regs))
  703. return PTR_ERR(regs);
  704. tcon->regs = devm_regmap_init_mmio(dev, regs,
  705. &sun4i_tcon_regmap_config);
  706. if (IS_ERR(tcon->regs)) {
  707. dev_err(dev, "Couldn't create the TCON regmap\n");
  708. return PTR_ERR(tcon->regs);
  709. }
  710. /* Make sure the TCON is disabled and all IRQs are off */
  711. regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
  712. regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
  713. regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
  714. /* Disable IO lines and set them to tristate */
  715. regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
  716. regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
  717. return 0;
  718. }
  719. /*
  720. * On SoCs with the old display pipeline design (Display Engine 1.0),
  721. * the TCON is always tied to just one backend. Hence we can traverse
  722. * the of_graph upwards to find the backend our tcon is connected to,
  723. * and take its ID as our own.
  724. *
  725. * We can either identify backends from their compatible strings, which
  726. * means maintaining a large list of them. Or, since the backend is
  727. * registered and binded before the TCON, we can just go through the
  728. * list of registered backends and compare the device node.
  729. *
  730. * As the structures now store engines instead of backends, here this
  731. * function in fact searches the corresponding engine, and the ID is
  732. * requested via the get_id function of the engine.
  733. */
  734. static struct sunxi_engine *
  735. sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
  736. struct device_node *node,
  737. u32 port_id)
  738. {
  739. struct device_node *port, *ep, *remote;
  740. struct sunxi_engine *engine = ERR_PTR(-EINVAL);
  741. u32 reg = 0;
  742. port = of_graph_get_port_by_id(node, port_id);
  743. if (!port)
  744. return ERR_PTR(-EINVAL);
  745. /*
  746. * This only works if there is only one path from the TCON
  747. * to any display engine. Otherwise the probe order of the
  748. * TCONs and display engines is not guaranteed. They may
  749. * either bind to the wrong one, or worse, bind to the same
  750. * one if additional checks are not done.
  751. *
  752. * Bail out if there are multiple input connections.
  753. */
  754. if (of_get_available_child_count(port) != 1)
  755. goto out_put_port;
  756. /* Get the first connection without specifying an ID */
  757. ep = of_get_next_available_child(port, NULL);
  758. if (!ep)
  759. goto out_put_port;
  760. remote = of_graph_get_remote_port_parent(ep);
  761. if (!remote)
  762. goto out_put_ep;
  763. /* does this node match any registered engines? */
  764. list_for_each_entry(engine, &drv->engine_list, list)
  765. if (remote == engine->node)
  766. goto out_put_remote;
  767. /*
  768. * According to device tree binding input ports have even id
  769. * number and output ports have odd id. Since component with
  770. * more than one input and one output (TCON TOP) exits, correct
  771. * remote input id has to be calculated by subtracting 1 from
  772. * remote output id. If this for some reason can't be done, 0
  773. * is used as input port id.
  774. */
  775. of_node_put(port);
  776. port = of_graph_get_remote_port(ep);
  777. if (!of_property_read_u32(port, "reg", &reg) && reg > 0)
  778. reg -= 1;
  779. /* keep looking through upstream ports */
  780. engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
  781. out_put_remote:
  782. of_node_put(remote);
  783. out_put_ep:
  784. of_node_put(ep);
  785. out_put_port:
  786. of_node_put(port);
  787. return engine;
  788. }
  789. /*
  790. * The device tree binding says that the remote endpoint ID of any
  791. * connection between components, up to and including the TCON, of
  792. * the display pipeline should be equal to the actual ID of the local
  793. * component. Thus we can look at any one of the input connections of
  794. * the TCONs, and use that connection's remote endpoint ID as our own.
  795. *
  796. * Since the user of this function already finds the input port,
  797. * the port is passed in directly without further checks.
  798. */
  799. static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
  800. {
  801. struct device_node *ep;
  802. int ret = -EINVAL;
  803. /* try finding an upstream endpoint */
  804. for_each_available_child_of_node(port, ep) {
  805. struct device_node *remote;
  806. u32 reg;
  807. remote = of_graph_get_remote_endpoint(ep);
  808. if (!remote)
  809. continue;
  810. ret = of_property_read_u32(remote, "reg", &reg);
  811. if (ret)
  812. continue;
  813. ret = reg;
  814. }
  815. return ret;
  816. }
  817. /*
  818. * Once we know the TCON's id, we can look through the list of
  819. * engines to find a matching one. We assume all engines have
  820. * been probed and added to the list.
  821. */
  822. static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
  823. int id)
  824. {
  825. struct sunxi_engine *engine;
  826. list_for_each_entry(engine, &drv->engine_list, list)
  827. if (engine->id == id)
  828. return engine;
  829. return ERR_PTR(-EINVAL);
  830. }
  831. static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node)
  832. {
  833. struct device_node *remote;
  834. bool ret = false;
  835. remote = of_graph_get_remote_node(node, 0, -1);
  836. if (remote) {
  837. ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
  838. of_match_node(sun8i_tcon_top_of_table, remote));
  839. of_node_put(remote);
  840. }
  841. return ret;
  842. }
  843. static int sun4i_tcon_get_index(struct sun4i_drv *drv)
  844. {
  845. struct list_head *pos;
  846. int size = 0;
  847. /*
  848. * Because TCON is added to the list at the end of the probe
  849. * (after this function is called), index of the current TCON
  850. * will be same as current TCON list size.
  851. */
  852. list_for_each(pos, &drv->tcon_list)
  853. ++size;
  854. return size;
  855. }
  856. /*
  857. * On SoCs with the old display pipeline design (Display Engine 1.0),
  858. * we assumed the TCON was always tied to just one backend. However
  859. * this proved not to be the case. On the A31, the TCON can select
  860. * either backend as its source. On the A20 (and likely on the A10),
  861. * the backend can choose which TCON to output to.
  862. *
  863. * The device tree binding says that the remote endpoint ID of any
  864. * connection between components, up to and including the TCON, of
  865. * the display pipeline should be equal to the actual ID of the local
  866. * component. Thus we should be able to look at any one of the input
  867. * connections of the TCONs, and use that connection's remote endpoint
  868. * ID as our own.
  869. *
  870. * However the connections between the backend and TCON were assumed
  871. * to be always singular, and their endpoit IDs were all incorrectly
  872. * set to 0. This means for these old device trees, we cannot just look
  873. * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
  874. * incorrectly identified as TCON0.
  875. *
  876. * This function first checks if the TCON node has 2 input endpoints.
  877. * If so, then the device tree is a corrected version, and it will use
  878. * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
  879. * to fetch the ID and engine directly. If not, then it is likely an
  880. * old device trees, where the endpoint IDs were incorrect, but did not
  881. * have endpoint connections between the backend and TCON across
  882. * different display pipelines. It will fall back to the old method of
  883. * traversing the of_graph to try and find a matching engine by device
  884. * node.
  885. *
  886. * In the case of single display pipeline device trees, either method
  887. * works.
  888. */
  889. static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
  890. struct device_node *node)
  891. {
  892. struct device_node *port;
  893. struct sunxi_engine *engine;
  894. port = of_graph_get_port_by_id(node, 0);
  895. if (!port)
  896. return ERR_PTR(-EINVAL);
  897. /*
  898. * Is this a corrected device tree with cross pipeline
  899. * connections between the backend and TCON?
  900. */
  901. if (of_get_child_count(port) > 1) {
  902. int id;
  903. /*
  904. * When pipeline has the same number of TCONs and engines which
  905. * are represented by frontends/backends (DE1) or mixers (DE2),
  906. * we match them by their respective IDs. However, if pipeline
  907. * contains TCON TOP, chances are that there are either more
  908. * TCONs than engines (R40) or TCONs with non-consecutive ids.
  909. * (H6). In that case it's easier just use TCON index in list
  910. * as an id. That means that on R40, any 2 TCONs can be enabled
  911. * in DT out of 4 (there are 2 mixers). Due to the design of
  912. * TCON TOP, remaining 2 TCONs can't be connected to anything
  913. * anyway.
  914. */
  915. if (sun4i_tcon_connected_to_tcon_top(node))
  916. id = sun4i_tcon_get_index(drv);
  917. else
  918. id = sun4i_tcon_of_get_id_from_port(port);
  919. /* Get our engine by matching our ID */
  920. engine = sun4i_tcon_get_engine_by_id(drv, id);
  921. of_node_put(port);
  922. return engine;
  923. }
  924. /* Fallback to old method by traversing input endpoints */
  925. of_node_put(port);
  926. return sun4i_tcon_find_engine_traverse(drv, node, 0);
  927. }
  928. static int sun4i_tcon_bind(struct device *dev, struct device *master,
  929. void *data)
  930. {
  931. struct drm_device *drm = data;
  932. struct sun4i_drv *drv = drm->dev_private;
  933. struct sunxi_engine *engine;
  934. struct device_node *remote;
  935. struct sun4i_tcon *tcon;
  936. struct reset_control *edp_rstc;
  937. bool has_lvds_rst, has_lvds_alt, can_lvds;
  938. int ret;
  939. engine = sun4i_tcon_find_engine(drv, dev->of_node);
  940. if (IS_ERR(engine)) {
  941. dev_err(dev, "Couldn't find matching engine\n");
  942. return -EPROBE_DEFER;
  943. }
  944. tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
  945. if (!tcon)
  946. return -ENOMEM;
  947. dev_set_drvdata(dev, tcon);
  948. tcon->drm = drm;
  949. tcon->dev = dev;
  950. tcon->id = engine->id;
  951. tcon->quirks = of_device_get_match_data(dev);
  952. tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
  953. if (IS_ERR(tcon->lcd_rst)) {
  954. dev_err(dev, "Couldn't get our reset line\n");
  955. return PTR_ERR(tcon->lcd_rst);
  956. }
  957. if (tcon->quirks->needs_edp_reset) {
  958. edp_rstc = devm_reset_control_get_shared(dev, "edp");
  959. if (IS_ERR(edp_rstc)) {
  960. dev_err(dev, "Couldn't get edp reset line\n");
  961. return PTR_ERR(edp_rstc);
  962. }
  963. ret = reset_control_deassert(edp_rstc);
  964. if (ret) {
  965. dev_err(dev, "Couldn't deassert edp reset line\n");
  966. return ret;
  967. }
  968. }
  969. /* Make sure our TCON is reset */
  970. ret = reset_control_reset(tcon->lcd_rst);
  971. if (ret) {
  972. dev_err(dev, "Couldn't deassert our reset line\n");
  973. return ret;
  974. }
  975. if (tcon->quirks->supports_lvds) {
  976. /*
  977. * This can only be made optional since we've had DT
  978. * nodes without the LVDS reset properties.
  979. *
  980. * If the property is missing, just disable LVDS, and
  981. * print a warning.
  982. */
  983. tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
  984. if (IS_ERR(tcon->lvds_rst)) {
  985. dev_err(dev, "Couldn't get our reset line\n");
  986. return PTR_ERR(tcon->lvds_rst);
  987. } else if (tcon->lvds_rst) {
  988. has_lvds_rst = true;
  989. reset_control_reset(tcon->lvds_rst);
  990. } else {
  991. has_lvds_rst = false;
  992. }
  993. /*
  994. * This can only be made optional since we've had DT
  995. * nodes without the LVDS reset properties.
  996. *
  997. * If the property is missing, just disable LVDS, and
  998. * print a warning.
  999. */
  1000. if (tcon->quirks->has_lvds_alt) {
  1001. tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
  1002. if (IS_ERR(tcon->lvds_pll)) {
  1003. if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
  1004. has_lvds_alt = false;
  1005. } else {
  1006. dev_err(dev, "Couldn't get the LVDS PLL\n");
  1007. return PTR_ERR(tcon->lvds_pll);
  1008. }
  1009. } else {
  1010. has_lvds_alt = true;
  1011. }
  1012. }
  1013. if (!has_lvds_rst ||
  1014. (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
  1015. dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
  1016. dev_warn(dev, "LVDS output disabled\n");
  1017. can_lvds = false;
  1018. } else {
  1019. can_lvds = true;
  1020. }
  1021. } else {
  1022. can_lvds = false;
  1023. }
  1024. ret = sun4i_tcon_init_clocks(dev, tcon);
  1025. if (ret) {
  1026. dev_err(dev, "Couldn't init our TCON clocks\n");
  1027. goto err_assert_reset;
  1028. }
  1029. ret = sun4i_tcon_init_regmap(dev, tcon);
  1030. if (ret) {
  1031. dev_err(dev, "Couldn't init our TCON regmap\n");
  1032. goto err_free_clocks;
  1033. }
  1034. if (tcon->quirks->has_channel_0) {
  1035. ret = sun4i_dclk_create(dev, tcon);
  1036. if (ret) {
  1037. dev_err(dev, "Couldn't create our TCON dot clock\n");
  1038. goto err_free_clocks;
  1039. }
  1040. }
  1041. ret = sun4i_tcon_init_irq(dev, tcon);
  1042. if (ret) {
  1043. dev_err(dev, "Couldn't init our TCON interrupts\n");
  1044. goto err_free_dotclock;
  1045. }
  1046. tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
  1047. if (IS_ERR(tcon->crtc)) {
  1048. dev_err(dev, "Couldn't create our CRTC\n");
  1049. ret = PTR_ERR(tcon->crtc);
  1050. goto err_free_dotclock;
  1051. }
  1052. if (tcon->quirks->has_channel_0) {
  1053. /*
  1054. * If we have an LVDS panel connected to the TCON, we should
  1055. * just probe the LVDS connector. Otherwise, just probe RGB as
  1056. * we used to.
  1057. */
  1058. remote = of_graph_get_remote_node(dev->of_node, 1, 0);
  1059. if (of_device_is_compatible(remote, "panel-lvds"))
  1060. if (can_lvds)
  1061. ret = sun4i_lvds_init(drm, tcon);
  1062. else
  1063. ret = -EINVAL;
  1064. else
  1065. ret = sun4i_rgb_init(drm, tcon);
  1066. of_node_put(remote);
  1067. if (ret < 0)
  1068. goto err_free_dotclock;
  1069. }
  1070. if (tcon->quirks->needs_de_be_mux) {
  1071. /*
  1072. * We assume there is no dynamic muxing of backends
  1073. * and TCONs, so we select the backend with same ID.
  1074. *
  1075. * While dynamic selection might be interesting, since
  1076. * the CRTC is tied to the TCON, while the layers are
  1077. * tied to the backends, this means, we will need to
  1078. * switch between groups of layers. There might not be
  1079. * a way to represent this constraint in DRM.
  1080. */
  1081. regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
  1082. SUN4I_TCON0_CTL_SRC_SEL_MASK,
  1083. tcon->id);
  1084. regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
  1085. SUN4I_TCON1_CTL_SRC_SEL_MASK,
  1086. tcon->id);
  1087. }
  1088. list_add_tail(&tcon->list, &drv->tcon_list);
  1089. return 0;
  1090. err_free_dotclock:
  1091. if (tcon->quirks->has_channel_0)
  1092. sun4i_dclk_free(tcon);
  1093. err_free_clocks:
  1094. sun4i_tcon_free_clocks(tcon);
  1095. err_assert_reset:
  1096. reset_control_assert(tcon->lcd_rst);
  1097. return ret;
  1098. }
  1099. static void sun4i_tcon_unbind(struct device *dev, struct device *master,
  1100. void *data)
  1101. {
  1102. struct sun4i_tcon *tcon = dev_get_drvdata(dev);
  1103. list_del(&tcon->list);
  1104. if (tcon->quirks->has_channel_0)
  1105. sun4i_dclk_free(tcon);
  1106. sun4i_tcon_free_clocks(tcon);
  1107. }
  1108. static const struct component_ops sun4i_tcon_ops = {
  1109. .bind = sun4i_tcon_bind,
  1110. .unbind = sun4i_tcon_unbind,
  1111. };
  1112. static int sun4i_tcon_probe(struct platform_device *pdev)
  1113. {
  1114. struct device_node *node = pdev->dev.of_node;
  1115. const struct sun4i_tcon_quirks *quirks;
  1116. struct drm_bridge *bridge;
  1117. struct drm_panel *panel;
  1118. int ret;
  1119. quirks = of_device_get_match_data(&pdev->dev);
  1120. /* panels and bridges are present only on TCONs with channel 0 */
  1121. if (quirks->has_channel_0) {
  1122. ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
  1123. if (ret == -EPROBE_DEFER)
  1124. return ret;
  1125. }
  1126. return component_add(&pdev->dev, &sun4i_tcon_ops);
  1127. }
  1128. static int sun4i_tcon_remove(struct platform_device *pdev)
  1129. {
  1130. component_del(&pdev->dev, &sun4i_tcon_ops);
  1131. return 0;
  1132. }
  1133. /* platform specific TCON muxing callbacks */
  1134. static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
  1135. const struct drm_encoder *encoder)
  1136. {
  1137. struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
  1138. u32 shift;
  1139. if (!tcon0)
  1140. return -EINVAL;
  1141. switch (encoder->encoder_type) {
  1142. case DRM_MODE_ENCODER_TMDS:
  1143. /* HDMI */
  1144. shift = 8;
  1145. break;
  1146. default:
  1147. return -EINVAL;
  1148. }
  1149. regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
  1150. 0x3 << shift, tcon->id << shift);
  1151. return 0;
  1152. }
  1153. static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
  1154. const struct drm_encoder *encoder)
  1155. {
  1156. u32 val;
  1157. if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
  1158. val = 1;
  1159. else
  1160. val = 0;
  1161. /*
  1162. * FIXME: Undocumented bits
  1163. */
  1164. return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
  1165. }
  1166. static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
  1167. const struct drm_encoder *encoder)
  1168. {
  1169. struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
  1170. u32 shift;
  1171. if (!tcon0)
  1172. return -EINVAL;
  1173. switch (encoder->encoder_type) {
  1174. case DRM_MODE_ENCODER_TMDS:
  1175. /* HDMI */
  1176. shift = 8;
  1177. break;
  1178. default:
  1179. /* TODO A31 has MIPI DSI but A31s does not */
  1180. return -EINVAL;
  1181. }
  1182. regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
  1183. 0x3 << shift, tcon->id << shift);
  1184. return 0;
  1185. }
  1186. static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
  1187. const struct drm_encoder *encoder)
  1188. {
  1189. struct device_node *port, *remote;
  1190. struct platform_device *pdev;
  1191. int id, ret;
  1192. /* find TCON TOP platform device and TCON id */
  1193. port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
  1194. if (!port)
  1195. return -EINVAL;
  1196. id = sun4i_tcon_of_get_id_from_port(port);
  1197. of_node_put(port);
  1198. remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
  1199. if (!remote)
  1200. return -EINVAL;
  1201. pdev = of_find_device_by_node(remote);
  1202. of_node_put(remote);
  1203. if (!pdev)
  1204. return -EINVAL;
  1205. if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
  1206. encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {
  1207. ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id);
  1208. if (ret) {
  1209. put_device(&pdev->dev);
  1210. return ret;
  1211. }
  1212. }
  1213. if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) {
  1214. ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
  1215. if (ret) {
  1216. put_device(&pdev->dev);
  1217. return ret;
  1218. }
  1219. }
  1220. return 0;
  1221. }
  1222. static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
  1223. .has_channel_0 = true,
  1224. .has_channel_1 = true,
  1225. .dclk_min_div = 4,
  1226. .set_mux = sun4i_a10_tcon_set_mux,
  1227. };
  1228. static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
  1229. .has_channel_0 = true,
  1230. .has_channel_1 = true,
  1231. .dclk_min_div = 4,
  1232. .set_mux = sun5i_a13_tcon_set_mux,
  1233. };
  1234. static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
  1235. .has_channel_0 = true,
  1236. .has_channel_1 = true,
  1237. .has_lvds_alt = true,
  1238. .needs_de_be_mux = true,
  1239. .dclk_min_div = 1,
  1240. .set_mux = sun6i_tcon_set_mux,
  1241. };
  1242. static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
  1243. .has_channel_0 = true,
  1244. .has_channel_1 = true,
  1245. .needs_de_be_mux = true,
  1246. .dclk_min_div = 1,
  1247. };
  1248. static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = {
  1249. .supports_lvds = true,
  1250. .has_channel_0 = true,
  1251. .has_channel_1 = true,
  1252. .dclk_min_div = 4,
  1253. /* Same display pipeline structure as A10 */
  1254. .set_mux = sun4i_a10_tcon_set_mux,
  1255. .setup_lvds_phy = sun4i_tcon_setup_lvds_phy,
  1256. };
  1257. static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
  1258. .has_channel_0 = true,
  1259. .has_channel_1 = true,
  1260. .dclk_min_div = 4,
  1261. /* Same display pipeline structure as A10 */
  1262. .set_mux = sun4i_a10_tcon_set_mux,
  1263. };
  1264. static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
  1265. .has_channel_0 = true,
  1266. .has_lvds_alt = true,
  1267. .dclk_min_div = 1,
  1268. .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
  1269. .supports_lvds = true,
  1270. };
  1271. static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
  1272. .supports_lvds = true,
  1273. .has_channel_0 = true,
  1274. .dclk_min_div = 1,
  1275. .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
  1276. };
  1277. static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
  1278. .has_channel_1 = true,
  1279. };
  1280. static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
  1281. .has_channel_1 = true,
  1282. .polarity_in_ch0 = true,
  1283. .set_mux = sun8i_r40_tcon_tv_set_mux,
  1284. };
  1285. static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
  1286. .has_channel_0 = true,
  1287. .dclk_min_div = 1,
  1288. };
  1289. static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
  1290. .has_channel_0 = true,
  1291. .needs_edp_reset = true,
  1292. .dclk_min_div = 1,
  1293. };
  1294. static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
  1295. .has_channel_1 = true,
  1296. .needs_edp_reset = true,
  1297. };
  1298. /* sun4i_drv uses this list to check if a device node is a TCON */
  1299. const struct of_device_id sun4i_tcon_of_table[] = {
  1300. { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
  1301. { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
  1302. { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
  1303. { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
  1304. { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
  1305. { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
  1306. { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
  1307. { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
  1308. { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
  1309. { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
  1310. { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
  1311. { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
  1312. { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
  1313. { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
  1314. { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
  1315. { }
  1316. };
  1317. MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
  1318. EXPORT_SYMBOL(sun4i_tcon_of_table);
  1319. static struct platform_driver sun4i_tcon_platform_driver = {
  1320. .probe = sun4i_tcon_probe,
  1321. .remove = sun4i_tcon_remove,
  1322. .driver = {
  1323. .name = "sun4i-tcon",
  1324. .of_match_table = sun4i_tcon_of_table,
  1325. },
  1326. };
  1327. module_platform_driver(sun4i_tcon_platform_driver);
  1328. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  1329. MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
  1330. MODULE_LICENSE("GPL");