sun4i_hdmi_i2c.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
  4. * Copyright (C) 2017 Jonathan Liu <net147@gmail.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/i2c.h>
  8. #include <linux/iopoll.h>
  9. #include "sun4i_hdmi.h"
  10. #define SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK ( \
  11. SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION | \
  12. SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW | \
  13. SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW | \
  14. SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR | \
  15. SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR | \
  16. SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR \
  17. )
  18. /* FIFO request bit is set when FIFO level is above RX_THRESHOLD during read */
  19. #define RX_THRESHOLD SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX
  20. static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read)
  21. {
  22. /*
  23. * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz
  24. * clock. As clock rate is fixed, just round it up to 100 us.
  25. */
  26. const unsigned long byte_time_ns = 100;
  27. const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
  28. SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
  29. SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE;
  30. u32 reg;
  31. /*
  32. * If threshold is inclusive, then the FIFO may only have
  33. * RX_THRESHOLD number of bytes, instead of RX_THRESHOLD + 1.
  34. */
  35. int read_len = RX_THRESHOLD +
  36. (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
  37. /*
  38. * Limit transfer length by FIFO threshold or FIFO size.
  39. * For TX the threshold is for an empty FIFO.
  40. */
  41. len = min_t(int, len, read ? read_len : SUN4I_HDMI_DDC_FIFO_SIZE);
  42. /* Wait until error, FIFO request bit set or transfer complete */
  43. if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg,
  44. reg & mask, len * byte_time_ns,
  45. 100000))
  46. return -ETIMEDOUT;
  47. if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK)
  48. return -EIO;
  49. if (read)
  50. readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
  51. else
  52. writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
  53. /* Clear FIFO request bit by forcing a write to that bit */
  54. regmap_field_force_write(hdmi->field_ddc_int_status,
  55. SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST);
  56. return len;
  57. }
  58. static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg)
  59. {
  60. int i, len;
  61. u32 reg;
  62. /* Set FIFO direction */
  63. if (hdmi->variant->ddc_fifo_has_dir) {
  64. reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
  65. reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
  66. reg |= (msg->flags & I2C_M_RD) ?
  67. SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
  68. SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
  69. writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
  70. }
  71. /* Clear address register (not cleared by soft reset) */
  72. regmap_field_write(hdmi->field_ddc_addr_reg, 0);
  73. /* Set I2C address */
  74. regmap_field_write(hdmi->field_ddc_slave_addr, msg->addr);
  75. /*
  76. * Set FIFO RX/TX thresholds and clear FIFO
  77. *
  78. * If threshold is inclusive, we can set the TX threshold to
  79. * 0 instead of 1.
  80. */
  81. regmap_field_write(hdmi->field_ddc_fifo_tx_thres,
  82. hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
  83. regmap_field_write(hdmi->field_ddc_fifo_rx_thres, RX_THRESHOLD);
  84. regmap_field_write(hdmi->field_ddc_fifo_clear, 1);
  85. if (regmap_field_read_poll_timeout(hdmi->field_ddc_fifo_clear,
  86. reg, !reg, 100, 2000))
  87. return -EIO;
  88. /* Set transfer length */
  89. regmap_field_write(hdmi->field_ddc_byte_count, msg->len);
  90. /* Set command */
  91. regmap_field_write(hdmi->field_ddc_cmd,
  92. msg->flags & I2C_M_RD ?
  93. SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
  94. SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE);
  95. /* Clear interrupt status bits by forcing a write */
  96. regmap_field_force_write(hdmi->field_ddc_int_status,
  97. SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
  98. SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
  99. SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE);
  100. /* Start command */
  101. regmap_field_write(hdmi->field_ddc_start, 1);
  102. /* Transfer bytes */
  103. for (i = 0; i < msg->len; i += len) {
  104. len = fifo_transfer(hdmi, msg->buf + i, msg->len - i,
  105. msg->flags & I2C_M_RD);
  106. if (len <= 0)
  107. return len;
  108. }
  109. /* Wait for command to finish */
  110. if (regmap_field_read_poll_timeout(hdmi->field_ddc_start,
  111. reg, !reg, 100, 100000))
  112. return -EIO;
  113. /* Check for errors */
  114. regmap_field_read(hdmi->field_ddc_int_status, &reg);
  115. if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) ||
  116. !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) {
  117. return -EIO;
  118. }
  119. return 0;
  120. }
  121. static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap,
  122. struct i2c_msg *msgs, int num)
  123. {
  124. struct sun4i_hdmi *hdmi = i2c_get_adapdata(adap);
  125. u32 reg;
  126. int err, i, ret = num;
  127. for (i = 0; i < num; i++) {
  128. if (!msgs[i].len)
  129. return -EINVAL;
  130. if (msgs[i].len > SUN4I_HDMI_DDC_BYTE_COUNT_MAX)
  131. return -EINVAL;
  132. }
  133. /* DDC clock needs to be enabled for the module to work */
  134. clk_prepare_enable(hdmi->ddc_clk);
  135. clk_set_rate(hdmi->ddc_clk, 100000);
  136. /* Reset I2C controller */
  137. regmap_field_write(hdmi->field_ddc_en, 1);
  138. regmap_field_write(hdmi->field_ddc_reset, 1);
  139. if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset,
  140. reg, !reg, 100, 2000)) {
  141. clk_disable_unprepare(hdmi->ddc_clk);
  142. return -EIO;
  143. }
  144. regmap_field_write(hdmi->field_ddc_sck_en, 1);
  145. regmap_field_write(hdmi->field_ddc_sda_en, 1);
  146. for (i = 0; i < num; i++) {
  147. err = xfer_msg(hdmi, &msgs[i]);
  148. if (err) {
  149. ret = err;
  150. break;
  151. }
  152. }
  153. clk_disable_unprepare(hdmi->ddc_clk);
  154. return ret;
  155. }
  156. static u32 sun4i_hdmi_i2c_func(struct i2c_adapter *adap)
  157. {
  158. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  159. }
  160. static const struct i2c_algorithm sun4i_hdmi_i2c_algorithm = {
  161. .master_xfer = sun4i_hdmi_i2c_xfer,
  162. .functionality = sun4i_hdmi_i2c_func,
  163. };
  164. static int sun4i_hdmi_init_regmap_fields(struct sun4i_hdmi *hdmi)
  165. {
  166. hdmi->field_ddc_en =
  167. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  168. hdmi->variant->field_ddc_en);
  169. if (IS_ERR(hdmi->field_ddc_en))
  170. return PTR_ERR(hdmi->field_ddc_en);
  171. hdmi->field_ddc_start =
  172. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  173. hdmi->variant->field_ddc_start);
  174. if (IS_ERR(hdmi->field_ddc_start))
  175. return PTR_ERR(hdmi->field_ddc_start);
  176. hdmi->field_ddc_reset =
  177. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  178. hdmi->variant->field_ddc_reset);
  179. if (IS_ERR(hdmi->field_ddc_reset))
  180. return PTR_ERR(hdmi->field_ddc_reset);
  181. hdmi->field_ddc_addr_reg =
  182. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  183. hdmi->variant->field_ddc_addr_reg);
  184. if (IS_ERR(hdmi->field_ddc_addr_reg))
  185. return PTR_ERR(hdmi->field_ddc_addr_reg);
  186. hdmi->field_ddc_slave_addr =
  187. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  188. hdmi->variant->field_ddc_slave_addr);
  189. if (IS_ERR(hdmi->field_ddc_slave_addr))
  190. return PTR_ERR(hdmi->field_ddc_slave_addr);
  191. hdmi->field_ddc_int_mask =
  192. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  193. hdmi->variant->field_ddc_int_mask);
  194. if (IS_ERR(hdmi->field_ddc_int_mask))
  195. return PTR_ERR(hdmi->field_ddc_int_mask);
  196. hdmi->field_ddc_int_status =
  197. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  198. hdmi->variant->field_ddc_int_status);
  199. if (IS_ERR(hdmi->field_ddc_int_status))
  200. return PTR_ERR(hdmi->field_ddc_int_status);
  201. hdmi->field_ddc_fifo_clear =
  202. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  203. hdmi->variant->field_ddc_fifo_clear);
  204. if (IS_ERR(hdmi->field_ddc_fifo_clear))
  205. return PTR_ERR(hdmi->field_ddc_fifo_clear);
  206. hdmi->field_ddc_fifo_rx_thres =
  207. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  208. hdmi->variant->field_ddc_fifo_rx_thres);
  209. if (IS_ERR(hdmi->field_ddc_fifo_rx_thres))
  210. return PTR_ERR(hdmi->field_ddc_fifo_rx_thres);
  211. hdmi->field_ddc_fifo_tx_thres =
  212. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  213. hdmi->variant->field_ddc_fifo_tx_thres);
  214. if (IS_ERR(hdmi->field_ddc_fifo_tx_thres))
  215. return PTR_ERR(hdmi->field_ddc_fifo_tx_thres);
  216. hdmi->field_ddc_byte_count =
  217. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  218. hdmi->variant->field_ddc_byte_count);
  219. if (IS_ERR(hdmi->field_ddc_byte_count))
  220. return PTR_ERR(hdmi->field_ddc_byte_count);
  221. hdmi->field_ddc_cmd =
  222. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  223. hdmi->variant->field_ddc_cmd);
  224. if (IS_ERR(hdmi->field_ddc_cmd))
  225. return PTR_ERR(hdmi->field_ddc_cmd);
  226. hdmi->field_ddc_sda_en =
  227. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  228. hdmi->variant->field_ddc_sda_en);
  229. if (IS_ERR(hdmi->field_ddc_sda_en))
  230. return PTR_ERR(hdmi->field_ddc_sda_en);
  231. hdmi->field_ddc_sck_en =
  232. devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
  233. hdmi->variant->field_ddc_sck_en);
  234. if (IS_ERR(hdmi->field_ddc_sck_en))
  235. return PTR_ERR(hdmi->field_ddc_sck_en);
  236. return 0;
  237. }
  238. int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi)
  239. {
  240. struct i2c_adapter *adap;
  241. int ret = 0;
  242. ret = sun4i_ddc_create(hdmi, hdmi->ddc_parent_clk);
  243. if (ret)
  244. return ret;
  245. ret = sun4i_hdmi_init_regmap_fields(hdmi);
  246. if (ret)
  247. return ret;
  248. adap = devm_kzalloc(dev, sizeof(*adap), GFP_KERNEL);
  249. if (!adap)
  250. return -ENOMEM;
  251. adap->owner = THIS_MODULE;
  252. adap->class = I2C_CLASS_DDC;
  253. adap->algo = &sun4i_hdmi_i2c_algorithm;
  254. strlcpy(adap->name, "sun4i_hdmi_i2c adapter", sizeof(adap->name));
  255. i2c_set_adapdata(adap, hdmi);
  256. ret = i2c_add_adapter(adap);
  257. if (ret)
  258. return ret;
  259. hdmi->i2c = adap;
  260. return ret;
  261. }