ltdc.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2017
  4. *
  5. * Authors: Philippe Cornu <philippe.cornu@st.com>
  6. * Yannick Fertre <yannick.fertre@st.com>
  7. * Fabien Dessenne <fabien.dessenne@st.com>
  8. * Mickael Reulier <mickael.reulier@st.com>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/component.h>
  12. #include <linux/delay.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/pinctrl/consumer.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/reset.h>
  21. #include <drm/drm_atomic.h>
  22. #include <drm/drm_atomic_helper.h>
  23. #include <drm/drm_bridge.h>
  24. #include <drm/drm_device.h>
  25. #include <drm/drm_fb_cma_helper.h>
  26. #include <drm/drm_fourcc.h>
  27. #include <drm/drm_gem_cma_helper.h>
  28. #include <drm/drm_gem_framebuffer_helper.h>
  29. #include <drm/drm_of.h>
  30. #include <drm/drm_plane_helper.h>
  31. #include <drm/drm_probe_helper.h>
  32. #include <drm/drm_vblank.h>
  33. #include <video/videomode.h>
  34. #include "ltdc.h"
  35. #define NB_CRTC 1
  36. #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
  37. #define MAX_IRQ 4
  38. #define HWVER_10200 0x010200
  39. #define HWVER_10300 0x010300
  40. #define HWVER_20101 0x020101
  41. /*
  42. * The address of some registers depends on the HW version: such registers have
  43. * an extra offset specified with reg_ofs.
  44. */
  45. #define REG_OFS_NONE 0
  46. #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */
  47. #define REG_OFS (ldev->caps.reg_ofs)
  48. #define LAY_OFS 0x80 /* Register Offset between 2 layers */
  49. /* Global register offsets */
  50. #define LTDC_IDR 0x0000 /* IDentification */
  51. #define LTDC_LCR 0x0004 /* Layer Count */
  52. #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
  53. #define LTDC_BPCR 0x000C /* Back Porch Configuration */
  54. #define LTDC_AWCR 0x0010 /* Active Width Configuration */
  55. #define LTDC_TWCR 0x0014 /* Total Width Configuration */
  56. #define LTDC_GCR 0x0018 /* Global Control */
  57. #define LTDC_GC1R 0x001C /* Global Configuration 1 */
  58. #define LTDC_GC2R 0x0020 /* Global Configuration 2 */
  59. #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
  60. #define LTDC_GACR 0x0028 /* GAmma Correction */
  61. #define LTDC_BCCR 0x002C /* Background Color Configuration */
  62. #define LTDC_IER 0x0034 /* Interrupt Enable */
  63. #define LTDC_ISR 0x0038 /* Interrupt Status */
  64. #define LTDC_ICR 0x003C /* Interrupt Clear */
  65. #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */
  66. #define LTDC_CPSR 0x0044 /* Current Position Status */
  67. #define LTDC_CDSR 0x0048 /* Current Display Status */
  68. /* Layer register offsets */
  69. #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */
  70. #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */
  71. #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */
  72. #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */
  73. #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */
  74. #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */
  75. #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */
  76. #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */
  77. #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */
  78. #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */
  79. #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */
  80. #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */
  81. #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */
  82. #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */
  83. #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */
  84. #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */
  85. #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */
  86. #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */
  87. #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */
  88. #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */
  89. #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */
  90. /* Bit definitions */
  91. #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
  92. #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
  93. #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
  94. #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
  95. #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
  96. #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
  97. #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
  98. #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
  99. #define GCR_LTDCEN BIT(0) /* LTDC ENable */
  100. #define GCR_DEN BIT(16) /* Dither ENable */
  101. #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
  102. #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
  103. #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
  104. #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
  105. #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
  106. #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
  107. #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
  108. #define GC1R_PBEN BIT(12) /* Precise Blending ENable */
  109. #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
  110. #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
  111. #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
  112. #define GC1R_BCP BIT(22) /* Background Colour Programmable */
  113. #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
  114. #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
  115. #define GC1R_TP BIT(25) /* Timing Programmable */
  116. #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
  117. #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
  118. #define GC1R_DWP BIT(28) /* Dither Width Programmable */
  119. #define GC1R_STREN BIT(29) /* STatus Registers ENabled */
  120. #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
  121. #define GC2R_EDCA BIT(0) /* External Display Control Ability */
  122. #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
  123. #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
  124. #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
  125. #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
  126. #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
  127. #define SRCR_IMR BIT(0) /* IMmediate Reload */
  128. #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
  129. #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
  130. #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
  131. #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
  132. #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
  133. #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
  134. #define IER_LIE BIT(0) /* Line Interrupt Enable */
  135. #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
  136. #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
  137. #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
  138. #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */
  139. #define ISR_LIF BIT(0) /* Line Interrupt Flag */
  140. #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
  141. #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
  142. #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
  143. #define LXCR_LEN BIT(0) /* Layer ENable */
  144. #define LXCR_COLKEN BIT(1) /* Color Keying Enable */
  145. #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
  146. #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
  147. #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
  148. #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
  149. #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
  150. #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
  151. #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
  152. #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
  153. #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
  154. #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
  155. #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
  156. #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
  157. #define CLUT_SIZE 256
  158. #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
  159. #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
  160. #define BF1_CA 0x400 /* Constant Alpha */
  161. #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
  162. #define BF2_1CA 0x005 /* 1 - Constant Alpha */
  163. #define NB_PF 8 /* Max nb of HW pixel format */
  164. enum ltdc_pix_fmt {
  165. PF_NONE,
  166. /* RGB formats */
  167. PF_ARGB8888, /* ARGB [32 bits] */
  168. PF_RGBA8888, /* RGBA [32 bits] */
  169. PF_RGB888, /* RGB [24 bits] */
  170. PF_RGB565, /* RGB [16 bits] */
  171. PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
  172. PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
  173. /* Indexed formats */
  174. PF_L8, /* Indexed 8 bits [8 bits] */
  175. PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
  176. PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
  177. };
  178. /* The index gives the encoding of the pixel format for an HW version */
  179. static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
  180. PF_ARGB8888, /* 0x00 */
  181. PF_RGB888, /* 0x01 */
  182. PF_RGB565, /* 0x02 */
  183. PF_ARGB1555, /* 0x03 */
  184. PF_ARGB4444, /* 0x04 */
  185. PF_L8, /* 0x05 */
  186. PF_AL44, /* 0x06 */
  187. PF_AL88 /* 0x07 */
  188. };
  189. static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
  190. PF_ARGB8888, /* 0x00 */
  191. PF_RGB888, /* 0x01 */
  192. PF_RGB565, /* 0x02 */
  193. PF_RGBA8888, /* 0x03 */
  194. PF_AL44, /* 0x04 */
  195. PF_L8, /* 0x05 */
  196. PF_ARGB1555, /* 0x06 */
  197. PF_ARGB4444 /* 0x07 */
  198. };
  199. static const u64 ltdc_format_modifiers[] = {
  200. DRM_FORMAT_MOD_LINEAR,
  201. DRM_FORMAT_MOD_INVALID
  202. };
  203. static inline u32 reg_read(void __iomem *base, u32 reg)
  204. {
  205. return readl_relaxed(base + reg);
  206. }
  207. static inline void reg_write(void __iomem *base, u32 reg, u32 val)
  208. {
  209. writel_relaxed(val, base + reg);
  210. }
  211. static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
  212. {
  213. reg_write(base, reg, reg_read(base, reg) | mask);
  214. }
  215. static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
  216. {
  217. reg_write(base, reg, reg_read(base, reg) & ~mask);
  218. }
  219. static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
  220. u32 val)
  221. {
  222. reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
  223. }
  224. static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
  225. {
  226. return (struct ltdc_device *)crtc->dev->dev_private;
  227. }
  228. static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
  229. {
  230. return (struct ltdc_device *)plane->dev->dev_private;
  231. }
  232. static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
  233. {
  234. return (struct ltdc_device *)enc->dev->dev_private;
  235. }
  236. static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
  237. {
  238. enum ltdc_pix_fmt pf;
  239. switch (drm_fmt) {
  240. case DRM_FORMAT_ARGB8888:
  241. case DRM_FORMAT_XRGB8888:
  242. pf = PF_ARGB8888;
  243. break;
  244. case DRM_FORMAT_RGBA8888:
  245. case DRM_FORMAT_RGBX8888:
  246. pf = PF_RGBA8888;
  247. break;
  248. case DRM_FORMAT_RGB888:
  249. pf = PF_RGB888;
  250. break;
  251. case DRM_FORMAT_RGB565:
  252. pf = PF_RGB565;
  253. break;
  254. case DRM_FORMAT_ARGB1555:
  255. case DRM_FORMAT_XRGB1555:
  256. pf = PF_ARGB1555;
  257. break;
  258. case DRM_FORMAT_ARGB4444:
  259. case DRM_FORMAT_XRGB4444:
  260. pf = PF_ARGB4444;
  261. break;
  262. case DRM_FORMAT_C8:
  263. pf = PF_L8;
  264. break;
  265. default:
  266. pf = PF_NONE;
  267. break;
  268. /* Note: There are no DRM_FORMAT for AL44 and AL88 */
  269. }
  270. return pf;
  271. }
  272. static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
  273. {
  274. switch (pf) {
  275. case PF_ARGB8888:
  276. return DRM_FORMAT_ARGB8888;
  277. case PF_RGBA8888:
  278. return DRM_FORMAT_RGBA8888;
  279. case PF_RGB888:
  280. return DRM_FORMAT_RGB888;
  281. case PF_RGB565:
  282. return DRM_FORMAT_RGB565;
  283. case PF_ARGB1555:
  284. return DRM_FORMAT_ARGB1555;
  285. case PF_ARGB4444:
  286. return DRM_FORMAT_ARGB4444;
  287. case PF_L8:
  288. return DRM_FORMAT_C8;
  289. case PF_AL44: /* No DRM support */
  290. case PF_AL88: /* No DRM support */
  291. case PF_NONE:
  292. default:
  293. return 0;
  294. }
  295. }
  296. static inline u32 get_pixelformat_without_alpha(u32 drm)
  297. {
  298. switch (drm) {
  299. case DRM_FORMAT_ARGB4444:
  300. return DRM_FORMAT_XRGB4444;
  301. case DRM_FORMAT_RGBA4444:
  302. return DRM_FORMAT_RGBX4444;
  303. case DRM_FORMAT_ARGB1555:
  304. return DRM_FORMAT_XRGB1555;
  305. case DRM_FORMAT_RGBA5551:
  306. return DRM_FORMAT_RGBX5551;
  307. case DRM_FORMAT_ARGB8888:
  308. return DRM_FORMAT_XRGB8888;
  309. case DRM_FORMAT_RGBA8888:
  310. return DRM_FORMAT_RGBX8888;
  311. default:
  312. return 0;
  313. }
  314. }
  315. static irqreturn_t ltdc_irq_thread(int irq, void *arg)
  316. {
  317. struct drm_device *ddev = arg;
  318. struct ltdc_device *ldev = ddev->dev_private;
  319. struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
  320. /* Line IRQ : trigger the vblank event */
  321. if (ldev->irq_status & ISR_LIF)
  322. drm_crtc_handle_vblank(crtc);
  323. /* Save FIFO Underrun & Transfer Error status */
  324. mutex_lock(&ldev->err_lock);
  325. if (ldev->irq_status & ISR_FUIF)
  326. ldev->error_status |= ISR_FUIF;
  327. if (ldev->irq_status & ISR_TERRIF)
  328. ldev->error_status |= ISR_TERRIF;
  329. mutex_unlock(&ldev->err_lock);
  330. return IRQ_HANDLED;
  331. }
  332. static irqreturn_t ltdc_irq(int irq, void *arg)
  333. {
  334. struct drm_device *ddev = arg;
  335. struct ltdc_device *ldev = ddev->dev_private;
  336. /* Read & Clear the interrupt status */
  337. ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
  338. reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
  339. return IRQ_WAKE_THREAD;
  340. }
  341. /*
  342. * DRM_CRTC
  343. */
  344. static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
  345. {
  346. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  347. struct drm_color_lut *lut;
  348. u32 val;
  349. int i;
  350. if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
  351. return;
  352. lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
  353. for (i = 0; i < CLUT_SIZE; i++, lut++) {
  354. val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
  355. (lut->blue >> 8) | (i << 24);
  356. reg_write(ldev->regs, LTDC_L1CLUTWR, val);
  357. }
  358. }
  359. static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
  360. struct drm_crtc_state *old_state)
  361. {
  362. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  363. struct drm_device *ddev = crtc->dev;
  364. DRM_DEBUG_DRIVER("\n");
  365. pm_runtime_get_sync(ddev->dev);
  366. /* Sets the background color value */
  367. reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
  368. /* Enable IRQ */
  369. reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
  370. /* Commit shadow registers = update planes at next vblank */
  371. reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
  372. drm_crtc_vblank_on(crtc);
  373. }
  374. static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
  375. struct drm_crtc_state *old_state)
  376. {
  377. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  378. struct drm_device *ddev = crtc->dev;
  379. DRM_DEBUG_DRIVER("\n");
  380. drm_crtc_vblank_off(crtc);
  381. /* disable IRQ */
  382. reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
  383. /* immediately commit disable of layers before switching off LTDC */
  384. reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
  385. pm_runtime_put_sync(ddev->dev);
  386. }
  387. #define CLK_TOLERANCE_HZ 50
  388. static enum drm_mode_status
  389. ltdc_crtc_mode_valid(struct drm_crtc *crtc,
  390. const struct drm_display_mode *mode)
  391. {
  392. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  393. int target = mode->clock * 1000;
  394. int target_min = target - CLK_TOLERANCE_HZ;
  395. int target_max = target + CLK_TOLERANCE_HZ;
  396. int result;
  397. result = clk_round_rate(ldev->pixel_clk, target);
  398. DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
  399. /* Filter modes according to the max frequency supported by the pads */
  400. if (result > ldev->caps.pad_max_freq_hz)
  401. return MODE_CLOCK_HIGH;
  402. /*
  403. * Accept all "preferred" modes:
  404. * - this is important for panels because panel clock tolerances are
  405. * bigger than hdmi ones and there is no reason to not accept them
  406. * (the fps may vary a little but it is not a problem).
  407. * - the hdmi preferred mode will be accepted too, but userland will
  408. * be able to use others hdmi "valid" modes if necessary.
  409. */
  410. if (mode->type & DRM_MODE_TYPE_PREFERRED)
  411. return MODE_OK;
  412. /*
  413. * Filter modes according to the clock value, particularly useful for
  414. * hdmi modes that require precise pixel clocks.
  415. */
  416. if (result < target_min || result > target_max)
  417. return MODE_CLOCK_RANGE;
  418. return MODE_OK;
  419. }
  420. static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
  421. const struct drm_display_mode *mode,
  422. struct drm_display_mode *adjusted_mode)
  423. {
  424. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  425. int rate = mode->clock * 1000;
  426. if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
  427. DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
  428. return false;
  429. }
  430. adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
  431. DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
  432. mode->clock, adjusted_mode->clock);
  433. return true;
  434. }
  435. static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
  436. {
  437. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  438. struct drm_device *ddev = crtc->dev;
  439. struct drm_connector_list_iter iter;
  440. struct drm_connector *connector = NULL;
  441. struct drm_encoder *encoder = NULL;
  442. struct drm_bridge *bridge = NULL;
  443. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  444. struct videomode vm;
  445. u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
  446. u32 total_width, total_height;
  447. u32 bus_flags = 0;
  448. u32 val;
  449. int ret;
  450. /* get encoder from crtc */
  451. drm_for_each_encoder(encoder, ddev)
  452. if (encoder->crtc == crtc)
  453. break;
  454. if (encoder) {
  455. /* get bridge from encoder */
  456. list_for_each_entry(bridge, &encoder->bridge_chain, chain_node)
  457. if (bridge->encoder == encoder)
  458. break;
  459. /* Get the connector from encoder */
  460. drm_connector_list_iter_begin(ddev, &iter);
  461. drm_for_each_connector_iter(connector, &iter)
  462. if (connector->encoder == encoder)
  463. break;
  464. drm_connector_list_iter_end(&iter);
  465. }
  466. if (bridge && bridge->timings)
  467. bus_flags = bridge->timings->input_bus_flags;
  468. else if (connector)
  469. bus_flags = connector->display_info.bus_flags;
  470. if (!pm_runtime_active(ddev->dev)) {
  471. ret = pm_runtime_get_sync(ddev->dev);
  472. if (ret) {
  473. DRM_ERROR("Failed to set mode, cannot get sync\n");
  474. return;
  475. }
  476. }
  477. drm_display_mode_to_videomode(mode, &vm);
  478. DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
  479. DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
  480. DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
  481. vm.hfront_porch, vm.hback_porch, vm.hsync_len,
  482. vm.vfront_porch, vm.vback_porch, vm.vsync_len);
  483. /* Convert video timings to ltdc timings */
  484. hsync = vm.hsync_len - 1;
  485. vsync = vm.vsync_len - 1;
  486. accum_hbp = hsync + vm.hback_porch;
  487. accum_vbp = vsync + vm.vback_porch;
  488. accum_act_w = accum_hbp + vm.hactive;
  489. accum_act_h = accum_vbp + vm.vactive;
  490. total_width = accum_act_w + vm.hfront_porch;
  491. total_height = accum_act_h + vm.vfront_porch;
  492. /* Configures the HS, VS, DE and PC polarities. Default Active Low */
  493. val = 0;
  494. if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
  495. val |= GCR_HSPOL;
  496. if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
  497. val |= GCR_VSPOL;
  498. if (bus_flags & DRM_BUS_FLAG_DE_LOW)
  499. val |= GCR_DEPOL;
  500. if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
  501. val |= GCR_PCPOL;
  502. reg_update_bits(ldev->regs, LTDC_GCR,
  503. GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
  504. /* Set Synchronization size */
  505. val = (hsync << 16) | vsync;
  506. reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
  507. /* Set Accumulated Back porch */
  508. val = (accum_hbp << 16) | accum_vbp;
  509. reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
  510. /* Set Accumulated Active Width */
  511. val = (accum_act_w << 16) | accum_act_h;
  512. reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
  513. /* Set total width & height */
  514. val = (total_width << 16) | total_height;
  515. reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
  516. reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
  517. }
  518. static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
  519. struct drm_crtc_state *old_crtc_state)
  520. {
  521. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  522. struct drm_device *ddev = crtc->dev;
  523. struct drm_pending_vblank_event *event = crtc->state->event;
  524. DRM_DEBUG_ATOMIC("\n");
  525. ltdc_crtc_update_clut(crtc);
  526. /* Commit shadow registers = update planes at next vblank */
  527. reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
  528. if (event) {
  529. crtc->state->event = NULL;
  530. spin_lock_irq(&ddev->event_lock);
  531. if (drm_crtc_vblank_get(crtc) == 0)
  532. drm_crtc_arm_vblank_event(crtc, event);
  533. else
  534. drm_crtc_send_vblank_event(crtc, event);
  535. spin_unlock_irq(&ddev->event_lock);
  536. }
  537. }
  538. static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
  539. bool in_vblank_irq,
  540. int *vpos, int *hpos,
  541. ktime_t *stime, ktime_t *etime,
  542. const struct drm_display_mode *mode)
  543. {
  544. struct drm_device *ddev = crtc->dev;
  545. struct ltdc_device *ldev = ddev->dev_private;
  546. int line, vactive_start, vactive_end, vtotal;
  547. if (stime)
  548. *stime = ktime_get();
  549. /* The active area starts after vsync + front porch and ends
  550. * at vsync + front porc + display size.
  551. * The total height also include back porch.
  552. * We have 3 possible cases to handle:
  553. * - line < vactive_start: vpos = line - vactive_start and will be
  554. * negative
  555. * - vactive_start < line < vactive_end: vpos = line - vactive_start
  556. * and will be positive
  557. * - line > vactive_end: vpos = line - vtotal - vactive_start
  558. * and will negative
  559. *
  560. * Computation for the two first cases are identical so we can
  561. * simplify the code and only test if line > vactive_end
  562. */
  563. if (pm_runtime_active(ddev->dev)) {
  564. line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
  565. vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
  566. vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
  567. vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
  568. if (line > vactive_end)
  569. *vpos = line - vtotal - vactive_start;
  570. else
  571. *vpos = line - vactive_start;
  572. } else {
  573. *vpos = 0;
  574. }
  575. *hpos = 0;
  576. if (etime)
  577. *etime = ktime_get();
  578. return true;
  579. }
  580. static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
  581. .mode_valid = ltdc_crtc_mode_valid,
  582. .mode_fixup = ltdc_crtc_mode_fixup,
  583. .mode_set_nofb = ltdc_crtc_mode_set_nofb,
  584. .atomic_flush = ltdc_crtc_atomic_flush,
  585. .atomic_enable = ltdc_crtc_atomic_enable,
  586. .atomic_disable = ltdc_crtc_atomic_disable,
  587. .get_scanout_position = ltdc_crtc_get_scanout_position,
  588. };
  589. static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
  590. {
  591. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  592. struct drm_crtc_state *state = crtc->state;
  593. DRM_DEBUG_DRIVER("\n");
  594. if (state->enable)
  595. reg_set(ldev->regs, LTDC_IER, IER_LIE);
  596. else
  597. return -EPERM;
  598. return 0;
  599. }
  600. static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
  601. {
  602. struct ltdc_device *ldev = crtc_to_ltdc(crtc);
  603. DRM_DEBUG_DRIVER("\n");
  604. reg_clear(ldev->regs, LTDC_IER, IER_LIE);
  605. }
  606. static const struct drm_crtc_funcs ltdc_crtc_funcs = {
  607. .destroy = drm_crtc_cleanup,
  608. .set_config = drm_atomic_helper_set_config,
  609. .page_flip = drm_atomic_helper_page_flip,
  610. .reset = drm_atomic_helper_crtc_reset,
  611. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  612. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  613. .enable_vblank = ltdc_crtc_enable_vblank,
  614. .disable_vblank = ltdc_crtc_disable_vblank,
  615. .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
  616. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  617. };
  618. /*
  619. * DRM_PLANE
  620. */
  621. static int ltdc_plane_atomic_check(struct drm_plane *plane,
  622. struct drm_plane_state *state)
  623. {
  624. struct drm_framebuffer *fb = state->fb;
  625. u32 src_w, src_h;
  626. DRM_DEBUG_DRIVER("\n");
  627. if (!fb)
  628. return 0;
  629. /* convert src_ from 16:16 format */
  630. src_w = state->src_w >> 16;
  631. src_h = state->src_h >> 16;
  632. /* Reject scaling */
  633. if (src_w != state->crtc_w || src_h != state->crtc_h) {
  634. DRM_ERROR("Scaling is not supported");
  635. return -EINVAL;
  636. }
  637. return 0;
  638. }
  639. static void ltdc_plane_atomic_update(struct drm_plane *plane,
  640. struct drm_plane_state *oldstate)
  641. {
  642. struct ltdc_device *ldev = plane_to_ltdc(plane);
  643. struct drm_plane_state *state = plane->state;
  644. struct drm_framebuffer *fb = state->fb;
  645. u32 lofs = plane->index * LAY_OFS;
  646. u32 x0 = state->crtc_x;
  647. u32 x1 = state->crtc_x + state->crtc_w - 1;
  648. u32 y0 = state->crtc_y;
  649. u32 y1 = state->crtc_y + state->crtc_h - 1;
  650. u32 src_x, src_y, src_w, src_h;
  651. u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
  652. enum ltdc_pix_fmt pf;
  653. if (!state->crtc || !fb) {
  654. DRM_DEBUG_DRIVER("fb or crtc NULL");
  655. return;
  656. }
  657. /* convert src_ from 16:16 format */
  658. src_x = state->src_x >> 16;
  659. src_y = state->src_y >> 16;
  660. src_w = state->src_w >> 16;
  661. src_h = state->src_h >> 16;
  662. DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
  663. plane->base.id, fb->base.id,
  664. src_w, src_h, src_x, src_y,
  665. state->crtc_w, state->crtc_h,
  666. state->crtc_x, state->crtc_y);
  667. bpcr = reg_read(ldev->regs, LTDC_BPCR);
  668. ahbp = (bpcr & BPCR_AHBP) >> 16;
  669. avbp = bpcr & BPCR_AVBP;
  670. /* Configures the horizontal start and stop position */
  671. val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
  672. reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
  673. LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
  674. /* Configures the vertical start and stop position */
  675. val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
  676. reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
  677. LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
  678. /* Specifies the pixel format */
  679. pf = to_ltdc_pixelformat(fb->format->format);
  680. for (val = 0; val < NB_PF; val++)
  681. if (ldev->caps.pix_fmt_hw[val] == pf)
  682. break;
  683. if (val == NB_PF) {
  684. DRM_ERROR("Pixel format %.4s not supported\n",
  685. (char *)&fb->format->format);
  686. val = 0; /* set by default ARGB 32 bits */
  687. }
  688. reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
  689. /* Configures the color frame buffer pitch in bytes & line length */
  690. pitch_in_bytes = fb->pitches[0];
  691. line_length = fb->format->cpp[0] *
  692. (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
  693. val = ((pitch_in_bytes << 16) | line_length);
  694. reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
  695. LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
  696. /* Specifies the constant alpha value */
  697. val = CONSTA_MAX;
  698. reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
  699. /* Specifies the blending factors */
  700. val = BF1_PAXCA | BF2_1PAXCA;
  701. if (!fb->format->has_alpha)
  702. val = BF1_CA | BF2_1CA;
  703. /* Manage hw-specific capabilities */
  704. if (ldev->caps.non_alpha_only_l1 &&
  705. plane->type != DRM_PLANE_TYPE_PRIMARY)
  706. val = BF1_PAXCA | BF2_1PAXCA;
  707. reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
  708. LXBFCR_BF2 | LXBFCR_BF1, val);
  709. /* Configures the frame buffer line number */
  710. val = y1 - y0 + 1;
  711. reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val);
  712. /* Sets the FB address */
  713. paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
  714. DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
  715. reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
  716. /* Enable layer and CLUT if needed */
  717. val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
  718. val |= LXCR_LEN;
  719. reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
  720. LXCR_LEN | LXCR_CLUTEN, val);
  721. ldev->plane_fpsi[plane->index].counter++;
  722. mutex_lock(&ldev->err_lock);
  723. if (ldev->error_status & ISR_FUIF) {
  724. DRM_WARN("ltdc fifo underrun: please verify display mode\n");
  725. ldev->error_status &= ~ISR_FUIF;
  726. }
  727. if (ldev->error_status & ISR_TERRIF) {
  728. DRM_WARN("ltdc transfer error\n");
  729. ldev->error_status &= ~ISR_TERRIF;
  730. }
  731. mutex_unlock(&ldev->err_lock);
  732. }
  733. static void ltdc_plane_atomic_disable(struct drm_plane *plane,
  734. struct drm_plane_state *oldstate)
  735. {
  736. struct ltdc_device *ldev = plane_to_ltdc(plane);
  737. u32 lofs = plane->index * LAY_OFS;
  738. /* disable layer */
  739. reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
  740. DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
  741. oldstate->crtc->base.id, plane->base.id);
  742. }
  743. static void ltdc_plane_atomic_print_state(struct drm_printer *p,
  744. const struct drm_plane_state *state)
  745. {
  746. struct drm_plane *plane = state->plane;
  747. struct ltdc_device *ldev = plane_to_ltdc(plane);
  748. struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
  749. int ms_since_last;
  750. ktime_t now;
  751. now = ktime_get();
  752. ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
  753. drm_printf(p, "\tuser_updates=%dfps\n",
  754. DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
  755. fpsi->last_timestamp = now;
  756. fpsi->counter = 0;
  757. }
  758. static bool ltdc_plane_format_mod_supported(struct drm_plane *plane,
  759. u32 format,
  760. u64 modifier)
  761. {
  762. if (modifier == DRM_FORMAT_MOD_LINEAR)
  763. return true;
  764. return false;
  765. }
  766. static const struct drm_plane_funcs ltdc_plane_funcs = {
  767. .update_plane = drm_atomic_helper_update_plane,
  768. .disable_plane = drm_atomic_helper_disable_plane,
  769. .destroy = drm_plane_cleanup,
  770. .reset = drm_atomic_helper_plane_reset,
  771. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  772. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  773. .atomic_print_state = ltdc_plane_atomic_print_state,
  774. .format_mod_supported = ltdc_plane_format_mod_supported,
  775. };
  776. static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
  777. .prepare_fb = drm_gem_fb_prepare_fb,
  778. .atomic_check = ltdc_plane_atomic_check,
  779. .atomic_update = ltdc_plane_atomic_update,
  780. .atomic_disable = ltdc_plane_atomic_disable,
  781. };
  782. static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
  783. enum drm_plane_type type)
  784. {
  785. unsigned long possible_crtcs = CRTC_MASK;
  786. struct ltdc_device *ldev = ddev->dev_private;
  787. struct device *dev = ddev->dev;
  788. struct drm_plane *plane;
  789. unsigned int i, nb_fmt = 0;
  790. u32 formats[NB_PF * 2];
  791. u32 drm_fmt, drm_fmt_no_alpha;
  792. const u64 *modifiers = ltdc_format_modifiers;
  793. int ret;
  794. /* Get supported pixel formats */
  795. for (i = 0; i < NB_PF; i++) {
  796. drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
  797. if (!drm_fmt)
  798. continue;
  799. formats[nb_fmt++] = drm_fmt;
  800. /* Add the no-alpha related format if any & supported */
  801. drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt);
  802. if (!drm_fmt_no_alpha)
  803. continue;
  804. /* Manage hw-specific capabilities */
  805. if (ldev->caps.non_alpha_only_l1 &&
  806. type != DRM_PLANE_TYPE_PRIMARY)
  807. continue;
  808. formats[nb_fmt++] = drm_fmt_no_alpha;
  809. }
  810. plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
  811. if (!plane)
  812. return NULL;
  813. ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
  814. &ltdc_plane_funcs, formats, nb_fmt,
  815. modifiers, type, NULL);
  816. if (ret < 0)
  817. return NULL;
  818. drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
  819. DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
  820. return plane;
  821. }
  822. static void ltdc_plane_destroy_all(struct drm_device *ddev)
  823. {
  824. struct drm_plane *plane, *plane_temp;
  825. list_for_each_entry_safe(plane, plane_temp,
  826. &ddev->mode_config.plane_list, head)
  827. drm_plane_cleanup(plane);
  828. }
  829. static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
  830. {
  831. struct ltdc_device *ldev = ddev->dev_private;
  832. struct drm_plane *primary, *overlay;
  833. unsigned int i;
  834. int ret;
  835. primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
  836. if (!primary) {
  837. DRM_ERROR("Can not create primary plane\n");
  838. return -EINVAL;
  839. }
  840. ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
  841. &ltdc_crtc_funcs, NULL);
  842. if (ret) {
  843. DRM_ERROR("Can not initialize CRTC\n");
  844. goto cleanup;
  845. }
  846. drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
  847. drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
  848. drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
  849. DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
  850. /* Add planes. Note : the first layer is used by primary plane */
  851. for (i = 1; i < ldev->caps.nb_layers; i++) {
  852. overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
  853. if (!overlay) {
  854. ret = -ENOMEM;
  855. DRM_ERROR("Can not create overlay plane %d\n", i);
  856. goto cleanup;
  857. }
  858. }
  859. return 0;
  860. cleanup:
  861. ltdc_plane_destroy_all(ddev);
  862. return ret;
  863. }
  864. /*
  865. * DRM_ENCODER
  866. */
  867. static const struct drm_encoder_funcs ltdc_encoder_funcs = {
  868. .destroy = drm_encoder_cleanup,
  869. };
  870. static void ltdc_encoder_disable(struct drm_encoder *encoder)
  871. {
  872. struct drm_device *ddev = encoder->dev;
  873. struct ltdc_device *ldev = ddev->dev_private;
  874. DRM_DEBUG_DRIVER("\n");
  875. /* Disable LTDC */
  876. reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
  877. /* Set to sleep state the pinctrl whatever type of encoder */
  878. pinctrl_pm_select_sleep_state(ddev->dev);
  879. }
  880. static void ltdc_encoder_enable(struct drm_encoder *encoder)
  881. {
  882. struct drm_device *ddev = encoder->dev;
  883. struct ltdc_device *ldev = ddev->dev_private;
  884. DRM_DEBUG_DRIVER("\n");
  885. /* Enable LTDC */
  886. reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
  887. }
  888. static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
  889. struct drm_display_mode *mode,
  890. struct drm_display_mode *adjusted_mode)
  891. {
  892. struct drm_device *ddev = encoder->dev;
  893. DRM_DEBUG_DRIVER("\n");
  894. /*
  895. * Set to default state the pinctrl only with DPI type.
  896. * Others types like DSI, don't need pinctrl due to
  897. * internal bridge (the signals do not come out of the chipset).
  898. */
  899. if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
  900. pinctrl_pm_select_default_state(ddev->dev);
  901. }
  902. static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
  903. .disable = ltdc_encoder_disable,
  904. .enable = ltdc_encoder_enable,
  905. .mode_set = ltdc_encoder_mode_set,
  906. };
  907. static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
  908. {
  909. struct drm_encoder *encoder;
  910. int ret;
  911. encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
  912. if (!encoder)
  913. return -ENOMEM;
  914. encoder->possible_crtcs = CRTC_MASK;
  915. encoder->possible_clones = 0; /* No cloning support */
  916. drm_encoder_init(ddev, encoder, &ltdc_encoder_funcs,
  917. DRM_MODE_ENCODER_DPI, NULL);
  918. drm_encoder_helper_add(encoder, &ltdc_encoder_helper_funcs);
  919. ret = drm_bridge_attach(encoder, bridge, NULL, 0);
  920. if (ret) {
  921. drm_encoder_cleanup(encoder);
  922. return -EINVAL;
  923. }
  924. DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
  925. return 0;
  926. }
  927. static int ltdc_get_caps(struct drm_device *ddev)
  928. {
  929. struct ltdc_device *ldev = ddev->dev_private;
  930. u32 bus_width_log2, lcr, gc2r;
  931. /*
  932. * at least 1 layer must be managed & the number of layers
  933. * must not exceed LTDC_MAX_LAYER
  934. */
  935. lcr = reg_read(ldev->regs, LTDC_LCR);
  936. ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
  937. /* set data bus width */
  938. gc2r = reg_read(ldev->regs, LTDC_GC2R);
  939. bus_width_log2 = (gc2r & GC2R_BW) >> 4;
  940. ldev->caps.bus_width = 8 << bus_width_log2;
  941. ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
  942. switch (ldev->caps.hw_version) {
  943. case HWVER_10200:
  944. case HWVER_10300:
  945. ldev->caps.reg_ofs = REG_OFS_NONE;
  946. ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
  947. /*
  948. * Hw older versions support non-alpha color formats derived
  949. * from native alpha color formats only on the primary layer.
  950. * For instance, RG16 native format without alpha works fine
  951. * on 2nd layer but XR24 (derived color format from AR24)
  952. * does not work on 2nd layer.
  953. */
  954. ldev->caps.non_alpha_only_l1 = true;
  955. ldev->caps.pad_max_freq_hz = 90000000;
  956. if (ldev->caps.hw_version == HWVER_10200)
  957. ldev->caps.pad_max_freq_hz = 65000000;
  958. ldev->caps.nb_irq = 2;
  959. break;
  960. case HWVER_20101:
  961. ldev->caps.reg_ofs = REG_OFS_4;
  962. ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
  963. ldev->caps.non_alpha_only_l1 = false;
  964. ldev->caps.pad_max_freq_hz = 150000000;
  965. ldev->caps.nb_irq = 4;
  966. break;
  967. default:
  968. return -ENODEV;
  969. }
  970. return 0;
  971. }
  972. void ltdc_suspend(struct drm_device *ddev)
  973. {
  974. struct ltdc_device *ldev = ddev->dev_private;
  975. DRM_DEBUG_DRIVER("\n");
  976. clk_disable_unprepare(ldev->pixel_clk);
  977. }
  978. int ltdc_resume(struct drm_device *ddev)
  979. {
  980. struct ltdc_device *ldev = ddev->dev_private;
  981. int ret;
  982. DRM_DEBUG_DRIVER("\n");
  983. ret = clk_prepare_enable(ldev->pixel_clk);
  984. if (ret) {
  985. DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
  986. return ret;
  987. }
  988. return 0;
  989. }
  990. int ltdc_load(struct drm_device *ddev)
  991. {
  992. struct platform_device *pdev = to_platform_device(ddev->dev);
  993. struct ltdc_device *ldev = ddev->dev_private;
  994. struct device *dev = ddev->dev;
  995. struct device_node *np = dev->of_node;
  996. struct drm_bridge *bridge;
  997. struct drm_panel *panel;
  998. struct drm_crtc *crtc;
  999. struct reset_control *rstc;
  1000. struct resource *res;
  1001. int irq, i, nb_endpoints;
  1002. int ret = -ENODEV;
  1003. DRM_DEBUG_DRIVER("\n");
  1004. /* Get number of endpoints */
  1005. nb_endpoints = of_graph_get_endpoint_count(np);
  1006. if (!nb_endpoints)
  1007. return -ENODEV;
  1008. ldev->pixel_clk = devm_clk_get(dev, "lcd");
  1009. if (IS_ERR(ldev->pixel_clk)) {
  1010. if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
  1011. DRM_ERROR("Unable to get lcd clock\n");
  1012. return PTR_ERR(ldev->pixel_clk);
  1013. }
  1014. if (clk_prepare_enable(ldev->pixel_clk)) {
  1015. DRM_ERROR("Unable to prepare pixel clock\n");
  1016. return -ENODEV;
  1017. }
  1018. /* Get endpoints if any */
  1019. for (i = 0; i < nb_endpoints; i++) {
  1020. ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
  1021. /*
  1022. * If at least one endpoint is -ENODEV, continue probing,
  1023. * else if at least one endpoint returned an error
  1024. * (ie -EPROBE_DEFER) then stop probing.
  1025. */
  1026. if (ret == -ENODEV)
  1027. continue;
  1028. else if (ret)
  1029. goto err;
  1030. if (panel) {
  1031. bridge = drm_panel_bridge_add_typed(panel,
  1032. DRM_MODE_CONNECTOR_DPI);
  1033. if (IS_ERR(bridge)) {
  1034. DRM_ERROR("panel-bridge endpoint %d\n", i);
  1035. ret = PTR_ERR(bridge);
  1036. goto err;
  1037. }
  1038. }
  1039. if (bridge) {
  1040. ret = ltdc_encoder_init(ddev, bridge);
  1041. if (ret) {
  1042. DRM_ERROR("init encoder endpoint %d\n", i);
  1043. goto err;
  1044. }
  1045. }
  1046. }
  1047. rstc = devm_reset_control_get_exclusive(dev, NULL);
  1048. mutex_init(&ldev->err_lock);
  1049. if (!IS_ERR(rstc)) {
  1050. reset_control_assert(rstc);
  1051. usleep_range(10, 20);
  1052. reset_control_deassert(rstc);
  1053. }
  1054. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1055. ldev->regs = devm_ioremap_resource(dev, res);
  1056. if (IS_ERR(ldev->regs)) {
  1057. DRM_ERROR("Unable to get ltdc registers\n");
  1058. ret = PTR_ERR(ldev->regs);
  1059. goto err;
  1060. }
  1061. /* Disable interrupts */
  1062. reg_clear(ldev->regs, LTDC_IER,
  1063. IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
  1064. ret = ltdc_get_caps(ddev);
  1065. if (ret) {
  1066. DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
  1067. ldev->caps.hw_version);
  1068. goto err;
  1069. }
  1070. DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
  1071. for (i = 0; i < ldev->caps.nb_irq; i++) {
  1072. irq = platform_get_irq(pdev, i);
  1073. if (irq < 0) {
  1074. ret = irq;
  1075. goto err;
  1076. }
  1077. ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
  1078. ltdc_irq_thread, IRQF_ONESHOT,
  1079. dev_name(dev), ddev);
  1080. if (ret) {
  1081. DRM_ERROR("Failed to register LTDC interrupt\n");
  1082. goto err;
  1083. }
  1084. }
  1085. crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
  1086. if (!crtc) {
  1087. DRM_ERROR("Failed to allocate crtc\n");
  1088. ret = -ENOMEM;
  1089. goto err;
  1090. }
  1091. ddev->mode_config.allow_fb_modifiers = true;
  1092. ret = ltdc_crtc_init(ddev, crtc);
  1093. if (ret) {
  1094. DRM_ERROR("Failed to init crtc\n");
  1095. goto err;
  1096. }
  1097. ret = drm_vblank_init(ddev, NB_CRTC);
  1098. if (ret) {
  1099. DRM_ERROR("Failed calling drm_vblank_init()\n");
  1100. goto err;
  1101. }
  1102. /* Allow usage of vblank without having to call drm_irq_install */
  1103. ddev->irq_enabled = 1;
  1104. clk_disable_unprepare(ldev->pixel_clk);
  1105. pinctrl_pm_select_sleep_state(ddev->dev);
  1106. pm_runtime_enable(ddev->dev);
  1107. return 0;
  1108. err:
  1109. for (i = 0; i < nb_endpoints; i++)
  1110. drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
  1111. clk_disable_unprepare(ldev->pixel_clk);
  1112. return ret;
  1113. }
  1114. void ltdc_unload(struct drm_device *ddev)
  1115. {
  1116. struct device *dev = ddev->dev;
  1117. int nb_endpoints, i;
  1118. DRM_DEBUG_DRIVER("\n");
  1119. nb_endpoints = of_graph_get_endpoint_count(dev->of_node);
  1120. for (i = 0; i < nb_endpoints; i++)
  1121. drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
  1122. pm_runtime_disable(ddev->dev);
  1123. }
  1124. MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
  1125. MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
  1126. MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
  1127. MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
  1128. MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
  1129. MODULE_LICENSE("GPL v2");