sti_gdp.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2014
  4. * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
  5. * Fabien Dessenne <fabien.dessenne@st.com>
  6. * for STMicroelectronics.
  7. */
  8. #include <linux/dma-mapping.h>
  9. #include <linux/seq_file.h>
  10. #include <drm/drm_atomic.h>
  11. #include <drm/drm_device.h>
  12. #include <drm/drm_fb_cma_helper.h>
  13. #include <drm/drm_fourcc.h>
  14. #include <drm/drm_gem_cma_helper.h>
  15. #include "sti_compositor.h"
  16. #include "sti_gdp.h"
  17. #include "sti_plane.h"
  18. #include "sti_vtg.h"
  19. #define ALPHASWITCH BIT(6)
  20. #define ENA_COLOR_FILL BIT(8)
  21. #define BIGNOTLITTLE BIT(23)
  22. #define WAIT_NEXT_VSYNC BIT(31)
  23. /* GDP color formats */
  24. #define GDP_RGB565 0x00
  25. #define GDP_RGB888 0x01
  26. #define GDP_RGB888_32 0x02
  27. #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
  28. #define GDP_ARGB8565 0x04
  29. #define GDP_ARGB8888 0x05
  30. #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
  31. #define GDP_ARGB1555 0x06
  32. #define GDP_ARGB4444 0x07
  33. #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
  34. static struct gdp_format_to_str {
  35. int format;
  36. char name[20];
  37. } gdp_format_to_str[] = {
  38. GDP2STR(RGB565),
  39. GDP2STR(RGB888),
  40. GDP2STR(RGB888_32),
  41. GDP2STR(XBGR8888),
  42. GDP2STR(ARGB8565),
  43. GDP2STR(ARGB8888),
  44. GDP2STR(ABGR8888),
  45. GDP2STR(ARGB1555),
  46. GDP2STR(ARGB4444)
  47. };
  48. #define GAM_GDP_CTL_OFFSET 0x00
  49. #define GAM_GDP_AGC_OFFSET 0x04
  50. #define GAM_GDP_VPO_OFFSET 0x0C
  51. #define GAM_GDP_VPS_OFFSET 0x10
  52. #define GAM_GDP_PML_OFFSET 0x14
  53. #define GAM_GDP_PMP_OFFSET 0x18
  54. #define GAM_GDP_SIZE_OFFSET 0x1C
  55. #define GAM_GDP_NVN_OFFSET 0x24
  56. #define GAM_GDP_KEY1_OFFSET 0x28
  57. #define GAM_GDP_KEY2_OFFSET 0x2C
  58. #define GAM_GDP_PPT_OFFSET 0x34
  59. #define GAM_GDP_CML_OFFSET 0x3C
  60. #define GAM_GDP_MST_OFFSET 0x68
  61. #define GAM_GDP_ALPHARANGE_255 BIT(5)
  62. #define GAM_GDP_AGC_FULL_RANGE 0x00808080
  63. #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
  64. #define GAM_GDP_SIZE_MAX_WIDTH 3840
  65. #define GAM_GDP_SIZE_MAX_HEIGHT 2160
  66. #define GDP_NODE_NB_BANK 2
  67. #define GDP_NODE_PER_FIELD 2
  68. struct sti_gdp_node {
  69. u32 gam_gdp_ctl;
  70. u32 gam_gdp_agc;
  71. u32 reserved1;
  72. u32 gam_gdp_vpo;
  73. u32 gam_gdp_vps;
  74. u32 gam_gdp_pml;
  75. u32 gam_gdp_pmp;
  76. u32 gam_gdp_size;
  77. u32 reserved2;
  78. u32 gam_gdp_nvn;
  79. u32 gam_gdp_key1;
  80. u32 gam_gdp_key2;
  81. u32 reserved3;
  82. u32 gam_gdp_ppt;
  83. u32 reserved4;
  84. u32 gam_gdp_cml;
  85. };
  86. struct sti_gdp_node_list {
  87. struct sti_gdp_node *top_field;
  88. dma_addr_t top_field_paddr;
  89. struct sti_gdp_node *btm_field;
  90. dma_addr_t btm_field_paddr;
  91. };
  92. /*
  93. * STI GDP structure
  94. *
  95. * @sti_plane: sti_plane structure
  96. * @dev: driver device
  97. * @regs: gdp registers
  98. * @clk_pix: pixel clock for the current gdp
  99. * @clk_main_parent: gdp parent clock if main path used
  100. * @clk_aux_parent: gdp parent clock if aux path used
  101. * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
  102. * @is_curr_top: true if the current node processed is the top field
  103. * @node_list: array of node list
  104. * @vtg: registered vtg
  105. */
  106. struct sti_gdp {
  107. struct sti_plane plane;
  108. struct device *dev;
  109. void __iomem *regs;
  110. struct clk *clk_pix;
  111. struct clk *clk_main_parent;
  112. struct clk *clk_aux_parent;
  113. struct notifier_block vtg_field_nb;
  114. bool is_curr_top;
  115. struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
  116. struct sti_vtg *vtg;
  117. };
  118. #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
  119. static const uint32_t gdp_supported_formats[] = {
  120. DRM_FORMAT_XRGB8888,
  121. DRM_FORMAT_XBGR8888,
  122. DRM_FORMAT_ARGB8888,
  123. DRM_FORMAT_ABGR8888,
  124. DRM_FORMAT_ARGB4444,
  125. DRM_FORMAT_ARGB1555,
  126. DRM_FORMAT_RGB565,
  127. DRM_FORMAT_RGB888,
  128. };
  129. #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
  130. readl(gdp->regs + reg ## _OFFSET))
  131. static void gdp_dbg_ctl(struct seq_file *s, int val)
  132. {
  133. int i;
  134. seq_puts(s, "\tColor:");
  135. for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
  136. if (gdp_format_to_str[i].format == (val & 0x1F)) {
  137. seq_puts(s, gdp_format_to_str[i].name);
  138. break;
  139. }
  140. }
  141. if (i == ARRAY_SIZE(gdp_format_to_str))
  142. seq_puts(s, "<UNKNOWN>");
  143. seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
  144. }
  145. static void gdp_dbg_vpo(struct seq_file *s, int val)
  146. {
  147. seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
  148. }
  149. static void gdp_dbg_vps(struct seq_file *s, int val)
  150. {
  151. seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
  152. }
  153. static void gdp_dbg_size(struct seq_file *s, int val)
  154. {
  155. seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
  156. }
  157. static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
  158. {
  159. void *base = NULL;
  160. unsigned int i;
  161. for (i = 0; i < GDP_NODE_NB_BANK; i++) {
  162. if (gdp->node_list[i].top_field_paddr == val) {
  163. base = gdp->node_list[i].top_field;
  164. break;
  165. }
  166. if (gdp->node_list[i].btm_field_paddr == val) {
  167. base = gdp->node_list[i].btm_field;
  168. break;
  169. }
  170. }
  171. if (base)
  172. seq_printf(s, "\tVirt @: %p", base);
  173. }
  174. static void gdp_dbg_ppt(struct seq_file *s, int val)
  175. {
  176. if (val & GAM_GDP_PPT_IGNORE)
  177. seq_puts(s, "\tNot displayed on mixer!");
  178. }
  179. static void gdp_dbg_mst(struct seq_file *s, int val)
  180. {
  181. if (val & 1)
  182. seq_puts(s, "\tBUFFER UNDERFLOW!");
  183. }
  184. static int gdp_dbg_show(struct seq_file *s, void *data)
  185. {
  186. struct drm_info_node *node = s->private;
  187. struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
  188. struct drm_plane *drm_plane = &gdp->plane.drm_plane;
  189. struct drm_crtc *crtc;
  190. drm_modeset_lock(&drm_plane->mutex, NULL);
  191. crtc = drm_plane->state->crtc;
  192. drm_modeset_unlock(&drm_plane->mutex);
  193. seq_printf(s, "%s: (vaddr = 0x%p)",
  194. sti_plane_to_str(&gdp->plane), gdp->regs);
  195. DBGFS_DUMP(GAM_GDP_CTL);
  196. gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
  197. DBGFS_DUMP(GAM_GDP_AGC);
  198. DBGFS_DUMP(GAM_GDP_VPO);
  199. gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
  200. DBGFS_DUMP(GAM_GDP_VPS);
  201. gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
  202. DBGFS_DUMP(GAM_GDP_PML);
  203. DBGFS_DUMP(GAM_GDP_PMP);
  204. DBGFS_DUMP(GAM_GDP_SIZE);
  205. gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
  206. DBGFS_DUMP(GAM_GDP_NVN);
  207. gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
  208. DBGFS_DUMP(GAM_GDP_KEY1);
  209. DBGFS_DUMP(GAM_GDP_KEY2);
  210. DBGFS_DUMP(GAM_GDP_PPT);
  211. gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
  212. DBGFS_DUMP(GAM_GDP_CML);
  213. DBGFS_DUMP(GAM_GDP_MST);
  214. gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
  215. seq_puts(s, "\n\n");
  216. if (!crtc)
  217. seq_puts(s, " Not connected to any DRM CRTC\n");
  218. else
  219. seq_printf(s, " Connected to DRM CRTC #%d (%s)\n",
  220. crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
  221. return 0;
  222. }
  223. static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
  224. {
  225. seq_printf(s, "\t@:0x%p", node);
  226. seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl);
  227. gdp_dbg_ctl(s, node->gam_gdp_ctl);
  228. seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc);
  229. seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo);
  230. gdp_dbg_vpo(s, node->gam_gdp_vpo);
  231. seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps);
  232. gdp_dbg_vps(s, node->gam_gdp_vps);
  233. seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml);
  234. seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp);
  235. seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
  236. gdp_dbg_size(s, node->gam_gdp_size);
  237. seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn);
  238. seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
  239. seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
  240. seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt);
  241. gdp_dbg_ppt(s, node->gam_gdp_ppt);
  242. seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml);
  243. }
  244. static int gdp_node_dbg_show(struct seq_file *s, void *arg)
  245. {
  246. struct drm_info_node *node = s->private;
  247. struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
  248. unsigned int b;
  249. for (b = 0; b < GDP_NODE_NB_BANK; b++) {
  250. seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
  251. gdp_node_dump_node(s, gdp->node_list[b].top_field);
  252. seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
  253. gdp_node_dump_node(s, gdp->node_list[b].btm_field);
  254. }
  255. return 0;
  256. }
  257. static struct drm_info_list gdp0_debugfs_files[] = {
  258. { "gdp0", gdp_dbg_show, 0, NULL },
  259. { "gdp0_node", gdp_node_dbg_show, 0, NULL },
  260. };
  261. static struct drm_info_list gdp1_debugfs_files[] = {
  262. { "gdp1", gdp_dbg_show, 0, NULL },
  263. { "gdp1_node", gdp_node_dbg_show, 0, NULL },
  264. };
  265. static struct drm_info_list gdp2_debugfs_files[] = {
  266. { "gdp2", gdp_dbg_show, 0, NULL },
  267. { "gdp2_node", gdp_node_dbg_show, 0, NULL },
  268. };
  269. static struct drm_info_list gdp3_debugfs_files[] = {
  270. { "gdp3", gdp_dbg_show, 0, NULL },
  271. { "gdp3_node", gdp_node_dbg_show, 0, NULL },
  272. };
  273. static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
  274. {
  275. unsigned int i;
  276. struct drm_info_list *gdp_debugfs_files;
  277. int nb_files;
  278. switch (gdp->plane.desc) {
  279. case STI_GDP_0:
  280. gdp_debugfs_files = gdp0_debugfs_files;
  281. nb_files = ARRAY_SIZE(gdp0_debugfs_files);
  282. break;
  283. case STI_GDP_1:
  284. gdp_debugfs_files = gdp1_debugfs_files;
  285. nb_files = ARRAY_SIZE(gdp1_debugfs_files);
  286. break;
  287. case STI_GDP_2:
  288. gdp_debugfs_files = gdp2_debugfs_files;
  289. nb_files = ARRAY_SIZE(gdp2_debugfs_files);
  290. break;
  291. case STI_GDP_3:
  292. gdp_debugfs_files = gdp3_debugfs_files;
  293. nb_files = ARRAY_SIZE(gdp3_debugfs_files);
  294. break;
  295. default:
  296. return -EINVAL;
  297. }
  298. for (i = 0; i < nb_files; i++)
  299. gdp_debugfs_files[i].data = gdp;
  300. drm_debugfs_create_files(gdp_debugfs_files,
  301. nb_files,
  302. minor->debugfs_root, minor);
  303. return 0;
  304. }
  305. static int sti_gdp_fourcc2format(int fourcc)
  306. {
  307. switch (fourcc) {
  308. case DRM_FORMAT_XRGB8888:
  309. return GDP_RGB888_32;
  310. case DRM_FORMAT_XBGR8888:
  311. return GDP_XBGR8888;
  312. case DRM_FORMAT_ARGB8888:
  313. return GDP_ARGB8888;
  314. case DRM_FORMAT_ABGR8888:
  315. return GDP_ABGR8888;
  316. case DRM_FORMAT_ARGB4444:
  317. return GDP_ARGB4444;
  318. case DRM_FORMAT_ARGB1555:
  319. return GDP_ARGB1555;
  320. case DRM_FORMAT_RGB565:
  321. return GDP_RGB565;
  322. case DRM_FORMAT_RGB888:
  323. return GDP_RGB888;
  324. }
  325. return -1;
  326. }
  327. static int sti_gdp_get_alpharange(int format)
  328. {
  329. switch (format) {
  330. case GDP_ARGB8565:
  331. case GDP_ARGB8888:
  332. case GDP_ABGR8888:
  333. return GAM_GDP_ALPHARANGE_255;
  334. }
  335. return 0;
  336. }
  337. /**
  338. * sti_gdp_get_free_nodes
  339. * @gdp: gdp pointer
  340. *
  341. * Look for a GDP node list that is not currently read by the HW.
  342. *
  343. * RETURNS:
  344. * Pointer to the free GDP node list
  345. */
  346. static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
  347. {
  348. int hw_nvn;
  349. unsigned int i;
  350. hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
  351. if (!hw_nvn)
  352. goto end;
  353. for (i = 0; i < GDP_NODE_NB_BANK; i++)
  354. if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
  355. (hw_nvn != gdp->node_list[i].top_field_paddr))
  356. return &gdp->node_list[i];
  357. /* in hazardious cases restart with the first node */
  358. DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
  359. sti_plane_to_str(&gdp->plane), hw_nvn);
  360. end:
  361. return &gdp->node_list[0];
  362. }
  363. /**
  364. * sti_gdp_get_current_nodes
  365. * @gdp: gdp pointer
  366. *
  367. * Look for GDP nodes that are currently read by the HW.
  368. *
  369. * RETURNS:
  370. * Pointer to the current GDP node list
  371. */
  372. static
  373. struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
  374. {
  375. int hw_nvn;
  376. unsigned int i;
  377. hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
  378. if (!hw_nvn)
  379. goto end;
  380. for (i = 0; i < GDP_NODE_NB_BANK; i++)
  381. if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
  382. (hw_nvn == gdp->node_list[i].top_field_paddr))
  383. return &gdp->node_list[i];
  384. end:
  385. DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
  386. hw_nvn, sti_plane_to_str(&gdp->plane));
  387. return NULL;
  388. }
  389. /**
  390. * sti_gdp_disable
  391. * @gdp: gdp pointer
  392. *
  393. * Disable a GDP.
  394. */
  395. static void sti_gdp_disable(struct sti_gdp *gdp)
  396. {
  397. unsigned int i;
  398. DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
  399. /* Set the nodes as 'to be ignored on mixer' */
  400. for (i = 0; i < GDP_NODE_NB_BANK; i++) {
  401. gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
  402. gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
  403. }
  404. if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
  405. DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
  406. if (gdp->clk_pix)
  407. clk_disable_unprepare(gdp->clk_pix);
  408. gdp->plane.status = STI_PLANE_DISABLED;
  409. gdp->vtg = NULL;
  410. }
  411. /**
  412. * sti_gdp_field_cb
  413. * @nb: notifier block
  414. * @event: event message
  415. * @data: private data
  416. *
  417. * Handle VTG top field and bottom field event.
  418. *
  419. * RETURNS:
  420. * 0 on success.
  421. */
  422. static int sti_gdp_field_cb(struct notifier_block *nb,
  423. unsigned long event, void *data)
  424. {
  425. struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
  426. if (gdp->plane.status == STI_PLANE_FLUSHING) {
  427. /* disable need to be synchronize on vsync event */
  428. DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
  429. sti_plane_to_str(&gdp->plane));
  430. sti_gdp_disable(gdp);
  431. }
  432. switch (event) {
  433. case VTG_TOP_FIELD_EVENT:
  434. gdp->is_curr_top = true;
  435. break;
  436. case VTG_BOTTOM_FIELD_EVENT:
  437. gdp->is_curr_top = false;
  438. break;
  439. default:
  440. DRM_ERROR("unsupported event: %lu\n", event);
  441. break;
  442. }
  443. return 0;
  444. }
  445. static void sti_gdp_init(struct sti_gdp *gdp)
  446. {
  447. struct device_node *np = gdp->dev->of_node;
  448. dma_addr_t dma_addr;
  449. void *base;
  450. unsigned int i, size;
  451. /* Allocate all the nodes within a single memory page */
  452. size = sizeof(struct sti_gdp_node) *
  453. GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
  454. base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL);
  455. if (!base) {
  456. DRM_ERROR("Failed to allocate memory for GDP node\n");
  457. return;
  458. }
  459. memset(base, 0, size);
  460. for (i = 0; i < GDP_NODE_NB_BANK; i++) {
  461. if (dma_addr & 0xF) {
  462. DRM_ERROR("Mem alignment failed\n");
  463. return;
  464. }
  465. gdp->node_list[i].top_field = base;
  466. gdp->node_list[i].top_field_paddr = dma_addr;
  467. DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
  468. base += sizeof(struct sti_gdp_node);
  469. dma_addr += sizeof(struct sti_gdp_node);
  470. if (dma_addr & 0xF) {
  471. DRM_ERROR("Mem alignment failed\n");
  472. return;
  473. }
  474. gdp->node_list[i].btm_field = base;
  475. gdp->node_list[i].btm_field_paddr = dma_addr;
  476. DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
  477. base += sizeof(struct sti_gdp_node);
  478. dma_addr += sizeof(struct sti_gdp_node);
  479. }
  480. if (of_device_is_compatible(np, "st,stih407-compositor")) {
  481. /* GDP of STiH407 chip have its own pixel clock */
  482. char *clk_name;
  483. switch (gdp->plane.desc) {
  484. case STI_GDP_0:
  485. clk_name = "pix_gdp1";
  486. break;
  487. case STI_GDP_1:
  488. clk_name = "pix_gdp2";
  489. break;
  490. case STI_GDP_2:
  491. clk_name = "pix_gdp3";
  492. break;
  493. case STI_GDP_3:
  494. clk_name = "pix_gdp4";
  495. break;
  496. default:
  497. DRM_ERROR("GDP id not recognized\n");
  498. return;
  499. }
  500. gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
  501. if (IS_ERR(gdp->clk_pix))
  502. DRM_ERROR("Cannot get %s clock\n", clk_name);
  503. gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
  504. if (IS_ERR(gdp->clk_main_parent))
  505. DRM_ERROR("Cannot get main_parent clock\n");
  506. gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
  507. if (IS_ERR(gdp->clk_aux_parent))
  508. DRM_ERROR("Cannot get aux_parent clock\n");
  509. }
  510. }
  511. /**
  512. * sti_gdp_get_dst
  513. * @dev: device
  514. * @dst: requested destination size
  515. * @src: source size
  516. *
  517. * Return the cropped / clamped destination size
  518. *
  519. * RETURNS:
  520. * cropped / clamped destination size
  521. */
  522. static int sti_gdp_get_dst(struct device *dev, int dst, int src)
  523. {
  524. if (dst == src)
  525. return dst;
  526. if (dst < src) {
  527. dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
  528. return dst;
  529. }
  530. dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
  531. return src;
  532. }
  533. static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
  534. struct drm_plane_state *state)
  535. {
  536. struct sti_plane *plane = to_sti_plane(drm_plane);
  537. struct sti_gdp *gdp = to_sti_gdp(plane);
  538. struct drm_crtc *crtc = state->crtc;
  539. struct drm_framebuffer *fb = state->fb;
  540. struct drm_crtc_state *crtc_state;
  541. struct sti_mixer *mixer;
  542. struct drm_display_mode *mode;
  543. int dst_x, dst_y, dst_w, dst_h;
  544. int src_x, src_y, src_w, src_h;
  545. int format;
  546. /* no need for further checks if the plane is being disabled */
  547. if (!crtc || !fb)
  548. return 0;
  549. mixer = to_sti_mixer(crtc);
  550. crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
  551. mode = &crtc_state->mode;
  552. dst_x = state->crtc_x;
  553. dst_y = state->crtc_y;
  554. dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
  555. dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
  556. /* src_x are in 16.16 format */
  557. src_x = state->src_x >> 16;
  558. src_y = state->src_y >> 16;
  559. src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
  560. src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
  561. format = sti_gdp_fourcc2format(fb->format->format);
  562. if (format == -1) {
  563. DRM_ERROR("Format not supported by GDP %.4s\n",
  564. (char *)&fb->format->format);
  565. return -EINVAL;
  566. }
  567. if (!drm_fb_cma_get_gem_obj(fb, 0)) {
  568. DRM_ERROR("Can't get CMA GEM object for fb\n");
  569. return -EINVAL;
  570. }
  571. /* Set gdp clock */
  572. if (mode->clock && gdp->clk_pix) {
  573. struct clk *clkp;
  574. int rate = mode->clock * 1000;
  575. int res;
  576. /*
  577. * According to the mixer used, the gdp pixel clock
  578. * should have a different parent clock.
  579. */
  580. if (mixer->id == STI_MIXER_MAIN)
  581. clkp = gdp->clk_main_parent;
  582. else
  583. clkp = gdp->clk_aux_parent;
  584. if (clkp)
  585. clk_set_parent(gdp->clk_pix, clkp);
  586. res = clk_set_rate(gdp->clk_pix, rate);
  587. if (res < 0) {
  588. DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
  589. rate);
  590. return -EINVAL;
  591. }
  592. }
  593. DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
  594. crtc->base.id, sti_mixer_to_str(mixer),
  595. drm_plane->base.id, sti_plane_to_str(plane));
  596. DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
  597. sti_plane_to_str(plane),
  598. dst_w, dst_h, dst_x, dst_y,
  599. src_w, src_h, src_x, src_y);
  600. return 0;
  601. }
  602. static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
  603. struct drm_plane_state *oldstate)
  604. {
  605. struct drm_plane_state *state = drm_plane->state;
  606. struct sti_plane *plane = to_sti_plane(drm_plane);
  607. struct sti_gdp *gdp = to_sti_gdp(plane);
  608. struct drm_crtc *crtc = state->crtc;
  609. struct drm_framebuffer *fb = state->fb;
  610. struct drm_display_mode *mode;
  611. int dst_x, dst_y, dst_w, dst_h;
  612. int src_x, src_y, src_w, src_h;
  613. struct drm_gem_cma_object *cma_obj;
  614. struct sti_gdp_node_list *list;
  615. struct sti_gdp_node_list *curr_list;
  616. struct sti_gdp_node *top_field, *btm_field;
  617. u32 dma_updated_top;
  618. u32 dma_updated_btm;
  619. int format;
  620. unsigned int bpp;
  621. u32 ydo, xdo, yds, xds;
  622. if (!crtc || !fb)
  623. return;
  624. if ((oldstate->fb == state->fb) &&
  625. (oldstate->crtc_x == state->crtc_x) &&
  626. (oldstate->crtc_y == state->crtc_y) &&
  627. (oldstate->crtc_w == state->crtc_w) &&
  628. (oldstate->crtc_h == state->crtc_h) &&
  629. (oldstate->src_x == state->src_x) &&
  630. (oldstate->src_y == state->src_y) &&
  631. (oldstate->src_w == state->src_w) &&
  632. (oldstate->src_h == state->src_h)) {
  633. /* No change since last update, do not post cmd */
  634. DRM_DEBUG_DRIVER("No change, not posting cmd\n");
  635. plane->status = STI_PLANE_UPDATED;
  636. return;
  637. }
  638. if (!gdp->vtg) {
  639. struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
  640. struct sti_mixer *mixer = to_sti_mixer(crtc);
  641. /* Register gdp callback */
  642. gdp->vtg = compo->vtg[mixer->id];
  643. sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc);
  644. clk_prepare_enable(gdp->clk_pix);
  645. }
  646. mode = &crtc->mode;
  647. dst_x = state->crtc_x;
  648. dst_y = state->crtc_y;
  649. dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
  650. dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
  651. /* src_x are in 16.16 format */
  652. src_x = state->src_x >> 16;
  653. src_y = state->src_y >> 16;
  654. src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
  655. src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
  656. list = sti_gdp_get_free_nodes(gdp);
  657. top_field = list->top_field;
  658. btm_field = list->btm_field;
  659. dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
  660. sti_plane_to_str(plane), top_field, btm_field);
  661. /* build the top field */
  662. top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
  663. top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
  664. format = sti_gdp_fourcc2format(fb->format->format);
  665. top_field->gam_gdp_ctl |= format;
  666. top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
  667. top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
  668. cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
  669. DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
  670. (char *)&fb->format->format,
  671. (unsigned long)cma_obj->paddr);
  672. /* pixel memory location */
  673. bpp = fb->format->cpp[0];
  674. top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
  675. top_field->gam_gdp_pml += src_x * bpp;
  676. top_field->gam_gdp_pml += src_y * fb->pitches[0];
  677. /* output parameters (clamped / cropped) */
  678. dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
  679. dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
  680. ydo = sti_vtg_get_line_number(*mode, dst_y);
  681. yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
  682. xdo = sti_vtg_get_pixel_number(*mode, dst_x);
  683. xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
  684. top_field->gam_gdp_vpo = (ydo << 16) | xdo;
  685. top_field->gam_gdp_vps = (yds << 16) | xds;
  686. /* input parameters */
  687. src_w = dst_w;
  688. top_field->gam_gdp_pmp = fb->pitches[0];
  689. top_field->gam_gdp_size = src_h << 16 | src_w;
  690. /* Same content and chained together */
  691. memcpy(btm_field, top_field, sizeof(*btm_field));
  692. top_field->gam_gdp_nvn = list->btm_field_paddr;
  693. btm_field->gam_gdp_nvn = list->top_field_paddr;
  694. /* Interlaced mode */
  695. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  696. btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
  697. fb->pitches[0];
  698. /* Update the NVN field of the 'right' field of the current GDP node
  699. * (being used by the HW) with the address of the updated ('free') top
  700. * field GDP node.
  701. * - In interlaced mode the 'right' field is the bottom field as we
  702. * update frames starting from their top field
  703. * - In progressive mode, we update both bottom and top fields which
  704. * are equal nodes.
  705. * At the next VSYNC, the updated node list will be used by the HW.
  706. */
  707. curr_list = sti_gdp_get_current_nodes(gdp);
  708. dma_updated_top = list->top_field_paddr;
  709. dma_updated_btm = list->btm_field_paddr;
  710. dev_dbg(gdp->dev, "Current NVN:0x%X\n",
  711. readl(gdp->regs + GAM_GDP_NVN_OFFSET));
  712. dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
  713. (unsigned long)cma_obj->paddr,
  714. readl(gdp->regs + GAM_GDP_PML_OFFSET));
  715. if (!curr_list) {
  716. /* First update or invalid node should directly write in the
  717. * hw register */
  718. DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
  719. sti_plane_to_str(plane));
  720. writel(gdp->is_curr_top ?
  721. dma_updated_btm : dma_updated_top,
  722. gdp->regs + GAM_GDP_NVN_OFFSET);
  723. goto end;
  724. }
  725. if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  726. if (gdp->is_curr_top) {
  727. /* Do not update in the middle of the frame, but
  728. * postpone the update after the bottom field has
  729. * been displayed */
  730. curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
  731. } else {
  732. /* Direct update to avoid one frame delay */
  733. writel(dma_updated_top,
  734. gdp->regs + GAM_GDP_NVN_OFFSET);
  735. }
  736. } else {
  737. /* Direct update for progressive to avoid one frame delay */
  738. writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
  739. }
  740. end:
  741. sti_plane_update_fps(plane, true, false);
  742. plane->status = STI_PLANE_UPDATED;
  743. }
  744. static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
  745. struct drm_plane_state *oldstate)
  746. {
  747. struct sti_plane *plane = to_sti_plane(drm_plane);
  748. if (!oldstate->crtc) {
  749. DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
  750. drm_plane->base.id);
  751. return;
  752. }
  753. DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
  754. oldstate->crtc->base.id,
  755. sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
  756. drm_plane->base.id, sti_plane_to_str(plane));
  757. plane->status = STI_PLANE_DISABLING;
  758. }
  759. static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
  760. .atomic_check = sti_gdp_atomic_check,
  761. .atomic_update = sti_gdp_atomic_update,
  762. .atomic_disable = sti_gdp_atomic_disable,
  763. };
  764. static void sti_gdp_destroy(struct drm_plane *drm_plane)
  765. {
  766. DRM_DEBUG_DRIVER("\n");
  767. drm_plane_cleanup(drm_plane);
  768. }
  769. static int sti_gdp_late_register(struct drm_plane *drm_plane)
  770. {
  771. struct sti_plane *plane = to_sti_plane(drm_plane);
  772. struct sti_gdp *gdp = to_sti_gdp(plane);
  773. return gdp_debugfs_init(gdp, drm_plane->dev->primary);
  774. }
  775. static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
  776. .update_plane = drm_atomic_helper_update_plane,
  777. .disable_plane = drm_atomic_helper_disable_plane,
  778. .destroy = sti_gdp_destroy,
  779. .reset = sti_plane_reset,
  780. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  781. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  782. .late_register = sti_gdp_late_register,
  783. };
  784. struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
  785. struct device *dev, int desc,
  786. void __iomem *baseaddr,
  787. unsigned int possible_crtcs,
  788. enum drm_plane_type type)
  789. {
  790. struct sti_gdp *gdp;
  791. int res;
  792. gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
  793. if (!gdp) {
  794. DRM_ERROR("Failed to allocate memory for GDP\n");
  795. return NULL;
  796. }
  797. gdp->dev = dev;
  798. gdp->regs = baseaddr;
  799. gdp->plane.desc = desc;
  800. gdp->plane.status = STI_PLANE_DISABLED;
  801. gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
  802. sti_gdp_init(gdp);
  803. res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
  804. possible_crtcs,
  805. &sti_gdp_plane_helpers_funcs,
  806. gdp_supported_formats,
  807. ARRAY_SIZE(gdp_supported_formats),
  808. NULL, type, NULL);
  809. if (res) {
  810. DRM_ERROR("Failed to initialize universal plane\n");
  811. goto err;
  812. }
  813. drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
  814. sti_plane_init_property(&gdp->plane, type);
  815. return &gdp->plane.drm_plane;
  816. err:
  817. devm_kfree(dev, gdp);
  818. return NULL;
  819. }