NOTES 3.1 KB

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  1. 1. stiH display hardware IP
  2. ---------------------------
  3. The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
  4. - The High Quality Video Display Processor (HQVDP) gets video frames from a
  5. video decoder and does high quality video processing, including scaling.
  6. - The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
  7. has several inputs:
  8. - The graphics planes are internally processed by the Generic Display
  9. Pipeline (GDP).
  10. - The video plug (VID) connects to the HQVDP output.
  11. - The cursor handles ... a cursor.
  12. - The TV OUT pre-formats (convert, clip, round) the compositor output data
  13. - The HDMI / DVO / HD Analog / SD analog IP builds the video signals
  14. - DVO (Digital Video Output) handles a 24bits parallel signal
  15. - The HD analog signal is typically driven by a YCbCr cable, supporting up to
  16. 1080i mode.
  17. - The SD analog signal is typically used for legacy TV
  18. - The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
  19. Note that some stiH drivers support only a subset of thee HW IP.
  20. .-------------. .-----------. .-----------.
  21. GPU >-------------+GDP Main | | +---+ HDMI +--> HDMI
  22. GPU >-------------+GDP mixer+---+ | :===========:
  23. GPU >-------------+Cursor | | +---+ DVO +--> 24b//
  24. ------- | COMPOSITOR | | TV OUT | :===========:
  25. | | | | | +---+ HD analog +--> YCbCr
  26. Vid >--+ HQVDP +--+VID Aux +---+ | :===========:
  27. dec | | | mixer| | +---+ SD analog +--> CVBS
  28. '-------' '-------------' '-----------' '-----------'
  29. .-----------.
  30. | main+--> Vsync
  31. | VTG |
  32. | aux+--> Vsync
  33. '-----------'
  34. 2. DRM / HW mapping
  35. -------------------
  36. These IP are mapped to the DRM objects as following:
  37. - The CRTCs are mapped to the Compositor Main and Aux Mixers
  38. - The Framebuffers and planes are mapped to the Compositor GDP (non video
  39. buffers) and to HQVDP+VID (video buffers)
  40. - The Cursor is mapped to the Compositor Cursor
  41. - The Encoders are mapped to the TVOut
  42. - The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
  43. FB & planes Cursor CRTC Encoders Bridges/Connectors
  44. | | | | |
  45. | | | | |
  46. | .-------------. | .-----------. .-----------. |
  47. +------------> |GDP | Main | | | +-> | | HDMI | <-+
  48. +------------> |GDP v mixer|<+ | | | :===========: |
  49. | |Cursor | | | +-> | | DVO | <-+
  50. | ------- | COMPOSITOR | | |TV OUT | | :===========: |
  51. | | | | | | | +-> | | HD analog | <-+
  52. +-> | HQVDP | |VID Aux |<+ | | | :===========: |
  53. | | | mixer| | +-> | | SD analog | <-+
  54. '-------' '-------------' '-----------' '-----------'