rockchip_vop_reg.h 38 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  4. * Author:Mark Yao <mark.yao@rock-chips.com>
  5. */
  6. #ifndef _ROCKCHIP_VOP_REG_H
  7. #define _ROCKCHIP_VOP_REG_H
  8. /* rk3288 register definition */
  9. #define RK3288_REG_CFG_DONE 0x0000
  10. #define RK3288_VERSION_INFO 0x0004
  11. #define RK3288_SYS_CTRL 0x0008
  12. #define RK3288_SYS_CTRL1 0x000c
  13. #define RK3288_DSP_CTRL0 0x0010
  14. #define RK3288_DSP_CTRL1 0x0014
  15. #define RK3288_DSP_BG 0x0018
  16. #define RK3288_MCU_CTRL 0x001c
  17. #define RK3288_INTR_CTRL0 0x0020
  18. #define RK3288_INTR_CTRL1 0x0024
  19. #define RK3288_WIN0_CTRL0 0x0030
  20. #define RK3288_WIN0_CTRL1 0x0034
  21. #define RK3288_WIN0_COLOR_KEY 0x0038
  22. #define RK3288_WIN0_VIR 0x003c
  23. #define RK3288_WIN0_YRGB_MST 0x0040
  24. #define RK3288_WIN0_CBR_MST 0x0044
  25. #define RK3288_WIN0_ACT_INFO 0x0048
  26. #define RK3288_WIN0_DSP_INFO 0x004c
  27. #define RK3288_WIN0_DSP_ST 0x0050
  28. #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054
  29. #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058
  30. #define RK3288_WIN0_SCL_OFFSET 0x005c
  31. #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060
  32. #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064
  33. #define RK3288_WIN0_FADING_CTRL 0x0068
  34. #define RK3288_WIN0_CTRL2 0x006c
  35. /* win1 register */
  36. #define RK3288_WIN1_CTRL0 0x0070
  37. #define RK3288_WIN1_CTRL1 0x0074
  38. #define RK3288_WIN1_COLOR_KEY 0x0078
  39. #define RK3288_WIN1_VIR 0x007c
  40. #define RK3288_WIN1_YRGB_MST 0x0080
  41. #define RK3288_WIN1_CBR_MST 0x0084
  42. #define RK3288_WIN1_ACT_INFO 0x0088
  43. #define RK3288_WIN1_DSP_INFO 0x008c
  44. #define RK3288_WIN1_DSP_ST 0x0090
  45. #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094
  46. #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098
  47. #define RK3288_WIN1_SCL_OFFSET 0x009c
  48. #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0
  49. #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4
  50. #define RK3288_WIN1_FADING_CTRL 0x00a8
  51. /* win2 register */
  52. #define RK3288_WIN2_CTRL0 0x00b0
  53. #define RK3288_WIN2_CTRL1 0x00b4
  54. #define RK3288_WIN2_VIR0_1 0x00b8
  55. #define RK3288_WIN2_VIR2_3 0x00bc
  56. #define RK3288_WIN2_MST0 0x00c0
  57. #define RK3288_WIN2_DSP_INFO0 0x00c4
  58. #define RK3288_WIN2_DSP_ST0 0x00c8
  59. #define RK3288_WIN2_COLOR_KEY 0x00cc
  60. #define RK3288_WIN2_MST1 0x00d0
  61. #define RK3288_WIN2_DSP_INFO1 0x00d4
  62. #define RK3288_WIN2_DSP_ST1 0x00d8
  63. #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc
  64. #define RK3288_WIN2_MST2 0x00e0
  65. #define RK3288_WIN2_DSP_INFO2 0x00e4
  66. #define RK3288_WIN2_DSP_ST2 0x00e8
  67. #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec
  68. #define RK3288_WIN2_MST3 0x00f0
  69. #define RK3288_WIN2_DSP_INFO3 0x00f4
  70. #define RK3288_WIN2_DSP_ST3 0x00f8
  71. #define RK3288_WIN2_FADING_CTRL 0x00fc
  72. /* win3 register */
  73. #define RK3288_WIN3_CTRL0 0x0100
  74. #define RK3288_WIN3_CTRL1 0x0104
  75. #define RK3288_WIN3_VIR0_1 0x0108
  76. #define RK3288_WIN3_VIR2_3 0x010c
  77. #define RK3288_WIN3_MST0 0x0110
  78. #define RK3288_WIN3_DSP_INFO0 0x0114
  79. #define RK3288_WIN3_DSP_ST0 0x0118
  80. #define RK3288_WIN3_COLOR_KEY 0x011c
  81. #define RK3288_WIN3_MST1 0x0120
  82. #define RK3288_WIN3_DSP_INFO1 0x0124
  83. #define RK3288_WIN3_DSP_ST1 0x0128
  84. #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c
  85. #define RK3288_WIN3_MST2 0x0130
  86. #define RK3288_WIN3_DSP_INFO2 0x0134
  87. #define RK3288_WIN3_DSP_ST2 0x0138
  88. #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c
  89. #define RK3288_WIN3_MST3 0x0140
  90. #define RK3288_WIN3_DSP_INFO3 0x0144
  91. #define RK3288_WIN3_DSP_ST3 0x0148
  92. #define RK3288_WIN3_FADING_CTRL 0x014c
  93. /* hwc register */
  94. #define RK3288_HWC_CTRL0 0x0150
  95. #define RK3288_HWC_CTRL1 0x0154
  96. #define RK3288_HWC_MST 0x0158
  97. #define RK3288_HWC_DSP_ST 0x015c
  98. #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160
  99. #define RK3288_HWC_DST_ALPHA_CTRL 0x0164
  100. #define RK3288_HWC_FADING_CTRL 0x0168
  101. /* post process register */
  102. #define RK3288_POST_DSP_HACT_INFO 0x0170
  103. #define RK3288_POST_DSP_VACT_INFO 0x0174
  104. #define RK3288_POST_SCL_FACTOR_YRGB 0x0178
  105. #define RK3288_POST_SCL_CTRL 0x0180
  106. #define RK3288_POST_DSP_VACT_INFO_F1 0x0184
  107. #define RK3288_DSP_HTOTAL_HS_END 0x0188
  108. #define RK3288_DSP_HACT_ST_END 0x018c
  109. #define RK3288_DSP_VTOTAL_VS_END 0x0190
  110. #define RK3288_DSP_VACT_ST_END 0x0194
  111. #define RK3288_DSP_VS_ST_END_F1 0x0198
  112. #define RK3288_DSP_VACT_ST_END_F1 0x019c
  113. /* register definition end */
  114. /* rk3368 register definition */
  115. #define RK3368_REG_CFG_DONE 0x0000
  116. #define RK3368_VERSION_INFO 0x0004
  117. #define RK3368_SYS_CTRL 0x0008
  118. #define RK3368_SYS_CTRL1 0x000c
  119. #define RK3368_DSP_CTRL0 0x0010
  120. #define RK3368_DSP_CTRL1 0x0014
  121. #define RK3368_DSP_BG 0x0018
  122. #define RK3368_MCU_CTRL 0x001c
  123. #define RK3368_LINE_FLAG 0x0020
  124. #define RK3368_INTR_EN 0x0024
  125. #define RK3368_INTR_CLEAR 0x0028
  126. #define RK3368_INTR_STATUS 0x002c
  127. #define RK3368_WIN0_CTRL0 0x0030
  128. #define RK3368_WIN0_CTRL1 0x0034
  129. #define RK3368_WIN0_COLOR_KEY 0x0038
  130. #define RK3368_WIN0_VIR 0x003c
  131. #define RK3368_WIN0_YRGB_MST 0x0040
  132. #define RK3368_WIN0_CBR_MST 0x0044
  133. #define RK3368_WIN0_ACT_INFO 0x0048
  134. #define RK3368_WIN0_DSP_INFO 0x004c
  135. #define RK3368_WIN0_DSP_ST 0x0050
  136. #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054
  137. #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058
  138. #define RK3368_WIN0_SCL_OFFSET 0x005c
  139. #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060
  140. #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064
  141. #define RK3368_WIN0_FADING_CTRL 0x0068
  142. #define RK3368_WIN0_CTRL2 0x006c
  143. #define RK3368_WIN1_CTRL0 0x0070
  144. #define RK3368_WIN1_CTRL1 0x0074
  145. #define RK3368_WIN1_COLOR_KEY 0x0078
  146. #define RK3368_WIN1_VIR 0x007c
  147. #define RK3368_WIN1_YRGB_MST 0x0080
  148. #define RK3368_WIN1_CBR_MST 0x0084
  149. #define RK3368_WIN1_ACT_INFO 0x0088
  150. #define RK3368_WIN1_DSP_INFO 0x008c
  151. #define RK3368_WIN1_DSP_ST 0x0090
  152. #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094
  153. #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098
  154. #define RK3368_WIN1_SCL_OFFSET 0x009c
  155. #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0
  156. #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4
  157. #define RK3368_WIN1_FADING_CTRL 0x00a8
  158. #define RK3368_WIN1_CTRL2 0x00ac
  159. #define RK3368_WIN2_CTRL0 0x00b0
  160. #define RK3368_WIN2_CTRL1 0x00b4
  161. #define RK3368_WIN2_VIR0_1 0x00b8
  162. #define RK3368_WIN2_VIR2_3 0x00bc
  163. #define RK3368_WIN2_MST0 0x00c0
  164. #define RK3368_WIN2_DSP_INFO0 0x00c4
  165. #define RK3368_WIN2_DSP_ST0 0x00c8
  166. #define RK3368_WIN2_COLOR_KEY 0x00cc
  167. #define RK3368_WIN2_MST1 0x00d0
  168. #define RK3368_WIN2_DSP_INFO1 0x00d4
  169. #define RK3368_WIN2_DSP_ST1 0x00d8
  170. #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc
  171. #define RK3368_WIN2_MST2 0x00e0
  172. #define RK3368_WIN2_DSP_INFO2 0x00e4
  173. #define RK3368_WIN2_DSP_ST2 0x00e8
  174. #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec
  175. #define RK3368_WIN2_MST3 0x00f0
  176. #define RK3368_WIN2_DSP_INFO3 0x00f4
  177. #define RK3368_WIN2_DSP_ST3 0x00f8
  178. #define RK3368_WIN2_FADING_CTRL 0x00fc
  179. #define RK3368_WIN3_CTRL0 0x0100
  180. #define RK3368_WIN3_CTRL1 0x0104
  181. #define RK3368_WIN3_VIR0_1 0x0108
  182. #define RK3368_WIN3_VIR2_3 0x010c
  183. #define RK3368_WIN3_MST0 0x0110
  184. #define RK3368_WIN3_DSP_INFO0 0x0114
  185. #define RK3368_WIN3_DSP_ST0 0x0118
  186. #define RK3368_WIN3_COLOR_KEY 0x011c
  187. #define RK3368_WIN3_MST1 0x0120
  188. #define RK3368_WIN3_DSP_INFO1 0x0124
  189. #define RK3368_WIN3_DSP_ST1 0x0128
  190. #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c
  191. #define RK3368_WIN3_MST2 0x0130
  192. #define RK3368_WIN3_DSP_INFO2 0x0134
  193. #define RK3368_WIN3_DSP_ST2 0x0138
  194. #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c
  195. #define RK3368_WIN3_MST3 0x0140
  196. #define RK3368_WIN3_DSP_INFO3 0x0144
  197. #define RK3368_WIN3_DSP_ST3 0x0148
  198. #define RK3368_WIN3_FADING_CTRL 0x014c
  199. #define RK3368_HWC_CTRL0 0x0150
  200. #define RK3368_HWC_CTRL1 0x0154
  201. #define RK3368_HWC_MST 0x0158
  202. #define RK3368_HWC_DSP_ST 0x015c
  203. #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160
  204. #define RK3368_HWC_DST_ALPHA_CTRL 0x0164
  205. #define RK3368_HWC_FADING_CTRL 0x0168
  206. #define RK3368_HWC_RESERVED1 0x016c
  207. #define RK3368_POST_DSP_HACT_INFO 0x0170
  208. #define RK3368_POST_DSP_VACT_INFO 0x0174
  209. #define RK3368_POST_SCL_FACTOR_YRGB 0x0178
  210. #define RK3368_POST_RESERVED 0x017c
  211. #define RK3368_POST_SCL_CTRL 0x0180
  212. #define RK3368_POST_DSP_VACT_INFO_F1 0x0184
  213. #define RK3368_DSP_HTOTAL_HS_END 0x0188
  214. #define RK3368_DSP_HACT_ST_END 0x018c
  215. #define RK3368_DSP_VTOTAL_VS_END 0x0190
  216. #define RK3368_DSP_VACT_ST_END 0x0194
  217. #define RK3368_DSP_VS_ST_END_F1 0x0198
  218. #define RK3368_DSP_VACT_ST_END_F1 0x019c
  219. #define RK3368_PWM_CTRL 0x01a0
  220. #define RK3368_PWM_PERIOD_HPR 0x01a4
  221. #define RK3368_PWM_DUTY_LPR 0x01a8
  222. #define RK3368_PWM_CNT 0x01ac
  223. #define RK3368_BCSH_COLOR_BAR 0x01b0
  224. #define RK3368_BCSH_BCS 0x01b4
  225. #define RK3368_BCSH_H 0x01b8
  226. #define RK3368_BCSH_CTRL 0x01bc
  227. #define RK3368_CABC_CTRL0 0x01c0
  228. #define RK3368_CABC_CTRL1 0x01c4
  229. #define RK3368_CABC_CTRL2 0x01c8
  230. #define RK3368_CABC_CTRL3 0x01cc
  231. #define RK3368_CABC_GAUSS_LINE0_0 0x01d0
  232. #define RK3368_CABC_GAUSS_LINE0_1 0x01d4
  233. #define RK3368_CABC_GAUSS_LINE1_0 0x01d8
  234. #define RK3368_CABC_GAUSS_LINE1_1 0x01dc
  235. #define RK3368_CABC_GAUSS_LINE2_0 0x01e0
  236. #define RK3368_CABC_GAUSS_LINE2_1 0x01e4
  237. #define RK3368_FRC_LOWER01_0 0x01e8
  238. #define RK3368_FRC_LOWER01_1 0x01ec
  239. #define RK3368_FRC_LOWER10_0 0x01f0
  240. #define RK3368_FRC_LOWER10_1 0x01f4
  241. #define RK3368_FRC_LOWER11_0 0x01f8
  242. #define RK3368_FRC_LOWER11_1 0x01fc
  243. #define RK3368_IFBDC_CTRL 0x0200
  244. #define RK3368_IFBDC_TILES_NUM 0x0204
  245. #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208
  246. #define RK3368_IFBDC_BASE_ADDR 0x020c
  247. #define RK3368_IFBDC_MB_SIZE 0x0210
  248. #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214
  249. #define RK3368_IFBDC_VIR 0x0220
  250. #define RK3368_IFBDC_DEBUG0 0x0230
  251. #define RK3368_IFBDC_DEBUG1 0x0234
  252. #define RK3368_LATENCY_CTRL0 0x0250
  253. #define RK3368_RD_MAX_LATENCY_NUM0 0x0254
  254. #define RK3368_RD_LATENCY_THR_NUM0 0x0258
  255. #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c
  256. #define RK3368_WIN0_DSP_BG 0x0260
  257. #define RK3368_WIN1_DSP_BG 0x0264
  258. #define RK3368_WIN2_DSP_BG 0x0268
  259. #define RK3368_WIN3_DSP_BG 0x026c
  260. #define RK3368_SCAN_LINE_NUM 0x0270
  261. #define RK3368_CABC_DEBUG0 0x0274
  262. #define RK3368_CABC_DEBUG1 0x0278
  263. #define RK3368_CABC_DEBUG2 0x027c
  264. #define RK3368_DBG_REG_000 0x0280
  265. #define RK3368_DBG_REG_001 0x0284
  266. #define RK3368_DBG_REG_002 0x0288
  267. #define RK3368_DBG_REG_003 0x028c
  268. #define RK3368_DBG_REG_004 0x0290
  269. #define RK3368_DBG_REG_005 0x0294
  270. #define RK3368_DBG_REG_006 0x0298
  271. #define RK3368_DBG_REG_007 0x029c
  272. #define RK3368_DBG_REG_008 0x02a0
  273. #define RK3368_DBG_REG_016 0x02c0
  274. #define RK3368_DBG_REG_017 0x02c4
  275. #define RK3368_DBG_REG_018 0x02c8
  276. #define RK3368_DBG_REG_019 0x02cc
  277. #define RK3368_DBG_REG_020 0x02d0
  278. #define RK3368_DBG_REG_021 0x02d4
  279. #define RK3368_DBG_REG_022 0x02d8
  280. #define RK3368_DBG_REG_023 0x02dc
  281. #define RK3368_DBG_REG_028 0x02f0
  282. #define RK3368_MMU_DTE_ADDR 0x0300
  283. #define RK3368_MMU_STATUS 0x0304
  284. #define RK3368_MMU_COMMAND 0x0308
  285. #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c
  286. #define RK3368_MMU_ZAP_ONE_LINE 0x0310
  287. #define RK3368_MMU_INT_RAWSTAT 0x0314
  288. #define RK3368_MMU_INT_CLEAR 0x0318
  289. #define RK3368_MMU_INT_MASK 0x031c
  290. #define RK3368_MMU_INT_STATUS 0x0320
  291. #define RK3368_MMU_AUTO_GATING 0x0324
  292. #define RK3368_WIN2_LUT_ADDR 0x0400
  293. #define RK3368_WIN3_LUT_ADDR 0x0800
  294. #define RK3368_HWC_LUT_ADDR 0x0c00
  295. #define RK3368_GAMMA_LUT_ADDR 0x1000
  296. #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800
  297. #define RK3368_MCU_BYPASS_WPORT 0x2200
  298. #define RK3368_MCU_BYPASS_RPORT 0x2300
  299. /* rk3368 register definition end */
  300. #define RK3366_REG_CFG_DONE 0x0000
  301. #define RK3366_VERSION_INFO 0x0004
  302. #define RK3366_SYS_CTRL 0x0008
  303. #define RK3366_SYS_CTRL1 0x000c
  304. #define RK3366_DSP_CTRL0 0x0010
  305. #define RK3366_DSP_CTRL1 0x0014
  306. #define RK3366_DSP_BG 0x0018
  307. #define RK3366_MCU_CTRL 0x001c
  308. #define RK3366_WB_CTRL0 0x0020
  309. #define RK3366_WB_CTRL1 0x0024
  310. #define RK3366_WB_YRGB_MST 0x0028
  311. #define RK3366_WB_CBR_MST 0x002c
  312. #define RK3366_WIN0_CTRL0 0x0030
  313. #define RK3366_WIN0_CTRL1 0x0034
  314. #define RK3366_WIN0_COLOR_KEY 0x0038
  315. #define RK3366_WIN0_VIR 0x003c
  316. #define RK3366_WIN0_YRGB_MST 0x0040
  317. #define RK3366_WIN0_CBR_MST 0x0044
  318. #define RK3366_WIN0_ACT_INFO 0x0048
  319. #define RK3366_WIN0_DSP_INFO 0x004c
  320. #define RK3366_WIN0_DSP_ST 0x0050
  321. #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054
  322. #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058
  323. #define RK3366_WIN0_SCL_OFFSET 0x005c
  324. #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060
  325. #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064
  326. #define RK3366_WIN0_FADING_CTRL 0x0068
  327. #define RK3366_WIN0_CTRL2 0x006c
  328. #define RK3366_WIN1_CTRL0 0x0070
  329. #define RK3366_WIN1_CTRL1 0x0074
  330. #define RK3366_WIN1_COLOR_KEY 0x0078
  331. #define RK3366_WIN1_VIR 0x007c
  332. #define RK3366_WIN1_YRGB_MST 0x0080
  333. #define RK3366_WIN1_CBR_MST 0x0084
  334. #define RK3366_WIN1_ACT_INFO 0x0088
  335. #define RK3366_WIN1_DSP_INFO 0x008c
  336. #define RK3366_WIN1_DSP_ST 0x0090
  337. #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094
  338. #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098
  339. #define RK3366_WIN1_SCL_OFFSET 0x009c
  340. #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0
  341. #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4
  342. #define RK3366_WIN1_FADING_CTRL 0x00a8
  343. #define RK3366_WIN1_CTRL2 0x00ac
  344. #define RK3366_WIN2_CTRL0 0x00b0
  345. #define RK3366_WIN2_CTRL1 0x00b4
  346. #define RK3366_WIN2_VIR0_1 0x00b8
  347. #define RK3366_WIN2_VIR2_3 0x00bc
  348. #define RK3366_WIN2_MST0 0x00c0
  349. #define RK3366_WIN2_DSP_INFO0 0x00c4
  350. #define RK3366_WIN2_DSP_ST0 0x00c8
  351. #define RK3366_WIN2_COLOR_KEY 0x00cc
  352. #define RK3366_WIN2_MST1 0x00d0
  353. #define RK3366_WIN2_DSP_INFO1 0x00d4
  354. #define RK3366_WIN2_DSP_ST1 0x00d8
  355. #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc
  356. #define RK3366_WIN2_MST2 0x00e0
  357. #define RK3366_WIN2_DSP_INFO2 0x00e4
  358. #define RK3366_WIN2_DSP_ST2 0x00e8
  359. #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec
  360. #define RK3366_WIN2_MST3 0x00f0
  361. #define RK3366_WIN2_DSP_INFO3 0x00f4
  362. #define RK3366_WIN2_DSP_ST3 0x00f8
  363. #define RK3366_WIN2_FADING_CTRL 0x00fc
  364. #define RK3366_WIN3_CTRL0 0x0100
  365. #define RK3366_WIN3_CTRL1 0x0104
  366. #define RK3366_WIN3_VIR0_1 0x0108
  367. #define RK3366_WIN3_VIR2_3 0x010c
  368. #define RK3366_WIN3_MST0 0x0110
  369. #define RK3366_WIN3_DSP_INFO0 0x0114
  370. #define RK3366_WIN3_DSP_ST0 0x0118
  371. #define RK3366_WIN3_COLOR_KEY 0x011c
  372. #define RK3366_WIN3_MST1 0x0120
  373. #define RK3366_WIN3_DSP_INFO1 0x0124
  374. #define RK3366_WIN3_DSP_ST1 0x0128
  375. #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c
  376. #define RK3366_WIN3_MST2 0x0130
  377. #define RK3366_WIN3_DSP_INFO2 0x0134
  378. #define RK3366_WIN3_DSP_ST2 0x0138
  379. #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c
  380. #define RK3366_WIN3_MST3 0x0140
  381. #define RK3366_WIN3_DSP_INFO3 0x0144
  382. #define RK3366_WIN3_DSP_ST3 0x0148
  383. #define RK3366_WIN3_FADING_CTRL 0x014c
  384. #define RK3366_HWC_CTRL0 0x0150
  385. #define RK3366_HWC_CTRL1 0x0154
  386. #define RK3366_HWC_MST 0x0158
  387. #define RK3366_HWC_DSP_ST 0x015c
  388. #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160
  389. #define RK3366_HWC_DST_ALPHA_CTRL 0x0164
  390. #define RK3366_HWC_FADING_CTRL 0x0168
  391. #define RK3366_HWC_RESERVED1 0x016c
  392. #define RK3366_POST_DSP_HACT_INFO 0x0170
  393. #define RK3366_POST_DSP_VACT_INFO 0x0174
  394. #define RK3366_POST_SCL_FACTOR_YRGB 0x0178
  395. #define RK3366_POST_RESERVED 0x017c
  396. #define RK3366_POST_SCL_CTRL 0x0180
  397. #define RK3366_POST_DSP_VACT_INFO_F1 0x0184
  398. #define RK3366_DSP_HTOTAL_HS_END 0x0188
  399. #define RK3366_DSP_HACT_ST_END 0x018c
  400. #define RK3366_DSP_VTOTAL_VS_END 0x0190
  401. #define RK3366_DSP_VACT_ST_END 0x0194
  402. #define RK3366_DSP_VS_ST_END_F1 0x0198
  403. #define RK3366_DSP_VACT_ST_END_F1 0x019c
  404. #define RK3366_PWM_CTRL 0x01a0
  405. #define RK3366_PWM_PERIOD_HPR 0x01a4
  406. #define RK3366_PWM_DUTY_LPR 0x01a8
  407. #define RK3366_PWM_CNT 0x01ac
  408. #define RK3366_BCSH_COLOR_BAR 0x01b0
  409. #define RK3366_BCSH_BCS 0x01b4
  410. #define RK3366_BCSH_H 0x01b8
  411. #define RK3366_BCSH_CTRL 0x01bc
  412. #define RK3366_CABC_CTRL0 0x01c0
  413. #define RK3366_CABC_CTRL1 0x01c4
  414. #define RK3366_CABC_CTRL2 0x01c8
  415. #define RK3366_CABC_CTRL3 0x01cc
  416. #define RK3366_CABC_GAUSS_LINE0_0 0x01d0
  417. #define RK3366_CABC_GAUSS_LINE0_1 0x01d4
  418. #define RK3366_CABC_GAUSS_LINE1_0 0x01d8
  419. #define RK3366_CABC_GAUSS_LINE1_1 0x01dc
  420. #define RK3366_CABC_GAUSS_LINE2_0 0x01e0
  421. #define RK3366_CABC_GAUSS_LINE2_1 0x01e4
  422. #define RK3366_FRC_LOWER01_0 0x01e8
  423. #define RK3366_FRC_LOWER01_1 0x01ec
  424. #define RK3366_FRC_LOWER10_0 0x01f0
  425. #define RK3366_FRC_LOWER10_1 0x01f4
  426. #define RK3366_FRC_LOWER11_0 0x01f8
  427. #define RK3366_FRC_LOWER11_1 0x01fc
  428. #define RK3366_INTR_EN0 0x0280
  429. #define RK3366_INTR_CLEAR0 0x0284
  430. #define RK3366_INTR_STATUS0 0x0288
  431. #define RK3366_INTR_RAW_STATUS0 0x028c
  432. #define RK3366_INTR_EN1 0x0290
  433. #define RK3366_INTR_CLEAR1 0x0294
  434. #define RK3366_INTR_STATUS1 0x0298
  435. #define RK3366_INTR_RAW_STATUS1 0x029c
  436. #define RK3366_LINE_FLAG 0x02a0
  437. #define RK3366_VOP_STATUS 0x02a4
  438. #define RK3366_BLANKING_VALUE 0x02a8
  439. #define RK3366_WIN0_DSP_BG 0x02b0
  440. #define RK3366_WIN1_DSP_BG 0x02b4
  441. #define RK3366_WIN2_DSP_BG 0x02b8
  442. #define RK3366_WIN3_DSP_BG 0x02bc
  443. #define RK3366_WIN2_LUT_ADDR 0x0400
  444. #define RK3366_WIN3_LUT_ADDR 0x0800
  445. #define RK3366_HWC_LUT_ADDR 0x0c00
  446. #define RK3366_GAMMA0_LUT_ADDR 0x1000
  447. #define RK3366_GAMMA1_LUT_ADDR 0x1400
  448. #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800
  449. #define RK3366_MCU_BYPASS_WPORT 0x2200
  450. #define RK3366_MCU_BYPASS_RPORT 0x2300
  451. #define RK3366_MMU_DTE_ADDR 0x2400
  452. #define RK3366_MMU_STATUS 0x2404
  453. #define RK3366_MMU_COMMAND 0x2408
  454. #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c
  455. #define RK3366_MMU_ZAP_ONE_LINE 0x2410
  456. #define RK3366_MMU_INT_RAWSTAT 0x2414
  457. #define RK3366_MMU_INT_CLEAR 0x2418
  458. #define RK3366_MMU_INT_MASK 0x241c
  459. #define RK3366_MMU_INT_STATUS 0x2420
  460. #define RK3366_MMU_AUTO_GATING 0x2424
  461. /* rk3399 register definition */
  462. #define RK3399_REG_CFG_DONE 0x0000
  463. #define RK3399_VERSION_INFO 0x0004
  464. #define RK3399_SYS_CTRL 0x0008
  465. #define RK3399_SYS_CTRL1 0x000c
  466. #define RK3399_DSP_CTRL0 0x0010
  467. #define RK3399_DSP_CTRL1 0x0014
  468. #define RK3399_DSP_BG 0x0018
  469. #define RK3399_MCU_CTRL 0x001c
  470. #define RK3399_WB_CTRL0 0x0020
  471. #define RK3399_WB_CTRL1 0x0024
  472. #define RK3399_WB_YRGB_MST 0x0028
  473. #define RK3399_WB_CBR_MST 0x002c
  474. #define RK3399_WIN0_CTRL0 0x0030
  475. #define RK3399_WIN0_CTRL1 0x0034
  476. #define RK3399_WIN0_COLOR_KEY 0x0038
  477. #define RK3399_WIN0_VIR 0x003c
  478. #define RK3399_WIN0_YRGB_MST 0x0040
  479. #define RK3399_WIN0_CBR_MST 0x0044
  480. #define RK3399_WIN0_ACT_INFO 0x0048
  481. #define RK3399_WIN0_DSP_INFO 0x004c
  482. #define RK3399_WIN0_DSP_ST 0x0050
  483. #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054
  484. #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058
  485. #define RK3399_WIN0_SCL_OFFSET 0x005c
  486. #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060
  487. #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064
  488. #define RK3399_WIN0_FADING_CTRL 0x0068
  489. #define RK3399_WIN0_CTRL2 0x006c
  490. #define RK3399_WIN1_CTRL0 0x0070
  491. #define RK3399_WIN1_CTRL1 0x0074
  492. #define RK3399_WIN1_COLOR_KEY 0x0078
  493. #define RK3399_WIN1_VIR 0x007c
  494. #define RK3399_WIN1_YRGB_MST 0x0080
  495. #define RK3399_WIN1_CBR_MST 0x0084
  496. #define RK3399_WIN1_ACT_INFO 0x0088
  497. #define RK3399_WIN1_DSP_INFO 0x008c
  498. #define RK3399_WIN1_DSP_ST 0x0090
  499. #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094
  500. #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098
  501. #define RK3399_WIN1_SCL_OFFSET 0x009c
  502. #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0
  503. #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4
  504. #define RK3399_WIN1_FADING_CTRL 0x00a8
  505. #define RK3399_WIN1_CTRL2 0x00ac
  506. #define RK3399_WIN2_CTRL0 0x00b0
  507. #define RK3399_WIN2_CTRL1 0x00b4
  508. #define RK3399_WIN2_VIR0_1 0x00b8
  509. #define RK3399_WIN2_VIR2_3 0x00bc
  510. #define RK3399_WIN2_MST0 0x00c0
  511. #define RK3399_WIN2_DSP_INFO0 0x00c4
  512. #define RK3399_WIN2_DSP_ST0 0x00c8
  513. #define RK3399_WIN2_COLOR_KEY 0x00cc
  514. #define RK3399_WIN2_MST1 0x00d0
  515. #define RK3399_WIN2_DSP_INFO1 0x00d4
  516. #define RK3399_WIN2_DSP_ST1 0x00d8
  517. #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc
  518. #define RK3399_WIN2_MST2 0x00e0
  519. #define RK3399_WIN2_DSP_INFO2 0x00e4
  520. #define RK3399_WIN2_DSP_ST2 0x00e8
  521. #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec
  522. #define RK3399_WIN2_MST3 0x00f0
  523. #define RK3399_WIN2_DSP_INFO3 0x00f4
  524. #define RK3399_WIN2_DSP_ST3 0x00f8
  525. #define RK3399_WIN2_FADING_CTRL 0x00fc
  526. #define RK3399_WIN3_CTRL0 0x0100
  527. #define RK3399_WIN3_CTRL1 0x0104
  528. #define RK3399_WIN3_VIR0_1 0x0108
  529. #define RK3399_WIN3_VIR2_3 0x010c
  530. #define RK3399_WIN3_MST0 0x0110
  531. #define RK3399_WIN3_DSP_INFO0 0x0114
  532. #define RK3399_WIN3_DSP_ST0 0x0118
  533. #define RK3399_WIN3_COLOR_KEY 0x011c
  534. #define RK3399_WIN3_MST1 0x0120
  535. #define RK3399_WIN3_DSP_INFO1 0x0124
  536. #define RK3399_WIN3_DSP_ST1 0x0128
  537. #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c
  538. #define RK3399_WIN3_MST2 0x0130
  539. #define RK3399_WIN3_DSP_INFO2 0x0134
  540. #define RK3399_WIN3_DSP_ST2 0x0138
  541. #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c
  542. #define RK3399_WIN3_MST3 0x0140
  543. #define RK3399_WIN3_DSP_INFO3 0x0144
  544. #define RK3399_WIN3_DSP_ST3 0x0148
  545. #define RK3399_WIN3_FADING_CTRL 0x014c
  546. #define RK3399_HWC_CTRL0 0x0150
  547. #define RK3399_HWC_CTRL1 0x0154
  548. #define RK3399_HWC_MST 0x0158
  549. #define RK3399_HWC_DSP_ST 0x015c
  550. #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160
  551. #define RK3399_HWC_DST_ALPHA_CTRL 0x0164
  552. #define RK3399_HWC_FADING_CTRL 0x0168
  553. #define RK3399_HWC_RESERVED1 0x016c
  554. #define RK3399_POST_DSP_HACT_INFO 0x0170
  555. #define RK3399_POST_DSP_VACT_INFO 0x0174
  556. #define RK3399_POST_SCL_FACTOR_YRGB 0x0178
  557. #define RK3399_POST_RESERVED 0x017c
  558. #define RK3399_POST_SCL_CTRL 0x0180
  559. #define RK3399_POST_DSP_VACT_INFO_F1 0x0184
  560. #define RK3399_DSP_HTOTAL_HS_END 0x0188
  561. #define RK3399_DSP_HACT_ST_END 0x018c
  562. #define RK3399_DSP_VTOTAL_VS_END 0x0190
  563. #define RK3399_DSP_VACT_ST_END 0x0194
  564. #define RK3399_DSP_VS_ST_END_F1 0x0198
  565. #define RK3399_DSP_VACT_ST_END_F1 0x019c
  566. #define RK3399_PWM_CTRL 0x01a0
  567. #define RK3399_PWM_PERIOD_HPR 0x01a4
  568. #define RK3399_PWM_DUTY_LPR 0x01a8
  569. #define RK3399_PWM_CNT 0x01ac
  570. #define RK3399_BCSH_COLOR_BAR 0x01b0
  571. #define RK3399_BCSH_BCS 0x01b4
  572. #define RK3399_BCSH_H 0x01b8
  573. #define RK3399_BCSH_CTRL 0x01bc
  574. #define RK3399_CABC_CTRL0 0x01c0
  575. #define RK3399_CABC_CTRL1 0x01c4
  576. #define RK3399_CABC_CTRL2 0x01c8
  577. #define RK3399_CABC_CTRL3 0x01cc
  578. #define RK3399_CABC_GAUSS_LINE0_0 0x01d0
  579. #define RK3399_CABC_GAUSS_LINE0_1 0x01d4
  580. #define RK3399_CABC_GAUSS_LINE1_0 0x01d8
  581. #define RK3399_CABC_GAUSS_LINE1_1 0x01dc
  582. #define RK3399_CABC_GAUSS_LINE2_0 0x01e0
  583. #define RK3399_CABC_GAUSS_LINE2_1 0x01e4
  584. #define RK3399_FRC_LOWER01_0 0x01e8
  585. #define RK3399_FRC_LOWER01_1 0x01ec
  586. #define RK3399_FRC_LOWER10_0 0x01f0
  587. #define RK3399_FRC_LOWER10_1 0x01f4
  588. #define RK3399_FRC_LOWER11_0 0x01f8
  589. #define RK3399_FRC_LOWER11_1 0x01fc
  590. #define RK3399_AFBCD0_CTRL 0x0200
  591. #define RK3399_AFBCD0_HDR_PTR 0x0204
  592. #define RK3399_AFBCD0_PIC_SIZE 0x0208
  593. #define RK3399_AFBCD0_STATUS 0x020c
  594. #define RK3399_AFBCD1_CTRL 0x0220
  595. #define RK3399_AFBCD1_HDR_PTR 0x0224
  596. #define RK3399_AFBCD1_PIC_SIZE 0x0228
  597. #define RK3399_AFBCD1_STATUS 0x022c
  598. #define RK3399_AFBCD2_CTRL 0x0240
  599. #define RK3399_AFBCD2_HDR_PTR 0x0244
  600. #define RK3399_AFBCD2_PIC_SIZE 0x0248
  601. #define RK3399_AFBCD2_STATUS 0x024c
  602. #define RK3399_AFBCD3_CTRL 0x0260
  603. #define RK3399_AFBCD3_HDR_PTR 0x0264
  604. #define RK3399_AFBCD3_PIC_SIZE 0x0268
  605. #define RK3399_AFBCD3_STATUS 0x026c
  606. #define RK3399_INTR_EN0 0x0280
  607. #define RK3399_INTR_CLEAR0 0x0284
  608. #define RK3399_INTR_STATUS0 0x0288
  609. #define RK3399_INTR_RAW_STATUS0 0x028c
  610. #define RK3399_INTR_EN1 0x0290
  611. #define RK3399_INTR_CLEAR1 0x0294
  612. #define RK3399_INTR_STATUS1 0x0298
  613. #define RK3399_INTR_RAW_STATUS1 0x029c
  614. #define RK3399_LINE_FLAG 0x02a0
  615. #define RK3399_VOP_STATUS 0x02a4
  616. #define RK3399_BLANKING_VALUE 0x02a8
  617. #define RK3399_MCU_BYPASS_PORT 0x02ac
  618. #define RK3399_WIN0_DSP_BG 0x02b0
  619. #define RK3399_WIN1_DSP_BG 0x02b4
  620. #define RK3399_WIN2_DSP_BG 0x02b8
  621. #define RK3399_WIN3_DSP_BG 0x02bc
  622. #define RK3399_YUV2YUV_WIN 0x02c0
  623. #define RK3399_YUV2YUV_POST 0x02c4
  624. #define RK3399_AUTO_GATING_EN 0x02cc
  625. #define RK3399_WIN0_CSC_COE 0x03a0
  626. #define RK3399_WIN1_CSC_COE 0x03c0
  627. #define RK3399_WIN2_CSC_COE 0x03e0
  628. #define RK3399_WIN3_CSC_COE 0x0400
  629. #define RK3399_HWC_CSC_COE 0x0420
  630. #define RK3399_BCSH_R2Y_CSC_COE 0x0440
  631. #define RK3399_BCSH_Y2R_CSC_COE 0x0460
  632. #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480
  633. #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0
  634. #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0
  635. #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0
  636. #define RK3399_WIN0_YUV2YUV_3X3 0x0500
  637. #define RK3399_WIN0_YUV2YUV_R2Y 0x0520
  638. #define RK3399_WIN1_YUV2YUV_Y2R 0x0540
  639. #define RK3399_WIN1_YUV2YUV_3X3 0x0560
  640. #define RK3399_WIN1_YUV2YUV_R2Y 0x0580
  641. #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0
  642. #define RK3399_WIN2_YUV2YUV_3X3 0x05c0
  643. #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0
  644. #define RK3399_WIN3_YUV2YUV_Y2R 0x0600
  645. #define RK3399_WIN3_YUV2YUV_3X3 0x0620
  646. #define RK3399_WIN3_YUV2YUV_R2Y 0x0640
  647. #define RK3399_WIN2_LUT_ADDR 0x1000
  648. #define RK3399_WIN3_LUT_ADDR 0x1400
  649. #define RK3399_HWC_LUT_ADDR 0x1800
  650. #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00
  651. #define RK3399_GAMMA_LUT_ADDR 0x2000
  652. /* rk3399 register definition end */
  653. /* rk3328 register definition end */
  654. #define RK3328_REG_CFG_DONE 0x00000000
  655. #define RK3328_VERSION_INFO 0x00000004
  656. #define RK3328_SYS_CTRL 0x00000008
  657. #define RK3328_SYS_CTRL1 0x0000000c
  658. #define RK3328_DSP_CTRL0 0x00000010
  659. #define RK3328_DSP_CTRL1 0x00000014
  660. #define RK3328_DSP_BG 0x00000018
  661. #define RK3328_AUTO_GATING_EN 0x0000003c
  662. #define RK3328_LINE_FLAG 0x00000040
  663. #define RK3328_VOP_STATUS 0x00000044
  664. #define RK3328_BLANKING_VALUE 0x00000048
  665. #define RK3328_WIN0_DSP_BG 0x00000050
  666. #define RK3328_WIN1_DSP_BG 0x00000054
  667. #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0
  668. #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4
  669. #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8
  670. #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc
  671. #define RK3328_INTR_EN0 0x000000e0
  672. #define RK3328_INTR_CLEAR0 0x000000e4
  673. #define RK3328_INTR_STATUS0 0x000000e8
  674. #define RK3328_INTR_RAW_STATUS0 0x000000ec
  675. #define RK3328_INTR_EN1 0x000000f0
  676. #define RK3328_INTR_CLEAR1 0x000000f4
  677. #define RK3328_INTR_STATUS1 0x000000f8
  678. #define RK3328_INTR_RAW_STATUS1 0x000000fc
  679. #define RK3328_WIN0_CTRL0 0x00000100
  680. #define RK3328_WIN0_CTRL1 0x00000104
  681. #define RK3328_WIN0_COLOR_KEY 0x00000108
  682. #define RK3328_WIN0_VIR 0x0000010c
  683. #define RK3328_WIN0_YRGB_MST 0x00000110
  684. #define RK3328_WIN0_CBR_MST 0x00000114
  685. #define RK3328_WIN0_ACT_INFO 0x00000118
  686. #define RK3328_WIN0_DSP_INFO 0x0000011c
  687. #define RK3328_WIN0_DSP_ST 0x00000120
  688. #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124
  689. #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128
  690. #define RK3328_WIN0_SCL_OFFSET 0x0000012c
  691. #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130
  692. #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134
  693. #define RK3328_WIN0_FADING_CTRL 0x00000138
  694. #define RK3328_WIN0_CTRL2 0x0000013c
  695. #define RK3328_DBG_WIN0_REG0 0x000001f0
  696. #define RK3328_DBG_WIN0_REG1 0x000001f4
  697. #define RK3328_DBG_WIN0_REG2 0x000001f8
  698. #define RK3328_DBG_WIN0_RESERVED 0x000001fc
  699. #define RK3328_WIN1_CTRL0 0x00000200
  700. #define RK3328_WIN1_CTRL1 0x00000204
  701. #define RK3328_WIN1_COLOR_KEY 0x00000208
  702. #define RK3328_WIN1_VIR 0x0000020c
  703. #define RK3328_WIN1_YRGB_MST 0x00000210
  704. #define RK3328_WIN1_CBR_MST 0x00000214
  705. #define RK3328_WIN1_ACT_INFO 0x00000218
  706. #define RK3328_WIN1_DSP_INFO 0x0000021c
  707. #define RK3328_WIN1_DSP_ST 0x00000220
  708. #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224
  709. #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228
  710. #define RK3328_WIN1_SCL_OFFSET 0x0000022c
  711. #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230
  712. #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234
  713. #define RK3328_WIN1_FADING_CTRL 0x00000238
  714. #define RK3328_WIN1_CTRL2 0x0000023c
  715. #define RK3328_DBG_WIN1_REG0 0x000002f0
  716. #define RK3328_DBG_WIN1_REG1 0x000002f4
  717. #define RK3328_DBG_WIN1_REG2 0x000002f8
  718. #define RK3328_DBG_WIN1_RESERVED 0x000002fc
  719. #define RK3328_WIN2_CTRL0 0x00000300
  720. #define RK3328_WIN2_CTRL1 0x00000304
  721. #define RK3328_WIN2_COLOR_KEY 0x00000308
  722. #define RK3328_WIN2_VIR 0x0000030c
  723. #define RK3328_WIN2_YRGB_MST 0x00000310
  724. #define RK3328_WIN2_CBR_MST 0x00000314
  725. #define RK3328_WIN2_ACT_INFO 0x00000318
  726. #define RK3328_WIN2_DSP_INFO 0x0000031c
  727. #define RK3328_WIN2_DSP_ST 0x00000320
  728. #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324
  729. #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328
  730. #define RK3328_WIN2_SCL_OFFSET 0x0000032c
  731. #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330
  732. #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334
  733. #define RK3328_WIN2_FADING_CTRL 0x00000338
  734. #define RK3328_WIN2_CTRL2 0x0000033c
  735. #define RK3328_DBG_WIN2_REG0 0x000003f0
  736. #define RK3328_DBG_WIN2_REG1 0x000003f4
  737. #define RK3328_DBG_WIN2_REG2 0x000003f8
  738. #define RK3328_DBG_WIN2_RESERVED 0x000003fc
  739. #define RK3328_WIN3_CTRL0 0x00000400
  740. #define RK3328_WIN3_CTRL1 0x00000404
  741. #define RK3328_WIN3_COLOR_KEY 0x00000408
  742. #define RK3328_WIN3_VIR 0x0000040c
  743. #define RK3328_WIN3_YRGB_MST 0x00000410
  744. #define RK3328_WIN3_CBR_MST 0x00000414
  745. #define RK3328_WIN3_ACT_INFO 0x00000418
  746. #define RK3328_WIN3_DSP_INFO 0x0000041c
  747. #define RK3328_WIN3_DSP_ST 0x00000420
  748. #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424
  749. #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428
  750. #define RK3328_WIN3_SCL_OFFSET 0x0000042c
  751. #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430
  752. #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434
  753. #define RK3328_WIN3_FADING_CTRL 0x00000438
  754. #define RK3328_WIN3_CTRL2 0x0000043c
  755. #define RK3328_DBG_WIN3_REG0 0x000004f0
  756. #define RK3328_DBG_WIN3_REG1 0x000004f4
  757. #define RK3328_DBG_WIN3_REG2 0x000004f8
  758. #define RK3328_DBG_WIN3_RESERVED 0x000004fc
  759. #define RK3328_HWC_CTRL0 0x00000500
  760. #define RK3328_HWC_CTRL1 0x00000504
  761. #define RK3328_HWC_MST 0x00000508
  762. #define RK3328_HWC_DSP_ST 0x0000050c
  763. #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510
  764. #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514
  765. #define RK3328_HWC_FADING_CTRL 0x00000518
  766. #define RK3328_HWC_RESERVED1 0x0000051c
  767. #define RK3328_POST_DSP_HACT_INFO 0x00000600
  768. #define RK3328_POST_DSP_VACT_INFO 0x00000604
  769. #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608
  770. #define RK3328_POST_RESERVED 0x0000060c
  771. #define RK3328_POST_SCL_CTRL 0x00000610
  772. #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614
  773. #define RK3328_DSP_HTOTAL_HS_END 0x00000618
  774. #define RK3328_DSP_HACT_ST_END 0x0000061c
  775. #define RK3328_DSP_VTOTAL_VS_END 0x00000620
  776. #define RK3328_DSP_VACT_ST_END 0x00000624
  777. #define RK3328_DSP_VS_ST_END_F1 0x00000628
  778. #define RK3328_DSP_VACT_ST_END_F1 0x0000062c
  779. #define RK3328_BCSH_COLOR_BAR 0x00000640
  780. #define RK3328_BCSH_BCS 0x00000644
  781. #define RK3328_BCSH_H 0x00000648
  782. #define RK3328_BCSH_CTRL 0x0000064c
  783. #define RK3328_FRC_LOWER01_0 0x00000678
  784. #define RK3328_FRC_LOWER01_1 0x0000067c
  785. #define RK3328_FRC_LOWER10_0 0x00000680
  786. #define RK3328_FRC_LOWER10_1 0x00000684
  787. #define RK3328_FRC_LOWER11_0 0x00000688
  788. #define RK3328_FRC_LOWER11_1 0x0000068c
  789. #define RK3328_DBG_POST_REG0 0x000006e8
  790. #define RK3328_DBG_POST_RESERVED 0x000006ec
  791. #define RK3328_DBG_DATAO 0x000006f0
  792. #define RK3328_DBG_DATAO_2 0x000006f4
  793. /* sdr to hdr */
  794. #define RK3328_SDR2HDR_CTRL 0x00000700
  795. #define RK3328_EOTF_OETF_Y0 0x00000704
  796. #define RK3328_RESERVED0001 0x00000708
  797. #define RK3328_RESERVED0002 0x0000070c
  798. #define RK3328_EOTF_OETF_Y1 0x00000710
  799. #define RK3328_EOTF_OETF_Y64 0x0000080c
  800. #define RK3328_OETF_DX_DXPOW1 0x00000810
  801. #define RK3328_OETF_DX_DXPOW64 0x0000090c
  802. #define RK3328_OETF_XN1 0x00000910
  803. #define RK3328_OETF_XN63 0x00000a08
  804. /* hdr to sdr */
  805. #define RK3328_HDR2SDR_CTRL 0x00000a10
  806. #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14
  807. #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18
  808. #define RK3328_RESERVED0003 0x00000a1c
  809. #define RK3328_HDR2SDR_DST_RANGE 0x00000a20
  810. #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24
  811. #define RK3328_EETF_OETF_Y0 0x00000a28
  812. #define RK3328_SAT_Y0 0x00000a2c
  813. #define RK3328_EETF_OETF_Y1 0x00000a30
  814. #define RK3328_SAT_Y1 0x00000ab0
  815. #define RK3328_SAT_Y8 0x00000acc
  816. #define RK3328_HWC_LUT_ADDR 0x00000c00
  817. /* rk3036 register definition */
  818. #define RK3036_SYS_CTRL 0x00
  819. #define RK3036_DSP_CTRL0 0x04
  820. #define RK3036_DSP_CTRL1 0x08
  821. #define RK3036_INT_STATUS 0x10
  822. #define RK3036_ALPHA_CTRL 0x14
  823. #define RK3036_WIN0_COLOR_KEY 0x18
  824. #define RK3036_WIN1_COLOR_KEY 0x1c
  825. #define RK3036_WIN0_YRGB_MST 0x20
  826. #define RK3036_WIN0_CBR_MST 0x24
  827. #define RK3036_WIN1_VIR 0x28
  828. #define RK3036_AXI_BUS_CTRL 0x2c
  829. #define RK3036_WIN0_VIR 0x30
  830. #define RK3036_WIN0_ACT_INFO 0x34
  831. #define RK3036_WIN0_DSP_INFO 0x38
  832. #define RK3036_WIN0_DSP_ST 0x3c
  833. #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40
  834. #define RK3036_WIN0_SCL_FACTOR_CBR 0x44
  835. #define RK3036_WIN0_SCL_OFFSET 0x48
  836. #define RK3036_HWC_MST 0x58
  837. #define RK3036_HWC_DSP_ST 0x5c
  838. #define RK3036_DSP_HTOTAL_HS_END 0x6c
  839. #define RK3036_DSP_HACT_ST_END 0x70
  840. #define RK3036_DSP_VTOTAL_VS_END 0x74
  841. #define RK3036_DSP_VACT_ST_END 0x78
  842. #define RK3036_DSP_VS_ST_END_F1 0x7c
  843. #define RK3036_DSP_VACT_ST_END_F1 0x80
  844. #define RK3036_GATHER_TRANSFER 0x84
  845. #define RK3036_VERSION_INFO 0x94
  846. #define RK3036_REG_CFG_DONE 0x90
  847. #define RK3036_WIN1_MST 0xa0
  848. #define RK3036_WIN1_ACT_INFO 0xb4
  849. #define RK3036_WIN1_DSP_INFO 0xb8
  850. #define RK3036_WIN1_DSP_ST 0xbc
  851. #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0
  852. #define RK3036_WIN1_SCL_OFFSET 0xc8
  853. #define RK3036_BCSH_CTRL 0xd0
  854. #define RK3036_BCSH_COLOR_BAR 0xd4
  855. #define RK3036_BCSH_BCS 0xd8
  856. #define RK3036_BCSH_H 0xdc
  857. #define RK3036_WIN1_LUT_ADDR 0x400
  858. #define RK3036_HWC_LUT_ADDR 0x800
  859. /* rk3036 register definition end */
  860. /* rk3126 register definition */
  861. #define RK3126_WIN1_MST 0x4c
  862. #define RK3126_WIN1_DSP_INFO 0x50
  863. #define RK3126_WIN1_DSP_ST 0x54
  864. /* rk3126 register definition end */
  865. /* px30 register definition */
  866. #define PX30_REG_CFG_DONE 0x00000
  867. #define PX30_VERSION 0x00004
  868. #define PX30_DSP_BG 0x00008
  869. #define PX30_MCU_CTRL 0x0000c
  870. #define PX30_SYS_CTRL0 0x00010
  871. #define PX30_SYS_CTRL1 0x00014
  872. #define PX30_SYS_CTRL2 0x00018
  873. #define PX30_DSP_CTRL0 0x00020
  874. #define PX30_DSP_CTRL2 0x00028
  875. #define PX30_VOP_STATUS 0x0002c
  876. #define PX30_LINE_FLAG 0x00030
  877. #define PX30_INTR_EN 0x00034
  878. #define PX30_INTR_CLEAR 0x00038
  879. #define PX30_INTR_STATUS 0x0003c
  880. #define PX30_WIN0_CTRL0 0x00050
  881. #define PX30_WIN0_CTRL1 0x00054
  882. #define PX30_WIN0_COLOR_KEY 0x00058
  883. #define PX30_WIN0_VIR 0x0005c
  884. #define PX30_WIN0_YRGB_MST0 0x00060
  885. #define PX30_WIN0_CBR_MST0 0x00064
  886. #define PX30_WIN0_ACT_INFO 0x00068
  887. #define PX30_WIN0_DSP_INFO 0x0006c
  888. #define PX30_WIN0_DSP_ST 0x00070
  889. #define PX30_WIN0_SCL_FACTOR_YRGB 0x00074
  890. #define PX30_WIN0_SCL_FACTOR_CBR 0x00078
  891. #define PX30_WIN0_SCL_OFFSET 0x0007c
  892. #define PX30_WIN0_ALPHA_CTRL 0x00080
  893. #define PX30_WIN1_CTRL0 0x00090
  894. #define PX30_WIN1_CTRL1 0x00094
  895. #define PX30_WIN1_VIR 0x00098
  896. #define PX30_WIN1_MST 0x000a0
  897. #define PX30_WIN1_DSP_INFO 0x000a4
  898. #define PX30_WIN1_DSP_ST 0x000a8
  899. #define PX30_WIN1_COLOR_KEY 0x000ac
  900. #define PX30_WIN1_ALPHA_CTRL 0x000bc
  901. #define PX30_HWC_CTRL0 0x000e0
  902. #define PX30_HWC_CTRL1 0x000e4
  903. #define PX30_HWC_MST 0x000e8
  904. #define PX30_HWC_DSP_ST 0x000ec
  905. #define PX30_HWC_ALPHA_CTRL 0x000f0
  906. #define PX30_DSP_HTOTAL_HS_END 0x00100
  907. #define PX30_DSP_HACT_ST_END 0x00104
  908. #define PX30_DSP_VTOTAL_VS_END 0x00108
  909. #define PX30_DSP_VACT_ST_END 0x0010c
  910. #define PX30_DSP_VS_ST_END_F1 0x00110
  911. #define PX30_DSP_VACT_ST_END_F1 0x00114
  912. #define PX30_BCSH_CTRL 0x00160
  913. #define PX30_BCSH_COL_BAR 0x00164
  914. #define PX30_BCSH_BCS 0x00168
  915. #define PX30_BCSH_H 0x0016c
  916. #define PX30_FRC_LOWER01_0 0x00170
  917. #define PX30_FRC_LOWER01_1 0x00174
  918. #define PX30_FRC_LOWER10_0 0x00178
  919. #define PX30_FRC_LOWER10_1 0x0017c
  920. #define PX30_FRC_LOWER11_0 0x00180
  921. #define PX30_FRC_LOWER11_1 0x00184
  922. #define PX30_MCU_RW_BYPASS_PORT 0x0018c
  923. #define PX30_WIN2_CTRL0 0x00190
  924. #define PX30_WIN2_CTRL1 0x00194
  925. #define PX30_WIN2_VIR0_1 0x00198
  926. #define PX30_WIN2_VIR2_3 0x0019c
  927. #define PX30_WIN2_MST0 0x001a0
  928. #define PX30_WIN2_DSP_INFO0 0x001a4
  929. #define PX30_WIN2_DSP_ST0 0x001a8
  930. #define PX30_WIN2_COLOR_KEY 0x001ac
  931. #define PX30_WIN2_ALPHA_CTRL 0x001bc
  932. #define PX30_BLANKING_VALUE 0x001f4
  933. #define PX30_FLAG_REG_FRM_VALID 0x001f8
  934. #define PX30_FLAG_REG 0x001fc
  935. #define PX30_HWC_LUT_ADDR 0x00600
  936. #define PX30_GAMMA_LUT_ADDR 0x00a00
  937. /* px30 register definition end */
  938. /* rk3188 register definition */
  939. #define RK3188_SYS_CTRL 0x00
  940. #define RK3188_DSP_CTRL0 0x04
  941. #define RK3188_DSP_CTRL1 0x08
  942. #define RK3188_INT_STATUS 0x10
  943. #define RK3188_WIN0_YRGB_MST0 0x20
  944. #define RK3188_WIN0_CBR_MST0 0x24
  945. #define RK3188_WIN0_YRGB_MST1 0x28
  946. #define RK3188_WIN0_CBR_MST1 0x2c
  947. #define RK3188_WIN_VIR 0x30
  948. #define RK3188_WIN0_ACT_INFO 0x34
  949. #define RK3188_WIN0_DSP_INFO 0x38
  950. #define RK3188_WIN0_DSP_ST 0x3c
  951. #define RK3188_WIN0_SCL_FACTOR_YRGB 0x40
  952. #define RK3188_WIN0_SCL_FACTOR_CBR 0x44
  953. #define RK3188_WIN1_MST 0x4c
  954. #define RK3188_WIN1_DSP_INFO 0x50
  955. #define RK3188_WIN1_DSP_ST 0x54
  956. #define RK3188_DSP_HTOTAL_HS_END 0x6c
  957. #define RK3188_DSP_HACT_ST_END 0x70
  958. #define RK3188_DSP_VTOTAL_VS_END 0x74
  959. #define RK3188_DSP_VACT_ST_END 0x78
  960. #define RK3188_REG_CFG_DONE 0x90
  961. /* rk3188 register definition end */
  962. /* rk3066 register definition */
  963. #define RK3066_SYS_CTRL0 0x00
  964. #define RK3066_SYS_CTRL1 0x04
  965. #define RK3066_DSP_CTRL0 0x08
  966. #define RK3066_DSP_CTRL1 0x0c
  967. #define RK3066_INT_STATUS 0x10
  968. #define RK3066_MCU_CTRL 0x14
  969. #define RK3066_BLEND_CTRL 0x18
  970. #define RK3066_WIN0_COLOR_KEY_CTRL 0x1c
  971. #define RK3066_WIN1_COLOR_KEY_CTRL 0x20
  972. #define RK3066_WIN2_COLOR_KEY_CTRL 0x24
  973. #define RK3066_WIN0_YRGB_MST0 0x28
  974. #define RK3066_WIN0_CBR_MST0 0x2c
  975. #define RK3066_WIN0_YRGB_MST1 0x30
  976. #define RK3066_WIN0_CBR_MST1 0x34
  977. #define RK3066_WIN0_VIR 0x38
  978. #define RK3066_WIN0_ACT_INFO 0x3c
  979. #define RK3066_WIN0_DSP_INFO 0x40
  980. #define RK3066_WIN0_DSP_ST 0x44
  981. #define RK3066_WIN0_SCL_FACTOR_YRGB 0x48
  982. #define RK3066_WIN0_SCL_FACTOR_CBR 0x4c
  983. #define RK3066_WIN0_SCL_OFFSET 0x50
  984. #define RK3066_WIN1_YRGB_MST 0x54
  985. #define RK3066_WIN1_CBR_MST 0x58
  986. #define RK3066_WIN1_VIR 0x5c
  987. #define RK3066_WIN1_ACT_INFO 0x60
  988. #define RK3066_WIN1_DSP_INFO 0x64
  989. #define RK3066_WIN1_DSP_ST 0x68
  990. #define RK3066_WIN1_SCL_FACTOR_YRGB 0x6c
  991. #define RK3066_WIN1_SCL_FACTOR_CBR 0x70
  992. #define RK3066_WIN1_SCL_OFFSET 0x74
  993. #define RK3066_WIN2_MST 0x78
  994. #define RK3066_WIN2_VIR 0x7c
  995. #define RK3066_WIN2_DSP_INFO 0x80
  996. #define RK3066_WIN2_DSP_ST 0x84
  997. #define RK3066_HWC_MST 0x88
  998. #define RK3066_HWC_DSP_ST 0x8c
  999. #define RK3066_HWC_COLOR_LUT0 0x90
  1000. #define RK3066_HWC_COLOR_LUT1 0x94
  1001. #define RK3066_HWC_COLOR_LUT2 0x98
  1002. #define RK3066_DSP_HTOTAL_HS_END 0x9c
  1003. #define RK3066_DSP_HACT_ST_END 0xa0
  1004. #define RK3066_DSP_VTOTAL_VS_END 0xa4
  1005. #define RK3066_DSP_VACT_ST_END 0xa8
  1006. #define RK3066_DSP_VS_ST_END_F1 0xac
  1007. #define RK3066_DSP_VACT_ST_END_F1 0xb0
  1008. #define RK3066_REG_CFG_DONE 0xc0
  1009. #define RK3066_MCU_BYPASS_WPORT 0x100
  1010. #define RK3066_MCU_BYPASS_RPORT 0x200
  1011. #define RK3066_WIN2_LUT_ADDR 0x400
  1012. #define RK3066_DSP_LUT_ADDR 0x800
  1013. /* rk3066 register definition end */
  1014. #endif /* _ROCKCHIP_VOP_REG_H */