rockchip_drm_vop.h 9.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  4. * Author:Mark Yao <mark.yao@rock-chips.com>
  5. */
  6. #ifndef _ROCKCHIP_DRM_VOP_H
  7. #define _ROCKCHIP_DRM_VOP_H
  8. /*
  9. * major: IP major version, used for IP structure
  10. * minor: big feature change under same structure
  11. */
  12. #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
  13. #define VOP_MAJOR(version) ((version) >> 8)
  14. #define VOP_MINOR(version) ((version) & 0xff)
  15. #define NUM_YUV2YUV_COEFFICIENTS 12
  16. /* AFBC supports a number of configurable modes. Relevant to us is block size
  17. * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
  18. * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
  19. * could be enabled via the hreg_block_split register, but is not currently
  20. * handled. The colourspace transform is implicitly always assumed by the
  21. * decoder, so consumers must use this transform as well.
  22. *
  23. * Failure to match modifiers will cause errors displaying AFBC buffers
  24. * produced by conformant AFBC producers, including Mesa.
  25. */
  26. #define ROCKCHIP_AFBC_MOD \
  27. DRM_FORMAT_MOD_ARM_AFBC( \
  28. AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
  29. | AFBC_FORMAT_MOD_YTR \
  30. )
  31. enum vop_data_format {
  32. VOP_FMT_ARGB8888 = 0,
  33. VOP_FMT_RGB888,
  34. VOP_FMT_RGB565,
  35. VOP_FMT_YUV420SP = 4,
  36. VOP_FMT_YUV422SP,
  37. VOP_FMT_YUV444SP,
  38. };
  39. struct vop_reg {
  40. uint32_t mask;
  41. uint16_t offset;
  42. uint8_t shift;
  43. bool write_mask;
  44. bool relaxed;
  45. };
  46. struct vop_afbc {
  47. struct vop_reg enable;
  48. struct vop_reg win_sel;
  49. struct vop_reg format;
  50. struct vop_reg hreg_block_split;
  51. struct vop_reg pic_size;
  52. struct vop_reg hdr_ptr;
  53. struct vop_reg rstn;
  54. };
  55. struct vop_modeset {
  56. struct vop_reg htotal_pw;
  57. struct vop_reg hact_st_end;
  58. struct vop_reg hpost_st_end;
  59. struct vop_reg vtotal_pw;
  60. struct vop_reg vact_st_end;
  61. struct vop_reg vpost_st_end;
  62. };
  63. struct vop_output {
  64. struct vop_reg pin_pol;
  65. struct vop_reg dp_pin_pol;
  66. struct vop_reg dp_dclk_pol;
  67. struct vop_reg edp_pin_pol;
  68. struct vop_reg edp_dclk_pol;
  69. struct vop_reg hdmi_pin_pol;
  70. struct vop_reg hdmi_dclk_pol;
  71. struct vop_reg mipi_pin_pol;
  72. struct vop_reg mipi_dclk_pol;
  73. struct vop_reg rgb_pin_pol;
  74. struct vop_reg rgb_dclk_pol;
  75. struct vop_reg dp_en;
  76. struct vop_reg edp_en;
  77. struct vop_reg hdmi_en;
  78. struct vop_reg mipi_en;
  79. struct vop_reg mipi_dual_channel_en;
  80. struct vop_reg rgb_en;
  81. };
  82. struct vop_common {
  83. struct vop_reg cfg_done;
  84. struct vop_reg dsp_blank;
  85. struct vop_reg data_blank;
  86. struct vop_reg pre_dither_down;
  87. struct vop_reg dither_down_sel;
  88. struct vop_reg dither_down_mode;
  89. struct vop_reg dither_down_en;
  90. struct vop_reg dither_up;
  91. struct vop_reg dsp_lut_en;
  92. struct vop_reg gate_en;
  93. struct vop_reg mmu_en;
  94. struct vop_reg out_mode;
  95. struct vop_reg standby;
  96. };
  97. struct vop_misc {
  98. struct vop_reg global_regdone_en;
  99. };
  100. struct vop_intr {
  101. const int *intrs;
  102. uint32_t nintrs;
  103. struct vop_reg line_flag_num[2];
  104. struct vop_reg enable;
  105. struct vop_reg clear;
  106. struct vop_reg status;
  107. };
  108. struct vop_scl_extension {
  109. struct vop_reg cbcr_vsd_mode;
  110. struct vop_reg cbcr_vsu_mode;
  111. struct vop_reg cbcr_hsd_mode;
  112. struct vop_reg cbcr_ver_scl_mode;
  113. struct vop_reg cbcr_hor_scl_mode;
  114. struct vop_reg yrgb_vsd_mode;
  115. struct vop_reg yrgb_vsu_mode;
  116. struct vop_reg yrgb_hsd_mode;
  117. struct vop_reg yrgb_ver_scl_mode;
  118. struct vop_reg yrgb_hor_scl_mode;
  119. struct vop_reg line_load_mode;
  120. struct vop_reg cbcr_axi_gather_num;
  121. struct vop_reg yrgb_axi_gather_num;
  122. struct vop_reg vsd_cbcr_gt2;
  123. struct vop_reg vsd_cbcr_gt4;
  124. struct vop_reg vsd_yrgb_gt2;
  125. struct vop_reg vsd_yrgb_gt4;
  126. struct vop_reg bic_coe_sel;
  127. struct vop_reg cbcr_axi_gather_en;
  128. struct vop_reg yrgb_axi_gather_en;
  129. struct vop_reg lb_mode;
  130. };
  131. struct vop_scl_regs {
  132. const struct vop_scl_extension *ext;
  133. struct vop_reg scale_yrgb_x;
  134. struct vop_reg scale_yrgb_y;
  135. struct vop_reg scale_cbcr_x;
  136. struct vop_reg scale_cbcr_y;
  137. };
  138. struct vop_yuv2yuv_phy {
  139. struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
  140. };
  141. struct vop_win_phy {
  142. const struct vop_scl_regs *scl;
  143. const uint32_t *data_formats;
  144. uint32_t nformats;
  145. const uint64_t *format_modifiers;
  146. struct vop_reg enable;
  147. struct vop_reg gate;
  148. struct vop_reg format;
  149. struct vop_reg rb_swap;
  150. struct vop_reg act_info;
  151. struct vop_reg dsp_info;
  152. struct vop_reg dsp_st;
  153. struct vop_reg yrgb_mst;
  154. struct vop_reg uv_mst;
  155. struct vop_reg yrgb_vir;
  156. struct vop_reg uv_vir;
  157. struct vop_reg y_mir_en;
  158. struct vop_reg x_mir_en;
  159. struct vop_reg dst_alpha_ctl;
  160. struct vop_reg src_alpha_ctl;
  161. struct vop_reg alpha_pre_mul;
  162. struct vop_reg alpha_mode;
  163. struct vop_reg alpha_en;
  164. struct vop_reg channel;
  165. };
  166. struct vop_win_yuv2yuv_data {
  167. uint32_t base;
  168. const struct vop_yuv2yuv_phy *phy;
  169. struct vop_reg y2r_en;
  170. };
  171. struct vop_win_data {
  172. uint32_t base;
  173. const struct vop_win_phy *phy;
  174. enum drm_plane_type type;
  175. };
  176. struct vop_data {
  177. uint32_t version;
  178. const struct vop_intr *intr;
  179. const struct vop_common *common;
  180. const struct vop_misc *misc;
  181. const struct vop_modeset *modeset;
  182. const struct vop_output *output;
  183. const struct vop_afbc *afbc;
  184. const struct vop_win_yuv2yuv_data *win_yuv2yuv;
  185. const struct vop_win_data *win;
  186. unsigned int win_size;
  187. unsigned int lut_size;
  188. #define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
  189. #define VOP_FEATURE_INTERNAL_RGB BIT(1)
  190. u64 feature;
  191. };
  192. /* interrupt define */
  193. #define DSP_HOLD_VALID_INTR (1 << 0)
  194. #define FS_INTR (1 << 1)
  195. #define LINE_FLAG_INTR (1 << 2)
  196. #define BUS_ERROR_INTR (1 << 3)
  197. #define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
  198. LINE_FLAG_INTR | BUS_ERROR_INTR)
  199. #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
  200. #define FS_INTR_EN(x) ((x) << 5)
  201. #define LINE_FLAG_INTR_EN(x) ((x) << 6)
  202. #define BUS_ERROR_INTR_EN(x) ((x) << 7)
  203. #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
  204. #define FS_INTR_MASK (1 << 5)
  205. #define LINE_FLAG_INTR_MASK (1 << 6)
  206. #define BUS_ERROR_INTR_MASK (1 << 7)
  207. #define INTR_CLR_SHIFT 8
  208. #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
  209. #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
  210. #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
  211. #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
  212. #define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
  213. #define DSP_LINE_NUM_MASK (0x1fff << 12)
  214. /* src alpha ctrl define */
  215. #define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
  216. #define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
  217. #define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
  218. #define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
  219. #define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
  220. #define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
  221. #define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
  222. #define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
  223. /* dst alpha ctrl define */
  224. #define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
  225. /*
  226. * display output interface supported by rockchip lcdc
  227. */
  228. #define ROCKCHIP_OUT_MODE_P888 0
  229. #define ROCKCHIP_OUT_MODE_P666 1
  230. #define ROCKCHIP_OUT_MODE_P565 2
  231. /* for use special outface */
  232. #define ROCKCHIP_OUT_MODE_AAAA 15
  233. /* output flags */
  234. #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
  235. enum alpha_mode {
  236. ALPHA_STRAIGHT,
  237. ALPHA_INVERSE,
  238. };
  239. enum global_blend_mode {
  240. ALPHA_GLOBAL,
  241. ALPHA_PER_PIX,
  242. ALPHA_PER_PIX_GLOBAL,
  243. };
  244. enum alpha_cal_mode {
  245. ALPHA_SATURATION,
  246. ALPHA_NO_SATURATION,
  247. };
  248. enum color_mode {
  249. ALPHA_SRC_PRE_MUL,
  250. ALPHA_SRC_NO_PRE_MUL,
  251. };
  252. enum factor_mode {
  253. ALPHA_ZERO,
  254. ALPHA_ONE,
  255. ALPHA_SRC,
  256. ALPHA_SRC_INVERSE,
  257. ALPHA_SRC_GLOBAL,
  258. };
  259. enum scale_mode {
  260. SCALE_NONE = 0x0,
  261. SCALE_UP = 0x1,
  262. SCALE_DOWN = 0x2
  263. };
  264. enum lb_mode {
  265. LB_YUV_3840X5 = 0x0,
  266. LB_YUV_2560X8 = 0x1,
  267. LB_RGB_3840X2 = 0x2,
  268. LB_RGB_2560X4 = 0x3,
  269. LB_RGB_1920X5 = 0x4,
  270. LB_RGB_1280X8 = 0x5
  271. };
  272. enum sacle_up_mode {
  273. SCALE_UP_BIL = 0x0,
  274. SCALE_UP_BIC = 0x1
  275. };
  276. enum scale_down_mode {
  277. SCALE_DOWN_BIL = 0x0,
  278. SCALE_DOWN_AVG = 0x1
  279. };
  280. enum dither_down_mode {
  281. RGB888_TO_RGB565 = 0x0,
  282. RGB888_TO_RGB666 = 0x1
  283. };
  284. enum dither_down_mode_sel {
  285. DITHER_DOWN_ALLEGRO = 0x0,
  286. DITHER_DOWN_FRC = 0x1
  287. };
  288. enum vop_pol {
  289. HSYNC_POSITIVE = 0,
  290. VSYNC_POSITIVE = 1,
  291. DEN_NEGATIVE = 2
  292. };
  293. #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
  294. #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
  295. #define SCL_MAX_VSKIPLINES 4
  296. #define MIN_SCL_FT_AFTER_VSKIP 1
  297. static inline uint16_t scl_cal_scale(int src, int dst, int shift)
  298. {
  299. return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
  300. }
  301. static inline uint16_t scl_cal_scale2(int src, int dst)
  302. {
  303. return ((src - 1) << 12) / (dst - 1);
  304. }
  305. #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
  306. #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
  307. #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
  308. static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
  309. int vskiplines)
  310. {
  311. int act_height;
  312. act_height = DIV_ROUND_UP(src_h, vskiplines);
  313. if (act_height == dst_h)
  314. return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
  315. return GET_SCL_FT_BILI_DN(act_height, dst_h);
  316. }
  317. static inline enum scale_mode scl_get_scl_mode(int src, int dst)
  318. {
  319. if (src < dst)
  320. return SCALE_UP;
  321. else if (src > dst)
  322. return SCALE_DOWN;
  323. return SCALE_NONE;
  324. }
  325. static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
  326. {
  327. uint32_t vskiplines;
  328. for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
  329. if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
  330. break;
  331. return vskiplines;
  332. }
  333. static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
  334. {
  335. int lb_mode;
  336. if (is_yuv) {
  337. if (width > 1280)
  338. lb_mode = LB_YUV_3840X5;
  339. else
  340. lb_mode = LB_YUV_2560X8;
  341. } else {
  342. if (width > 2560)
  343. lb_mode = LB_RGB_3840X2;
  344. else if (width > 1920)
  345. lb_mode = LB_RGB_2560X4;
  346. else
  347. lb_mode = LB_RGB_1920X5;
  348. }
  349. return lb_mode;
  350. }
  351. extern const struct component_ops vop_component_ops;
  352. #endif /* _ROCKCHIP_DRM_VOP_H */