rk3066_hdmi.h 6.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  4. * Zheng Yang <zhengyang@rock-chips.com>
  5. */
  6. #ifndef __RK3066_HDMI_H__
  7. #define __RK3066_HDMI_H__
  8. #define GRF_SOC_CON0 0x150
  9. #define HDMI_VIDEO_SEL BIT(14)
  10. #define DDC_SEGMENT_ADDR 0x30
  11. #define HDMI_SCL_RATE (50 * 1000)
  12. #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
  13. #define N_32K 0x1000
  14. #define N_441K 0x1880
  15. #define N_882K 0x3100
  16. #define N_1764K 0x6200
  17. #define N_48K 0x1800
  18. #define N_96K 0x3000
  19. #define N_192K 0x6000
  20. #define HDMI_SYS_CTRL 0x000
  21. #define HDMI_LR_SWAP_N3 0x004
  22. #define HDMI_N2 0x008
  23. #define HDMI_N1 0x00c
  24. #define HDMI_SPDIF_FS_CTS_INT3 0x010
  25. #define HDMI_CTS_INT2 0x014
  26. #define HDMI_CTS_INT1 0x018
  27. #define HDMI_CTS_EXT3 0x01c
  28. #define HDMI_CTS_EXT2 0x020
  29. #define HDMI_CTS_EXT1 0x024
  30. #define HDMI_AUDIO_CTRL1 0x028
  31. #define HDMI_AUDIO_CTRL2 0x02c
  32. #define HDMI_I2S_AUDIO_CTRL 0x030
  33. #define HDMI_I2S_SWAP 0x040
  34. #define HDMI_AUDIO_STA_BIT_CTRL1 0x044
  35. #define HDMI_AUDIO_STA_BIT_CTRL2 0x048
  36. #define HDMI_AUDIO_SRC_NUM_AND_LENGTH 0x050
  37. #define HDMI_AV_CTRL1 0x054
  38. #define HDMI_VIDEO_CTRL1 0x058
  39. #define HDMI_DEEP_COLOR_MODE 0x05c
  40. #define HDMI_EXT_VIDEO_PARA 0x0c0
  41. #define HDMI_EXT_HTOTAL_L 0x0c4
  42. #define HDMI_EXT_HTOTAL_H 0x0c8
  43. #define HDMI_EXT_HBLANK_L 0x0cc
  44. #define HDMI_EXT_HBLANK_H 0x0d0
  45. #define HDMI_EXT_HDELAY_L 0x0d4
  46. #define HDMI_EXT_HDELAY_H 0x0d8
  47. #define HDMI_EXT_HDURATION_L 0x0dc
  48. #define HDMI_EXT_HDURATION_H 0x0e0
  49. #define HDMI_EXT_VTOTAL_L 0x0e4
  50. #define HDMI_EXT_VTOTAL_H 0x0e8
  51. #define HDMI_AV_CTRL2 0x0ec
  52. #define HDMI_EXT_VBLANK_L 0x0f4
  53. #define HDMI_EXT_VBLANK_H 0x10c
  54. #define HDMI_EXT_VDELAY 0x0f8
  55. #define HDMI_EXT_VDURATION 0x0fc
  56. #define HDMI_CP_MANU_SEND_CTRL 0x100
  57. #define HDMI_CP_AUTO_SEND_CTRL 0x104
  58. #define HDMI_AUTO_CHECKSUM_OPT 0x108
  59. #define HDMI_VIDEO_CTRL2 0x114
  60. #define HDMI_PHY_OPTION 0x144
  61. #define HDMI_CP_BUF_INDEX 0x17c
  62. #define HDMI_CP_BUF_ACC_HB0 0x180
  63. #define HDMI_CP_BUF_ACC_HB1 0x184
  64. #define HDMI_CP_BUF_ACC_HB2 0x188
  65. #define HDMI_CP_BUF_ACC_PB0 0x18c
  66. #define HDMI_DDC_READ_FIFO_ADDR 0x200
  67. #define HDMI_DDC_BUS_FREQ_L 0x204
  68. #define HDMI_DDC_BUS_FREQ_H 0x208
  69. #define HDMI_DDC_BUS_CTRL 0x2dc
  70. #define HDMI_DDC_I2C_LEN 0x278
  71. #define HDMI_DDC_I2C_OFFSET 0x280
  72. #define HDMI_DDC_I2C_CTRL 0x284
  73. #define HDMI_DDC_I2C_READ_BUF0 0x288
  74. #define HDMI_DDC_I2C_READ_BUF1 0x28c
  75. #define HDMI_DDC_I2C_READ_BUF2 0x290
  76. #define HDMI_DDC_I2C_READ_BUF3 0x294
  77. #define HDMI_DDC_I2C_WRITE_BUF0 0x298
  78. #define HDMI_DDC_I2C_WRITE_BUF1 0x29c
  79. #define HDMI_DDC_I2C_WRITE_BUF2 0x2a0
  80. #define HDMI_DDC_I2C_WRITE_BUF3 0x2a4
  81. #define HDMI_DDC_I2C_WRITE_BUF4 0x2ac
  82. #define HDMI_DDC_I2C_WRITE_BUF5 0x2b0
  83. #define HDMI_DDC_I2C_WRITE_BUF6 0x2b4
  84. #define HDMI_INTR_MASK1 0x248
  85. #define HDMI_INTR_MASK2 0x24c
  86. #define HDMI_INTR_STATUS1 0x250
  87. #define HDMI_INTR_STATUS2 0x254
  88. #define HDMI_INTR_MASK3 0x258
  89. #define HDMI_INTR_MASK4 0x25c
  90. #define HDMI_INTR_STATUS3 0x260
  91. #define HDMI_INTR_STATUS4 0x264
  92. #define HDMI_HDCP_CTRL 0x2bc
  93. #define HDMI_EDID_SEGMENT_POINTER 0x310
  94. #define HDMI_EDID_WORD_ADDR 0x314
  95. #define HDMI_EDID_FIFO_ADDR 0x318
  96. #define HDMI_HPG_MENS_STA 0x37c
  97. #define HDMI_INTERNAL_CLK_DIVIDER 0x800
  98. enum {
  99. /* HDMI_SYS_CTRL */
  100. HDMI_SYS_POWER_MODE_MASK = 0xf0,
  101. HDMI_SYS_POWER_MODE_A = 0x10,
  102. HDMI_SYS_POWER_MODE_B = 0x20,
  103. HDMI_SYS_POWER_MODE_D = 0x40,
  104. HDMI_SYS_POWER_MODE_E = 0x80,
  105. HDMI_SYS_PLL_RESET_MASK = 0x0c,
  106. HDMI_SYS_PLL_RESET = 0x0c,
  107. HDMI_SYS_PLLB_RESET = 0x08,
  108. /* HDMI_LR_SWAP_N3 */
  109. HDMI_AUDIO_LR_SWAP_MASK = 0xf0,
  110. HDMI_AUDIO_LR_SWAP_SUBPACKET0 = 0x10,
  111. HDMI_AUDIO_LR_SWAP_SUBPACKET1 = 0x20,
  112. HDMI_AUDIO_LR_SWAP_SUBPACKET2 = 0x40,
  113. HDMI_AUDIO_LR_SWAP_SUBPACKET3 = 0x80,
  114. HDMI_AUDIO_N_19_16_MASK = 0x0f,
  115. /* HDMI_AUDIO_CTRL1 */
  116. HDMI_AUDIO_EXTERNAL_CTS = BIT(7),
  117. HDMI_AUDIO_INPUT_IIS = 0,
  118. HDMI_AUDIO_INPUT_SPDIF = 0x08,
  119. HDMI_AUDIO_INPUT_MCLK_ACTIVE = 0x04,
  120. HDMI_AUDIO_INPUT_MCLK_DEACTIVE = 0,
  121. HDMI_AUDIO_INPUT_MCLK_RATE_128X = 0,
  122. HDMI_AUDIO_INPUT_MCLK_RATE_256X = 1,
  123. HDMI_AUDIO_INPUT_MCLK_RATE_384X = 2,
  124. HDMI_AUDIO_INPUT_MCLK_RATE_512X = 3,
  125. /* HDMI_I2S_AUDIO_CTRL */
  126. HDMI_AUDIO_I2S_FORMAT_STANDARD = 0,
  127. HDMI_AUDIO_I2S_CHANNEL_1_2 = 0x04,
  128. HDMI_AUDIO_I2S_CHANNEL_3_4 = 0x0c,
  129. HDMI_AUDIO_I2S_CHANNEL_5_6 = 0x1c,
  130. HDMI_AUDIO_I2S_CHANNEL_7_8 = 0x3c,
  131. /* HDMI_AV_CTRL1 */
  132. HDMI_AUDIO_SAMPLE_FRE_MASK = 0xf0,
  133. HDMI_AUDIO_SAMPLE_FRE_32000 = 0x30,
  134. HDMI_AUDIO_SAMPLE_FRE_44100 = 0,
  135. HDMI_AUDIO_SAMPLE_FRE_48000 = 0x20,
  136. HDMI_AUDIO_SAMPLE_FRE_88200 = 0x80,
  137. HDMI_AUDIO_SAMPLE_FRE_96000 = 0xa0,
  138. HDMI_AUDIO_SAMPLE_FRE_176400 = 0xc0,
  139. HDMI_AUDIO_SAMPLE_FRE_192000 = 0xe0,
  140. HDMI_AUDIO_SAMPLE_FRE_768000 = 0x90,
  141. HDMI_VIDEO_INPUT_FORMAT_MASK = 0x0e,
  142. HDMI_VIDEO_INPUT_RGB_YCBCR444 = 0,
  143. HDMI_VIDEO_INPUT_YCBCR422 = 0x02,
  144. HDMI_VIDEO_DE_MASK = 0x1,
  145. HDMI_VIDEO_INTERNAL_DE = 0,
  146. HDMI_VIDEO_EXTERNAL_DE = 0x01,
  147. /* HDMI_VIDEO_CTRL1 */
  148. HDMI_VIDEO_OUTPUT_FORMAT_MASK = 0xc0,
  149. HDMI_VIDEO_OUTPUT_RGB444 = 0,
  150. HDMI_VIDEO_OUTPUT_YCBCR444 = 0x40,
  151. HDMI_VIDEO_OUTPUT_YCBCR422 = 0x80,
  152. HDMI_VIDEO_INPUT_DATA_DEPTH_MASK = 0x30,
  153. HDMI_VIDEO_INPUT_DATA_DEPTH_12BIT = 0,
  154. HDMI_VIDEO_INPUT_DATA_DEPTH_10BIT = 0x10,
  155. HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT = 0x30,
  156. HDMI_VIDEO_INPUT_COLOR_MASK = 1,
  157. HDMI_VIDEO_INPUT_COLOR_RGB = 0,
  158. HDMI_VIDEO_INPUT_COLOR_YCBCR = 1,
  159. /* HDMI_EXT_VIDEO_PARA */
  160. HDMI_VIDEO_VSYNC_OFFSET_SHIFT = 4,
  161. HDMI_VIDEO_VSYNC_ACTIVE_HIGH = BIT(3),
  162. HDMI_VIDEO_VSYNC_ACTIVE_LOW = 0,
  163. HDMI_VIDEO_HSYNC_ACTIVE_HIGH = BIT(2),
  164. HDMI_VIDEO_HSYNC_ACTIVE_LOW = 0,
  165. HDMI_VIDEO_MODE_INTERLACE = BIT(1),
  166. HDMI_VIDEO_MODE_PROGRESSIVE = 0,
  167. HDMI_EXT_VIDEO_SET_EN = BIT(0),
  168. /* HDMI_CP_AUTO_SEND_CTRL */
  169. /* HDMI_VIDEO_CTRL2 */
  170. HDMI_VIDEO_AV_MUTE_MASK = 0xc0,
  171. HDMI_VIDEO_CLR_AV_MUTE = BIT(7),
  172. HDMI_VIDEO_SET_AV_MUTE = BIT(6),
  173. HDMI_AUDIO_CP_LOGIC_RESET_MASK = BIT(2),
  174. HDMI_AUDIO_CP_LOGIC_RESET = BIT(2),
  175. HDMI_VIDEO_AUDIO_DISABLE_MASK = 0x3,
  176. HDMI_AUDIO_DISABLE = BIT(1),
  177. HDMI_VIDEO_DISABLE = BIT(0),
  178. /* HDMI_CP_BUF_INDEX */
  179. HDMI_INFOFRAME_VSI = 0x05,
  180. HDMI_INFOFRAME_AVI = 0x06,
  181. HDMI_INFOFRAME_AAI = 0x08,
  182. /* HDMI_INTR_MASK1 */
  183. /* HDMI_INTR_STATUS1 */
  184. HDMI_INTR_HOTPLUG = BIT(7),
  185. HDMI_INTR_MSENS = BIT(6),
  186. HDMI_INTR_VSYNC = BIT(5),
  187. HDMI_INTR_AUDIO_FIFO_FULL = BIT(4),
  188. HDMI_INTR_EDID_MASK = 0x6,
  189. HDMI_INTR_EDID_READY = BIT(2),
  190. HDMI_INTR_EDID_ERR = BIT(1),
  191. /* HDMI_HDCP_CTRL */
  192. HDMI_VIDEO_MODE_MASK = BIT(1),
  193. HDMI_VIDEO_MODE_HDMI = BIT(1),
  194. /* HDMI_HPG_MENS_STA */
  195. HDMI_HPG_IN_STATUS_HIGH = BIT(7),
  196. HDMI_MSENS_IN_STATUS_HIGH = BIT(6),
  197. };
  198. #endif /* __RK3066_HDMI_H__ */