inno_hdmi.h 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  4. * Zheng Yang <zhengyang@rock-chips.com>
  5. * Yakir Yang <ykk@rock-chips.com>
  6. */
  7. #ifndef __INNO_HDMI_H__
  8. #define __INNO_HDMI_H__
  9. #define DDC_SEGMENT_ADDR 0x30
  10. enum PWR_MODE {
  11. NORMAL,
  12. LOWER_PWR,
  13. };
  14. #define HDMI_SCL_RATE (100*1000)
  15. #define DDC_BUS_FREQ_L 0x4b
  16. #define DDC_BUS_FREQ_H 0x4c
  17. #define HDMI_SYS_CTRL 0x00
  18. #define m_RST_ANALOG (1 << 6)
  19. #define v_RST_ANALOG (0 << 6)
  20. #define v_NOT_RST_ANALOG (1 << 6)
  21. #define m_RST_DIGITAL (1 << 5)
  22. #define v_RST_DIGITAL (0 << 5)
  23. #define v_NOT_RST_DIGITAL (1 << 5)
  24. #define m_REG_CLK_INV (1 << 4)
  25. #define v_REG_CLK_NOT_INV (0 << 4)
  26. #define v_REG_CLK_INV (1 << 4)
  27. #define m_VCLK_INV (1 << 3)
  28. #define v_VCLK_NOT_INV (0 << 3)
  29. #define v_VCLK_INV (1 << 3)
  30. #define m_REG_CLK_SOURCE (1 << 2)
  31. #define v_REG_CLK_SOURCE_TMDS (0 << 2)
  32. #define v_REG_CLK_SOURCE_SYS (1 << 2)
  33. #define m_POWER (1 << 1)
  34. #define v_PWR_ON (0 << 1)
  35. #define v_PWR_OFF (1 << 1)
  36. #define m_INT_POL (1 << 0)
  37. #define v_INT_POL_HIGH 1
  38. #define v_INT_POL_LOW 0
  39. #define HDMI_VIDEO_CONTRL1 0x01
  40. #define m_VIDEO_INPUT_FORMAT (7 << 1)
  41. #define m_DE_SOURCE (1 << 0)
  42. #define v_VIDEO_INPUT_FORMAT(n) (n << 1)
  43. #define v_DE_EXTERNAL 1
  44. #define v_DE_INTERNAL 0
  45. enum {
  46. VIDEO_INPUT_SDR_RGB444 = 0,
  47. VIDEO_INPUT_DDR_RGB444 = 5,
  48. VIDEO_INPUT_DDR_YCBCR422 = 6
  49. };
  50. #define HDMI_VIDEO_CONTRL2 0x02
  51. #define m_VIDEO_OUTPUT_COLOR (3 << 6)
  52. #define m_VIDEO_INPUT_BITS (3 << 4)
  53. #define m_VIDEO_INPUT_CSP (1 << 0)
  54. #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6)
  55. #define v_VIDEO_INPUT_BITS(n) (n << 4)
  56. #define v_VIDEO_INPUT_CSP(n) (n << 0)
  57. enum {
  58. VIDEO_INPUT_12BITS = 0,
  59. VIDEO_INPUT_10BITS = 1,
  60. VIDEO_INPUT_REVERT = 2,
  61. VIDEO_INPUT_8BITS = 3,
  62. };
  63. #define HDMI_VIDEO_CONTRL 0x03
  64. #define m_VIDEO_AUTO_CSC (1 << 7)
  65. #define v_VIDEO_AUTO_CSC(n) (n << 7)
  66. #define m_VIDEO_C0_C2_SWAP (1 << 0)
  67. #define v_VIDEO_C0_C2_SWAP(n) (n << 0)
  68. enum {
  69. C0_C2_CHANGE_ENABLE = 0,
  70. C0_C2_CHANGE_DISABLE = 1,
  71. AUTO_CSC_DISABLE = 0,
  72. AUTO_CSC_ENABLE = 1,
  73. };
  74. #define HDMI_VIDEO_CONTRL3 0x04
  75. #define m_COLOR_DEPTH_NOT_INDICATED (1 << 4)
  76. #define m_SOF (1 << 3)
  77. #define m_COLOR_RANGE (1 << 2)
  78. #define m_CSC (1 << 0)
  79. #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4)
  80. #define v_SOF_ENABLE (0 << 3)
  81. #define v_SOF_DISABLE (1 << 3)
  82. #define v_COLOR_RANGE_FULL (1 << 2)
  83. #define v_COLOR_RANGE_LIMITED (0 << 2)
  84. #define v_CSC_ENABLE 1
  85. #define v_CSC_DISABLE 0
  86. #define HDMI_AV_MUTE 0x05
  87. #define m_AVMUTE_CLEAR (1 << 7)
  88. #define m_AVMUTE_ENABLE (1 << 6)
  89. #define m_AUDIO_MUTE (1 << 1)
  90. #define m_VIDEO_BLACK (1 << 0)
  91. #define v_AVMUTE_CLEAR(n) (n << 7)
  92. #define v_AVMUTE_ENABLE(n) (n << 6)
  93. #define v_AUDIO_MUTE(n) (n << 1)
  94. #define v_VIDEO_MUTE(n) (n << 0)
  95. #define HDMI_VIDEO_TIMING_CTL 0x08
  96. #define v_HSYNC_POLARITY(n) (n << 3)
  97. #define v_VSYNC_POLARITY(n) (n << 2)
  98. #define v_INETLACE(n) (n << 1)
  99. #define v_EXTERANL_VIDEO(n) (n << 0)
  100. #define HDMI_VIDEO_EXT_HTOTAL_L 0x09
  101. #define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
  102. #define HDMI_VIDEO_EXT_HBLANK_L 0x0b
  103. #define HDMI_VIDEO_EXT_HBLANK_H 0x0c
  104. #define HDMI_VIDEO_EXT_HDELAY_L 0x0d
  105. #define HDMI_VIDEO_EXT_HDELAY_H 0x0e
  106. #define HDMI_VIDEO_EXT_HDURATION_L 0x0f
  107. #define HDMI_VIDEO_EXT_HDURATION_H 0x10
  108. #define HDMI_VIDEO_EXT_VTOTAL_L 0x11
  109. #define HDMI_VIDEO_EXT_VTOTAL_H 0x12
  110. #define HDMI_VIDEO_EXT_VBLANK 0x13
  111. #define HDMI_VIDEO_EXT_VDELAY 0x14
  112. #define HDMI_VIDEO_EXT_VDURATION 0x15
  113. #define HDMI_VIDEO_CSC_COEF 0x18
  114. #define HDMI_AUDIO_CTRL1 0x35
  115. enum {
  116. CTS_SOURCE_INTERNAL = 0,
  117. CTS_SOURCE_EXTERNAL = 1,
  118. };
  119. #define v_CTS_SOURCE(n) (n << 7)
  120. enum {
  121. DOWNSAMPLE_DISABLE = 0,
  122. DOWNSAMPLE_1_2 = 1,
  123. DOWNSAMPLE_1_4 = 2,
  124. };
  125. #define v_DOWN_SAMPLE(n) (n << 5)
  126. enum {
  127. AUDIO_SOURCE_IIS = 0,
  128. AUDIO_SOURCE_SPDIF = 1,
  129. };
  130. #define v_AUDIO_SOURCE(n) (n << 3)
  131. #define v_MCLK_ENABLE(n) (n << 2)
  132. enum {
  133. MCLK_128FS = 0,
  134. MCLK_256FS = 1,
  135. MCLK_384FS = 2,
  136. MCLK_512FS = 3,
  137. };
  138. #define v_MCLK_RATIO(n) (n)
  139. #define AUDIO_SAMPLE_RATE 0x37
  140. enum {
  141. AUDIO_32K = 0x3,
  142. AUDIO_441K = 0x0,
  143. AUDIO_48K = 0x2,
  144. AUDIO_882K = 0x8,
  145. AUDIO_96K = 0xa,
  146. AUDIO_1764K = 0xc,
  147. AUDIO_192K = 0xe,
  148. };
  149. #define AUDIO_I2S_MODE 0x38
  150. enum {
  151. I2S_CHANNEL_1_2 = 1,
  152. I2S_CHANNEL_3_4 = 3,
  153. I2S_CHANNEL_5_6 = 7,
  154. I2S_CHANNEL_7_8 = 0xf
  155. };
  156. #define v_I2S_CHANNEL(n) ((n) << 2)
  157. enum {
  158. I2S_STANDARD = 0,
  159. I2S_LEFT_JUSTIFIED = 1,
  160. I2S_RIGHT_JUSTIFIED = 2,
  161. };
  162. #define v_I2S_MODE(n) (n)
  163. #define AUDIO_I2S_MAP 0x39
  164. #define AUDIO_I2S_SWAPS_SPDIF 0x3a
  165. #define v_SPIDF_FREQ(n) (n)
  166. #define N_32K 0x1000
  167. #define N_441K 0x1880
  168. #define N_882K 0x3100
  169. #define N_1764K 0x6200
  170. #define N_48K 0x1800
  171. #define N_96K 0x3000
  172. #define N_192K 0x6000
  173. #define HDMI_AUDIO_CHANNEL_STATUS 0x3e
  174. #define m_AUDIO_STATUS_NLPCM (1 << 7)
  175. #define m_AUDIO_STATUS_USE (1 << 6)
  176. #define m_AUDIO_STATUS_COPYRIGHT (1 << 5)
  177. #define m_AUDIO_STATUS_ADDITION (3 << 2)
  178. #define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0)
  179. #define v_AUDIO_STATUS_NLPCM(n) ((n & 1) << 7)
  180. #define AUDIO_N_H 0x3f
  181. #define AUDIO_N_M 0x40
  182. #define AUDIO_N_L 0x41
  183. #define HDMI_AUDIO_CTS_H 0x45
  184. #define HDMI_AUDIO_CTS_M 0x46
  185. #define HDMI_AUDIO_CTS_L 0x47
  186. #define HDMI_DDC_CLK_L 0x4b
  187. #define HDMI_DDC_CLK_H 0x4c
  188. #define HDMI_EDID_SEGMENT_POINTER 0x4d
  189. #define HDMI_EDID_WORD_ADDR 0x4e
  190. #define HDMI_EDID_FIFO_OFFSET 0x4f
  191. #define HDMI_EDID_FIFO_ADDR 0x50
  192. #define HDMI_PACKET_SEND_MANUAL 0x9c
  193. #define HDMI_PACKET_SEND_AUTO 0x9d
  194. #define m_PACKET_GCP_EN (1 << 7)
  195. #define m_PACKET_MSI_EN (1 << 6)
  196. #define m_PACKET_SDI_EN (1 << 5)
  197. #define m_PACKET_VSI_EN (1 << 4)
  198. #define v_PACKET_GCP_EN(n) ((n & 1) << 7)
  199. #define v_PACKET_MSI_EN(n) ((n & 1) << 6)
  200. #define v_PACKET_SDI_EN(n) ((n & 1) << 5)
  201. #define v_PACKET_VSI_EN(n) ((n & 1) << 4)
  202. #define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
  203. enum {
  204. INFOFRAME_VSI = 0x05,
  205. INFOFRAME_AVI = 0x06,
  206. INFOFRAME_AAI = 0x08,
  207. };
  208. #define HDMI_CONTROL_PACKET_ADDR 0xa0
  209. #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
  210. enum {
  211. AVI_COLOR_MODE_RGB = 0,
  212. AVI_COLOR_MODE_YCBCR422 = 1,
  213. AVI_COLOR_MODE_YCBCR444 = 2,
  214. AVI_COLORIMETRY_NO_DATA = 0,
  215. AVI_COLORIMETRY_SMPTE_170M = 1,
  216. AVI_COLORIMETRY_ITU709 = 2,
  217. AVI_COLORIMETRY_EXTENDED = 3,
  218. AVI_CODED_FRAME_ASPECT_NO_DATA = 0,
  219. AVI_CODED_FRAME_ASPECT_4_3 = 1,
  220. AVI_CODED_FRAME_ASPECT_16_9 = 2,
  221. ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08,
  222. ACTIVE_ASPECT_RATE_4_3 = 0x09,
  223. ACTIVE_ASPECT_RATE_16_9 = 0x0A,
  224. ACTIVE_ASPECT_RATE_14_9 = 0x0B,
  225. };
  226. #define HDMI_HDCP_CTRL 0x52
  227. #define m_HDMI_DVI (1 << 1)
  228. #define v_HDMI_DVI(n) (n << 1)
  229. #define HDMI_INTERRUPT_MASK1 0xc0
  230. #define HDMI_INTERRUPT_STATUS1 0xc1
  231. #define m_INT_ACTIVE_VSYNC (1 << 5)
  232. #define m_INT_EDID_READY (1 << 2)
  233. #define HDMI_INTERRUPT_MASK2 0xc2
  234. #define HDMI_INTERRUPT_STATUS2 0xc3
  235. #define m_INT_HDCP_ERR (1 << 7)
  236. #define m_INT_BKSV_FLAG (1 << 6)
  237. #define m_INT_HDCP_OK (1 << 4)
  238. #define HDMI_STATUS 0xc8
  239. #define m_HOTPLUG (1 << 7)
  240. #define m_MASK_INT_HOTPLUG (1 << 5)
  241. #define m_INT_HOTPLUG (1 << 1)
  242. #define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
  243. #define HDMI_COLORBAR 0xc9
  244. #define HDMI_PHY_SYNC 0xce
  245. #define HDMI_PHY_SYS_CTL 0xe0
  246. #define m_TMDS_CLK_SOURCE (1 << 5)
  247. #define v_TMDS_FROM_PLL (0 << 5)
  248. #define v_TMDS_FROM_GEN (1 << 5)
  249. #define m_PHASE_CLK (1 << 4)
  250. #define v_DEFAULT_PHASE (0 << 4)
  251. #define v_SYNC_PHASE (1 << 4)
  252. #define m_TMDS_CURRENT_PWR (1 << 3)
  253. #define v_TURN_ON_CURRENT (0 << 3)
  254. #define v_CAT_OFF_CURRENT (1 << 3)
  255. #define m_BANDGAP_PWR (1 << 2)
  256. #define v_BANDGAP_PWR_UP (0 << 2)
  257. #define v_BANDGAP_PWR_DOWN (1 << 2)
  258. #define m_PLL_PWR (1 << 1)
  259. #define v_PLL_PWR_UP (0 << 1)
  260. #define v_PLL_PWR_DOWN (1 << 1)
  261. #define m_TMDS_CHG_PWR (1 << 0)
  262. #define v_TMDS_CHG_PWR_UP (0 << 0)
  263. #define v_TMDS_CHG_PWR_DOWN (1 << 0)
  264. #define HDMI_PHY_CHG_PWR 0xe1
  265. #define v_CLK_CHG_PWR(n) ((n & 1) << 3)
  266. #define v_DATA_CHG_PWR(n) ((n & 7) << 0)
  267. #define HDMI_PHY_DRIVER 0xe2
  268. #define v_CLK_MAIN_DRIVER(n) (n << 4)
  269. #define v_DATA_MAIN_DRIVER(n) (n << 0)
  270. #define HDMI_PHY_PRE_EMPHASIS 0xe3
  271. #define v_PRE_EMPHASIS(n) ((n & 7) << 4)
  272. #define v_CLK_PRE_DRIVER(n) ((n & 3) << 2)
  273. #define v_DATA_PRE_DRIVER(n) ((n & 3) << 0)
  274. #define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
  275. #define v_FEEDBACK_DIV_LOW(n) (n & 0xff)
  276. #define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
  277. #define v_FEEDBACK_DIV_HIGH(n) (n & 1)
  278. #define HDMI_PHY_PRE_DIV_RATIO 0xed
  279. #define v_PRE_DIV_RATIO(n) (n & 0x1f)
  280. #define HDMI_CEC_CTRL 0xd0
  281. #define m_ADJUST_FOR_HISENSE (1 << 6)
  282. #define m_REJECT_RX_BROADCAST (1 << 5)
  283. #define m_BUSFREETIME_ENABLE (1 << 2)
  284. #define m_REJECT_RX (1 << 1)
  285. #define m_START_TX (1 << 0)
  286. #define HDMI_CEC_DATA 0xd1
  287. #define HDMI_CEC_TX_OFFSET 0xd2
  288. #define HDMI_CEC_RX_OFFSET 0xd3
  289. #define HDMI_CEC_CLK_H 0xd4
  290. #define HDMI_CEC_CLK_L 0xd5
  291. #define HDMI_CEC_TX_LENGTH 0xd6
  292. #define HDMI_CEC_RX_LENGTH 0xd7
  293. #define HDMI_CEC_TX_INT_MASK 0xd8
  294. #define m_TX_DONE (1 << 3)
  295. #define m_TX_NOACK (1 << 2)
  296. #define m_TX_BROADCAST_REJ (1 << 1)
  297. #define m_TX_BUSNOTFREE (1 << 0)
  298. #define HDMI_CEC_RX_INT_MASK 0xd9
  299. #define m_RX_LA_ERR (1 << 4)
  300. #define m_RX_GLITCH (1 << 3)
  301. #define m_RX_DONE (1 << 0)
  302. #define HDMI_CEC_TX_INT 0xda
  303. #define HDMI_CEC_RX_INT 0xdb
  304. #define HDMI_CEC_BUSFREETIME_L 0xdc
  305. #define HDMI_CEC_BUSFREETIME_H 0xdd
  306. #define HDMI_CEC_LOGICADDR 0xde
  307. #endif /* __INNO_HDMI_H__ */