dw_hdmi-rockchip.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/mfd/syscon.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/phy/phy.h>
  10. #include <linux/regmap.h>
  11. #include <drm/bridge/dw_hdmi.h>
  12. #include <drm/drm_edid.h>
  13. #include <drm/drm_of.h>
  14. #include <drm/drm_probe_helper.h>
  15. #include <drm/drm_simple_kms_helper.h>
  16. #include "rockchip_drm_drv.h"
  17. #include "rockchip_drm_vop.h"
  18. #define RK3228_GRF_SOC_CON2 0x0408
  19. #define RK3228_HDMI_SDAIN_MSK BIT(14)
  20. #define RK3228_HDMI_SCLIN_MSK BIT(13)
  21. #define RK3228_GRF_SOC_CON6 0x0418
  22. #define RK3228_HDMI_HPD_VSEL BIT(6)
  23. #define RK3228_HDMI_SDA_VSEL BIT(5)
  24. #define RK3228_HDMI_SCL_VSEL BIT(4)
  25. #define RK3288_GRF_SOC_CON6 0x025C
  26. #define RK3288_HDMI_LCDC_SEL BIT(4)
  27. #define RK3328_GRF_SOC_CON2 0x0408
  28. #define RK3328_HDMI_SDAIN_MSK BIT(11)
  29. #define RK3328_HDMI_SCLIN_MSK BIT(10)
  30. #define RK3328_HDMI_HPD_IOE BIT(2)
  31. #define RK3328_GRF_SOC_CON3 0x040c
  32. /* need to be unset if hdmi or i2c should control voltage */
  33. #define RK3328_HDMI_SDA5V_GRF BIT(15)
  34. #define RK3328_HDMI_SCL5V_GRF BIT(14)
  35. #define RK3328_HDMI_HPD5V_GRF BIT(13)
  36. #define RK3328_HDMI_CEC5V_GRF BIT(12)
  37. #define RK3328_GRF_SOC_CON4 0x0410
  38. #define RK3328_HDMI_HPD_SARADC BIT(13)
  39. #define RK3328_HDMI_CEC_5V BIT(11)
  40. #define RK3328_HDMI_SDA_5V BIT(10)
  41. #define RK3328_HDMI_SCL_5V BIT(9)
  42. #define RK3328_HDMI_HPD_5V BIT(8)
  43. #define RK3399_GRF_SOC_CON20 0x6250
  44. #define RK3399_HDMI_LCDC_SEL BIT(6)
  45. #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
  46. /**
  47. * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
  48. * @lcdsel_grf_reg: grf register offset of lcdc select
  49. * @lcdsel_big: reg value of selecting vop big for HDMI
  50. * @lcdsel_lit: reg value of selecting vop little for HDMI
  51. */
  52. struct rockchip_hdmi_chip_data {
  53. int lcdsel_grf_reg;
  54. u32 lcdsel_big;
  55. u32 lcdsel_lit;
  56. };
  57. struct rockchip_hdmi {
  58. struct device *dev;
  59. struct regmap *regmap;
  60. struct drm_encoder encoder;
  61. const struct rockchip_hdmi_chip_data *chip_data;
  62. struct clk *vpll_clk;
  63. struct clk *grf_clk;
  64. struct dw_hdmi *hdmi;
  65. struct phy *phy;
  66. };
  67. #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
  68. static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
  69. {
  70. 27000000, {
  71. { 0x00b3, 0x0000},
  72. { 0x2153, 0x0000},
  73. { 0x40f3, 0x0000}
  74. },
  75. }, {
  76. 36000000, {
  77. { 0x00b3, 0x0000},
  78. { 0x2153, 0x0000},
  79. { 0x40f3, 0x0000}
  80. },
  81. }, {
  82. 40000000, {
  83. { 0x00b3, 0x0000},
  84. { 0x2153, 0x0000},
  85. { 0x40f3, 0x0000}
  86. },
  87. }, {
  88. 54000000, {
  89. { 0x0072, 0x0001},
  90. { 0x2142, 0x0001},
  91. { 0x40a2, 0x0001},
  92. },
  93. }, {
  94. 65000000, {
  95. { 0x0072, 0x0001},
  96. { 0x2142, 0x0001},
  97. { 0x40a2, 0x0001},
  98. },
  99. }, {
  100. 66000000, {
  101. { 0x013e, 0x0003},
  102. { 0x217e, 0x0002},
  103. { 0x4061, 0x0002}
  104. },
  105. }, {
  106. 74250000, {
  107. { 0x0072, 0x0001},
  108. { 0x2145, 0x0002},
  109. { 0x4061, 0x0002}
  110. },
  111. }, {
  112. 83500000, {
  113. { 0x0072, 0x0001},
  114. },
  115. }, {
  116. 108000000, {
  117. { 0x0051, 0x0002},
  118. { 0x2145, 0x0002},
  119. { 0x4061, 0x0002}
  120. },
  121. }, {
  122. 106500000, {
  123. { 0x0051, 0x0002},
  124. { 0x2145, 0x0002},
  125. { 0x4061, 0x0002}
  126. },
  127. }, {
  128. 146250000, {
  129. { 0x0051, 0x0002},
  130. { 0x2145, 0x0002},
  131. { 0x4061, 0x0002}
  132. },
  133. }, {
  134. 148500000, {
  135. { 0x0051, 0x0003},
  136. { 0x214c, 0x0003},
  137. { 0x4064, 0x0003}
  138. },
  139. }, {
  140. ~0UL, {
  141. { 0x00a0, 0x000a },
  142. { 0x2001, 0x000f },
  143. { 0x4002, 0x000f },
  144. },
  145. }
  146. };
  147. static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
  148. /* pixelclk bpp8 bpp10 bpp12 */
  149. {
  150. 40000000, { 0x0018, 0x0018, 0x0018 },
  151. }, {
  152. 65000000, { 0x0028, 0x0028, 0x0028 },
  153. }, {
  154. 66000000, { 0x0038, 0x0038, 0x0038 },
  155. }, {
  156. 74250000, { 0x0028, 0x0038, 0x0038 },
  157. }, {
  158. 83500000, { 0x0028, 0x0038, 0x0038 },
  159. }, {
  160. 146250000, { 0x0038, 0x0038, 0x0038 },
  161. }, {
  162. 148500000, { 0x0000, 0x0038, 0x0038 },
  163. }, {
  164. ~0UL, { 0x0000, 0x0000, 0x0000},
  165. }
  166. };
  167. static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
  168. /*pixelclk symbol term vlev*/
  169. { 74250000, 0x8009, 0x0004, 0x0272},
  170. { 148500000, 0x802b, 0x0004, 0x028d},
  171. { 297000000, 0x8039, 0x0005, 0x028d},
  172. { ~0UL, 0x0000, 0x0000, 0x0000}
  173. };
  174. static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
  175. {
  176. struct device_node *np = hdmi->dev->of_node;
  177. hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  178. if (IS_ERR(hdmi->regmap)) {
  179. DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
  180. return PTR_ERR(hdmi->regmap);
  181. }
  182. hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
  183. if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
  184. hdmi->vpll_clk = NULL;
  185. } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
  186. return -EPROBE_DEFER;
  187. } else if (IS_ERR(hdmi->vpll_clk)) {
  188. DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
  189. return PTR_ERR(hdmi->vpll_clk);
  190. }
  191. hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
  192. if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
  193. hdmi->grf_clk = NULL;
  194. } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
  195. return -EPROBE_DEFER;
  196. } else if (IS_ERR(hdmi->grf_clk)) {
  197. DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
  198. return PTR_ERR(hdmi->grf_clk);
  199. }
  200. return 0;
  201. }
  202. static enum drm_mode_status
  203. dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
  204. const struct drm_display_info *info,
  205. const struct drm_display_mode *mode)
  206. {
  207. const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
  208. int pclk = mode->clock * 1000;
  209. bool valid = false;
  210. int i;
  211. for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
  212. if (pclk == mpll_cfg[i].mpixelclock) {
  213. valid = true;
  214. break;
  215. }
  216. }
  217. return (valid) ? MODE_OK : MODE_BAD;
  218. }
  219. static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
  220. {
  221. }
  222. static bool
  223. dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
  224. const struct drm_display_mode *mode,
  225. struct drm_display_mode *adj_mode)
  226. {
  227. return true;
  228. }
  229. static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
  230. struct drm_display_mode *mode,
  231. struct drm_display_mode *adj_mode)
  232. {
  233. struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
  234. clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
  235. }
  236. static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
  237. {
  238. struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
  239. u32 val;
  240. int ret;
  241. if (hdmi->chip_data->lcdsel_grf_reg < 0)
  242. return;
  243. ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
  244. if (ret)
  245. val = hdmi->chip_data->lcdsel_lit;
  246. else
  247. val = hdmi->chip_data->lcdsel_big;
  248. ret = clk_prepare_enable(hdmi->grf_clk);
  249. if (ret < 0) {
  250. DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
  251. return;
  252. }
  253. ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
  254. if (ret != 0)
  255. DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
  256. clk_disable_unprepare(hdmi->grf_clk);
  257. DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
  258. ret ? "LIT" : "BIG");
  259. }
  260. static int
  261. dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
  262. struct drm_crtc_state *crtc_state,
  263. struct drm_connector_state *conn_state)
  264. {
  265. struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
  266. s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
  267. s->output_type = DRM_MODE_CONNECTOR_HDMIA;
  268. return 0;
  269. }
  270. static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
  271. .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
  272. .mode_set = dw_hdmi_rockchip_encoder_mode_set,
  273. .enable = dw_hdmi_rockchip_encoder_enable,
  274. .disable = dw_hdmi_rockchip_encoder_disable,
  275. .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
  276. };
  277. static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
  278. const struct drm_display_info *display,
  279. const struct drm_display_mode *mode)
  280. {
  281. struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
  282. return phy_power_on(hdmi->phy);
  283. }
  284. static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
  285. {
  286. struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
  287. phy_power_off(hdmi->phy);
  288. }
  289. static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
  290. {
  291. struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
  292. dw_hdmi_phy_setup_hpd(dw_hdmi, data);
  293. regmap_write(hdmi->regmap,
  294. RK3228_GRF_SOC_CON6,
  295. HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
  296. RK3228_HDMI_SCL_VSEL,
  297. RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
  298. RK3228_HDMI_SCL_VSEL));
  299. regmap_write(hdmi->regmap,
  300. RK3228_GRF_SOC_CON2,
  301. HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
  302. RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
  303. }
  304. static enum drm_connector_status
  305. dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
  306. {
  307. struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
  308. enum drm_connector_status status;
  309. status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
  310. if (status == connector_status_connected)
  311. regmap_write(hdmi->regmap,
  312. RK3328_GRF_SOC_CON4,
  313. HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
  314. RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
  315. else
  316. regmap_write(hdmi->regmap,
  317. RK3328_GRF_SOC_CON4,
  318. HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
  319. RK3328_HDMI_SCL_5V));
  320. return status;
  321. }
  322. static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
  323. {
  324. struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
  325. dw_hdmi_phy_setup_hpd(dw_hdmi, data);
  326. /* Enable and map pins to 3V grf-controlled io-voltage */
  327. regmap_write(hdmi->regmap,
  328. RK3328_GRF_SOC_CON4,
  329. HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
  330. RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
  331. RK3328_HDMI_HPD_5V));
  332. regmap_write(hdmi->regmap,
  333. RK3328_GRF_SOC_CON3,
  334. HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
  335. RK3328_HDMI_HPD5V_GRF |
  336. RK3328_HDMI_CEC5V_GRF));
  337. regmap_write(hdmi->regmap,
  338. RK3328_GRF_SOC_CON2,
  339. HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
  340. RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
  341. RK3328_HDMI_HPD_IOE));
  342. }
  343. static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
  344. .init = dw_hdmi_rockchip_genphy_init,
  345. .disable = dw_hdmi_rockchip_genphy_disable,
  346. .read_hpd = dw_hdmi_phy_read_hpd,
  347. .update_hpd = dw_hdmi_phy_update_hpd,
  348. .setup_hpd = dw_hdmi_rk3228_setup_hpd,
  349. };
  350. static struct rockchip_hdmi_chip_data rk3228_chip_data = {
  351. .lcdsel_grf_reg = -1,
  352. };
  353. static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
  354. .mode_valid = dw_hdmi_rockchip_mode_valid,
  355. .mpll_cfg = rockchip_mpll_cfg,
  356. .cur_ctr = rockchip_cur_ctr,
  357. .phy_config = rockchip_phy_config,
  358. .phy_data = &rk3228_chip_data,
  359. .phy_ops = &rk3228_hdmi_phy_ops,
  360. .phy_name = "inno_dw_hdmi_phy2",
  361. .phy_force_vendor = true,
  362. };
  363. static struct rockchip_hdmi_chip_data rk3288_chip_data = {
  364. .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
  365. .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
  366. .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
  367. };
  368. static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
  369. .mode_valid = dw_hdmi_rockchip_mode_valid,
  370. .mpll_cfg = rockchip_mpll_cfg,
  371. .cur_ctr = rockchip_cur_ctr,
  372. .phy_config = rockchip_phy_config,
  373. .phy_data = &rk3288_chip_data,
  374. };
  375. static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
  376. .init = dw_hdmi_rockchip_genphy_init,
  377. .disable = dw_hdmi_rockchip_genphy_disable,
  378. .read_hpd = dw_hdmi_rk3328_read_hpd,
  379. .update_hpd = dw_hdmi_phy_update_hpd,
  380. .setup_hpd = dw_hdmi_rk3328_setup_hpd,
  381. };
  382. static struct rockchip_hdmi_chip_data rk3328_chip_data = {
  383. .lcdsel_grf_reg = -1,
  384. };
  385. static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
  386. .mode_valid = dw_hdmi_rockchip_mode_valid,
  387. .mpll_cfg = rockchip_mpll_cfg,
  388. .cur_ctr = rockchip_cur_ctr,
  389. .phy_config = rockchip_phy_config,
  390. .phy_data = &rk3328_chip_data,
  391. .phy_ops = &rk3328_hdmi_phy_ops,
  392. .phy_name = "inno_dw_hdmi_phy2",
  393. .phy_force_vendor = true,
  394. .use_drm_infoframe = true,
  395. };
  396. static struct rockchip_hdmi_chip_data rk3399_chip_data = {
  397. .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
  398. .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
  399. .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
  400. };
  401. static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
  402. .mode_valid = dw_hdmi_rockchip_mode_valid,
  403. .mpll_cfg = rockchip_mpll_cfg,
  404. .cur_ctr = rockchip_cur_ctr,
  405. .phy_config = rockchip_phy_config,
  406. .phy_data = &rk3399_chip_data,
  407. .use_drm_infoframe = true,
  408. };
  409. static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
  410. { .compatible = "rockchip,rk3228-dw-hdmi",
  411. .data = &rk3228_hdmi_drv_data
  412. },
  413. { .compatible = "rockchip,rk3288-dw-hdmi",
  414. .data = &rk3288_hdmi_drv_data
  415. },
  416. { .compatible = "rockchip,rk3328-dw-hdmi",
  417. .data = &rk3328_hdmi_drv_data
  418. },
  419. { .compatible = "rockchip,rk3399-dw-hdmi",
  420. .data = &rk3399_hdmi_drv_data
  421. },
  422. {},
  423. };
  424. MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
  425. static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
  426. void *data)
  427. {
  428. struct platform_device *pdev = to_platform_device(dev);
  429. struct dw_hdmi_plat_data *plat_data;
  430. const struct of_device_id *match;
  431. struct drm_device *drm = data;
  432. struct drm_encoder *encoder;
  433. struct rockchip_hdmi *hdmi;
  434. int ret;
  435. if (!pdev->dev.of_node)
  436. return -ENODEV;
  437. hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
  438. if (!hdmi)
  439. return -ENOMEM;
  440. match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
  441. plat_data = devm_kmemdup(&pdev->dev, match->data,
  442. sizeof(*plat_data), GFP_KERNEL);
  443. if (!plat_data)
  444. return -ENOMEM;
  445. hdmi->dev = &pdev->dev;
  446. hdmi->chip_data = plat_data->phy_data;
  447. plat_data->phy_data = hdmi;
  448. encoder = &hdmi->encoder;
  449. encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
  450. /*
  451. * If we failed to find the CRTC(s) which this encoder is
  452. * supposed to be connected to, it's because the CRTC has
  453. * not been registered yet. Defer probing, and hope that
  454. * the required CRTC is added later.
  455. */
  456. if (encoder->possible_crtcs == 0)
  457. return -EPROBE_DEFER;
  458. ret = rockchip_hdmi_parse_dt(hdmi);
  459. if (ret) {
  460. DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
  461. return ret;
  462. }
  463. hdmi->phy = devm_phy_optional_get(dev, "hdmi");
  464. if (IS_ERR(hdmi->phy)) {
  465. ret = PTR_ERR(hdmi->phy);
  466. if (ret != -EPROBE_DEFER)
  467. DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
  468. return ret;
  469. }
  470. ret = clk_prepare_enable(hdmi->vpll_clk);
  471. if (ret) {
  472. DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
  473. ret);
  474. return ret;
  475. }
  476. drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
  477. drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
  478. platform_set_drvdata(pdev, hdmi);
  479. hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
  480. /*
  481. * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
  482. * which would have called the encoder cleanup. Do it manually.
  483. */
  484. if (IS_ERR(hdmi->hdmi)) {
  485. ret = PTR_ERR(hdmi->hdmi);
  486. drm_encoder_cleanup(encoder);
  487. clk_disable_unprepare(hdmi->vpll_clk);
  488. }
  489. return ret;
  490. }
  491. static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
  492. void *data)
  493. {
  494. struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
  495. dw_hdmi_unbind(hdmi->hdmi);
  496. clk_disable_unprepare(hdmi->vpll_clk);
  497. }
  498. static const struct component_ops dw_hdmi_rockchip_ops = {
  499. .bind = dw_hdmi_rockchip_bind,
  500. .unbind = dw_hdmi_rockchip_unbind,
  501. };
  502. static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
  503. {
  504. return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
  505. }
  506. static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
  507. {
  508. component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
  509. return 0;
  510. }
  511. static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
  512. {
  513. struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
  514. dw_hdmi_resume(hdmi->hdmi);
  515. return 0;
  516. }
  517. static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
  518. SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
  519. };
  520. struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
  521. .probe = dw_hdmi_rockchip_probe,
  522. .remove = dw_hdmi_rockchip_remove,
  523. .driver = {
  524. .name = "dwhdmi-rockchip",
  525. .pm = &dw_hdmi_rockchip_pm,
  526. .of_match_table = dw_hdmi_rockchip_dt_ids,
  527. },
  528. };