dw-mipi-dsi-rockchip.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  4. * Author:
  5. * Chris Zhong <zyw@rock-chips.com>
  6. * Nickey Yang <nickey.yang@rock-chips.com>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/math64.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <linux/of_device.h>
  14. #include <linux/phy/phy.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regmap.h>
  17. #include <video/mipi_display.h>
  18. #include <drm/bridge/dw_mipi_dsi.h>
  19. #include <drm/drm_mipi_dsi.h>
  20. #include <drm/drm_of.h>
  21. #include <drm/drm_simple_kms_helper.h>
  22. #include "rockchip_drm_drv.h"
  23. #include "rockchip_drm_vop.h"
  24. #define DSI_PHY_RSTZ 0xa0
  25. #define PHY_DISFORCEPLL 0
  26. #define PHY_ENFORCEPLL BIT(3)
  27. #define PHY_DISABLECLK 0
  28. #define PHY_ENABLECLK BIT(2)
  29. #define PHY_RSTZ 0
  30. #define PHY_UNRSTZ BIT(1)
  31. #define PHY_SHUTDOWNZ 0
  32. #define PHY_UNSHUTDOWNZ BIT(0)
  33. #define DSI_PHY_IF_CFG 0xa4
  34. #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
  35. #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
  36. #define DSI_PHY_STATUS 0xb0
  37. #define LOCK BIT(0)
  38. #define STOP_STATE_CLK_LANE BIT(2)
  39. #define DSI_PHY_TST_CTRL0 0xb4
  40. #define PHY_TESTCLK BIT(1)
  41. #define PHY_UNTESTCLK 0
  42. #define PHY_TESTCLR BIT(0)
  43. #define PHY_UNTESTCLR 0
  44. #define DSI_PHY_TST_CTRL1 0xb8
  45. #define PHY_TESTEN BIT(16)
  46. #define PHY_UNTESTEN 0
  47. #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
  48. #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
  49. #define DSI_INT_ST0 0xbc
  50. #define DSI_INT_ST1 0xc0
  51. #define DSI_INT_MSK0 0xc4
  52. #define DSI_INT_MSK1 0xc8
  53. #define PHY_STATUS_TIMEOUT_US 10000
  54. #define CMD_PKT_STATUS_TIMEOUT_US 20000
  55. #define BYPASS_VCO_RANGE BIT(7)
  56. #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3)
  57. #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1)
  58. #define VCO_IN_CAP_CON_LOW (0x1 << 1)
  59. #define VCO_IN_CAP_CON_HIGH (0x2 << 1)
  60. #define REF_BIAS_CUR_SEL BIT(0)
  61. #define CP_CURRENT_3UA 0x1
  62. #define CP_CURRENT_4_5UA 0x2
  63. #define CP_CURRENT_7_5UA 0x6
  64. #define CP_CURRENT_6UA 0x9
  65. #define CP_CURRENT_12UA 0xb
  66. #define CP_CURRENT_SEL(val) ((val) & 0xf)
  67. #define CP_PROGRAM_EN BIT(7)
  68. #define LPF_RESISTORS_15_5KOHM 0x1
  69. #define LPF_RESISTORS_13KOHM 0x2
  70. #define LPF_RESISTORS_11_5KOHM 0x4
  71. #define LPF_RESISTORS_10_5KOHM 0x8
  72. #define LPF_RESISTORS_8KOHM 0x10
  73. #define LPF_PROGRAM_EN BIT(6)
  74. #define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
  75. #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
  76. #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
  77. #define LOW_PROGRAM_EN 0
  78. #define HIGH_PROGRAM_EN BIT(7)
  79. #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
  80. #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
  81. #define PLL_LOOP_DIV_EN BIT(5)
  82. #define PLL_INPUT_DIV_EN BIT(4)
  83. #define POWER_CONTROL BIT(6)
  84. #define INTERNAL_REG_CURRENT BIT(3)
  85. #define BIAS_BLOCK_ON BIT(2)
  86. #define BANDGAP_ON BIT(0)
  87. #define TER_RESISTOR_HIGH BIT(7)
  88. #define TER_RESISTOR_LOW 0
  89. #define LEVEL_SHIFTERS_ON BIT(6)
  90. #define TER_CAL_DONE BIT(5)
  91. #define SETRD_MAX (0x7 << 2)
  92. #define POWER_MANAGE BIT(1)
  93. #define TER_RESISTORS_ON BIT(0)
  94. #define BIASEXTR_SEL(val) ((val) & 0x7)
  95. #define BANDGAP_SEL(val) ((val) & 0x7)
  96. #define TLP_PROGRAM_EN BIT(7)
  97. #define THS_PRE_PROGRAM_EN BIT(7)
  98. #define THS_ZERO_PROGRAM_EN BIT(6)
  99. #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10
  100. #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11
  101. #define PLL_LPF_AND_CP_CONTROL 0x12
  102. #define PLL_INPUT_DIVIDER_RATIO 0x17
  103. #define PLL_LOOP_DIVIDER_RATIO 0x18
  104. #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19
  105. #define BANDGAP_AND_BIAS_CONTROL 0x20
  106. #define TERMINATION_RESISTER_CONTROL 0x21
  107. #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22
  108. #define HS_RX_CONTROL_OF_LANE_0 0x44
  109. #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60
  110. #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61
  111. #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62
  112. #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63
  113. #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64
  114. #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65
  115. #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70
  116. #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71
  117. #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
  118. #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
  119. #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74
  120. #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
  121. #define DW_MIPI_NEEDS_GRF_CLK BIT(1)
  122. #define PX30_GRF_PD_VO_CON1 0x0438
  123. #define PX30_DSI_FORCETXSTOPMODE (0xf << 7)
  124. #define PX30_DSI_FORCERXMODE BIT(6)
  125. #define PX30_DSI_TURNDISABLE BIT(5)
  126. #define PX30_DSI_LCDC_SEL BIT(0)
  127. #define RK3288_GRF_SOC_CON6 0x025c
  128. #define RK3288_DSI0_LCDC_SEL BIT(6)
  129. #define RK3288_DSI1_LCDC_SEL BIT(9)
  130. #define RK3399_GRF_SOC_CON20 0x6250
  131. #define RK3399_DSI0_LCDC_SEL BIT(0)
  132. #define RK3399_DSI1_LCDC_SEL BIT(4)
  133. #define RK3399_GRF_SOC_CON22 0x6258
  134. #define RK3399_DSI0_TURNREQUEST (0xf << 12)
  135. #define RK3399_DSI0_TURNDISABLE (0xf << 8)
  136. #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4)
  137. #define RK3399_DSI0_FORCERXMODE (0xf << 0)
  138. #define RK3399_GRF_SOC_CON23 0x625c
  139. #define RK3399_DSI1_TURNDISABLE (0xf << 12)
  140. #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8)
  141. #define RK3399_DSI1_FORCERXMODE (0xf << 4)
  142. #define RK3399_DSI1_ENABLE (0xf << 0)
  143. #define RK3399_GRF_SOC_CON24 0x6260
  144. #define RK3399_TXRX_MASTERSLAVEZ BIT(7)
  145. #define RK3399_TXRX_ENABLECLK BIT(6)
  146. #define RK3399_TXRX_BASEDIR BIT(5)
  147. #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
  148. #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
  149. enum {
  150. BANDGAP_97_07,
  151. BANDGAP_98_05,
  152. BANDGAP_99_02,
  153. BANDGAP_100_00,
  154. BANDGAP_93_17,
  155. BANDGAP_94_15,
  156. BANDGAP_95_12,
  157. BANDGAP_96_10,
  158. };
  159. enum {
  160. BIASEXTR_87_1,
  161. BIASEXTR_91_5,
  162. BIASEXTR_95_9,
  163. BIASEXTR_100,
  164. BIASEXTR_105_94,
  165. BIASEXTR_111_88,
  166. BIASEXTR_118_8,
  167. BIASEXTR_127_7,
  168. };
  169. struct rockchip_dw_dsi_chip_data {
  170. u32 reg;
  171. u32 lcdsel_grf_reg;
  172. u32 lcdsel_big;
  173. u32 lcdsel_lit;
  174. u32 enable_grf_reg;
  175. u32 enable;
  176. u32 lanecfg1_grf_reg;
  177. u32 lanecfg1;
  178. u32 lanecfg2_grf_reg;
  179. u32 lanecfg2;
  180. unsigned int flags;
  181. unsigned int max_data_lanes;
  182. };
  183. struct dw_mipi_dsi_rockchip {
  184. struct device *dev;
  185. struct drm_encoder encoder;
  186. void __iomem *base;
  187. struct regmap *grf_regmap;
  188. struct clk *pllref_clk;
  189. struct clk *grf_clk;
  190. struct clk *phy_cfg_clk;
  191. /* dual-channel */
  192. bool is_slave;
  193. struct dw_mipi_dsi_rockchip *slave;
  194. /* optional external dphy */
  195. struct phy *phy;
  196. union phy_configure_opts phy_opts;
  197. unsigned int lane_mbps; /* per lane */
  198. u16 input_div;
  199. u16 feedback_div;
  200. u32 format;
  201. struct dw_mipi_dsi *dmd;
  202. const struct rockchip_dw_dsi_chip_data *cdata;
  203. struct dw_mipi_dsi_plat_data pdata;
  204. bool dsi_bound;
  205. };
  206. struct dphy_pll_parameter_map {
  207. unsigned int max_mbps;
  208. u8 hsfreqrange;
  209. u8 icpctrl;
  210. u8 lpfctrl;
  211. };
  212. /* The table is based on 27MHz DPHY pll reference clock. */
  213. static const struct dphy_pll_parameter_map dppa_map[] = {
  214. { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
  215. { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
  216. { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM },
  217. { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
  218. { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
  219. { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
  220. { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
  221. { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
  222. { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM },
  223. { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
  224. { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
  225. { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM },
  226. { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
  227. { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM },
  228. { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
  229. { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
  230. { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM },
  231. { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  232. { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  233. { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
  234. { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM },
  235. { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  236. { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  237. { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  238. { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  239. { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  240. { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM },
  241. { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
  242. { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
  243. {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
  244. {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM },
  245. {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  246. {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  247. {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  248. {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  249. {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  250. {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  251. {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM },
  252. {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }
  253. };
  254. static int max_mbps_to_parameter(unsigned int max_mbps)
  255. {
  256. int i;
  257. for (i = 0; i < ARRAY_SIZE(dppa_map); i++)
  258. if (dppa_map[i].max_mbps >= max_mbps)
  259. return i;
  260. return -EINVAL;
  261. }
  262. static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
  263. {
  264. writel(val, dsi->base + reg);
  265. }
  266. static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg)
  267. {
  268. return readl(dsi->base + reg);
  269. }
  270. static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask)
  271. {
  272. dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
  273. }
  274. static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg,
  275. u32 mask, u32 val)
  276. {
  277. dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
  278. }
  279. static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
  280. u8 test_code,
  281. u8 test_data)
  282. {
  283. /*
  284. * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
  285. * is latched internally as the current test code. Test data is
  286. * programmed internally by rising edge on TESTCLK.
  287. */
  288. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
  289. dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
  290. PHY_TESTDIN(test_code));
  291. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
  292. dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
  293. PHY_TESTDIN(test_data));
  294. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
  295. }
  296. /**
  297. * ns2bc - Nanoseconds to byte clock cycles
  298. */
  299. static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
  300. {
  301. return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
  302. }
  303. /**
  304. * ns2ui - Nanoseconds to UI time periods
  305. */
  306. static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
  307. {
  308. return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
  309. }
  310. static int dw_mipi_dsi_phy_init(void *priv_data)
  311. {
  312. struct dw_mipi_dsi_rockchip *dsi = priv_data;
  313. int ret, i, vco;
  314. if (dsi->phy)
  315. return 0;
  316. /*
  317. * Get vco from frequency(lane_mbps)
  318. * vco frequency table
  319. * 000 - between 80 and 200 MHz
  320. * 001 - between 200 and 300 MHz
  321. * 010 - between 300 and 500 MHz
  322. * 011 - between 500 and 700 MHz
  323. * 100 - between 700 and 900 MHz
  324. * 101 - between 900 and 1100 MHz
  325. * 110 - between 1100 and 1300 MHz
  326. * 111 - between 1300 and 1500 MHz
  327. */
  328. vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
  329. i = max_mbps_to_parameter(dsi->lane_mbps);
  330. if (i < 0) {
  331. DRM_DEV_ERROR(dsi->dev,
  332. "failed to get parameter for %dmbps clock\n",
  333. dsi->lane_mbps);
  334. return i;
  335. }
  336. ret = clk_prepare_enable(dsi->phy_cfg_clk);
  337. if (ret) {
  338. DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
  339. return ret;
  340. }
  341. dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
  342. BYPASS_VCO_RANGE |
  343. VCO_RANGE_CON_SEL(vco) |
  344. VCO_IN_CAP_CON_LOW |
  345. REF_BIAS_CUR_SEL);
  346. dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
  347. CP_CURRENT_SEL(dppa_map[i].icpctrl));
  348. dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
  349. CP_PROGRAM_EN | LPF_PROGRAM_EN |
  350. LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
  351. dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
  352. HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
  353. dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
  354. INPUT_DIVIDER(dsi->input_div));
  355. dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
  356. LOOP_DIV_LOW_SEL(dsi->feedback_div) |
  357. LOW_PROGRAM_EN);
  358. /*
  359. * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately
  360. * to make the configured LSB effective according to IP simulation
  361. * and lab test results.
  362. * Only in this way can we get correct mipi phy pll frequency.
  363. */
  364. dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
  365. PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
  366. dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
  367. LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
  368. HIGH_PROGRAM_EN);
  369. dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
  370. PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN);
  371. dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
  372. LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7));
  373. dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
  374. HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10));
  375. dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
  376. POWER_CONTROL | INTERNAL_REG_CURRENT |
  377. BIAS_BLOCK_ON | BANDGAP_ON);
  378. dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
  379. TER_RESISTOR_LOW | TER_CAL_DONE |
  380. SETRD_MAX | TER_RESISTORS_ON);
  381. dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
  382. TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON |
  383. SETRD_MAX | POWER_MANAGE |
  384. TER_RESISTORS_ON);
  385. dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
  386. TLP_PROGRAM_EN | ns2bc(dsi, 500));
  387. dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
  388. THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
  389. dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
  390. THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
  391. dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
  392. THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
  393. dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
  394. BIT(5) | ns2bc(dsi, 100));
  395. dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
  396. BIT(5) | (ns2bc(dsi, 60) + 7));
  397. dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
  398. TLP_PROGRAM_EN | ns2bc(dsi, 500));
  399. dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
  400. THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
  401. dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
  402. THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
  403. dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
  404. THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
  405. dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
  406. BIT(5) | ns2bc(dsi, 100));
  407. clk_disable_unprepare(dsi->phy_cfg_clk);
  408. return ret;
  409. }
  410. static void dw_mipi_dsi_phy_power_on(void *priv_data)
  411. {
  412. struct dw_mipi_dsi_rockchip *dsi = priv_data;
  413. int ret;
  414. ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
  415. if (ret) {
  416. DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
  417. return;
  418. }
  419. phy_configure(dsi->phy, &dsi->phy_opts);
  420. phy_power_on(dsi->phy);
  421. }
  422. static void dw_mipi_dsi_phy_power_off(void *priv_data)
  423. {
  424. struct dw_mipi_dsi_rockchip *dsi = priv_data;
  425. phy_power_off(dsi->phy);
  426. }
  427. static int
  428. dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
  429. unsigned long mode_flags, u32 lanes, u32 format,
  430. unsigned int *lane_mbps)
  431. {
  432. struct dw_mipi_dsi_rockchip *dsi = priv_data;
  433. int bpp;
  434. unsigned long mpclk, tmp;
  435. unsigned int target_mbps = 1000;
  436. unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps;
  437. unsigned long best_freq = 0;
  438. unsigned long fvco_min, fvco_max, fin, fout;
  439. unsigned int min_prediv, max_prediv;
  440. unsigned int _prediv, best_prediv;
  441. unsigned long _fbdiv, best_fbdiv;
  442. unsigned long min_delta = ULONG_MAX;
  443. dsi->format = format;
  444. bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
  445. if (bpp < 0) {
  446. DRM_DEV_ERROR(dsi->dev,
  447. "failed to get bpp for pixel format %d\n",
  448. dsi->format);
  449. return bpp;
  450. }
  451. mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
  452. if (mpclk) {
  453. /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
  454. tmp = mpclk * (bpp / lanes) * 10 / 8;
  455. if (tmp < max_mbps)
  456. target_mbps = tmp;
  457. else
  458. DRM_DEV_ERROR(dsi->dev,
  459. "DPHY clock frequency is out of range\n");
  460. }
  461. /* for external phy only a the mipi_dphy_config is necessary */
  462. if (dsi->phy) {
  463. phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8,
  464. bpp, lanes,
  465. &dsi->phy_opts.mipi_dphy);
  466. dsi->lane_mbps = target_mbps;
  467. *lane_mbps = dsi->lane_mbps;
  468. return 0;
  469. }
  470. fin = clk_get_rate(dsi->pllref_clk);
  471. fout = target_mbps * USEC_PER_SEC;
  472. /* constraint: 5Mhz <= Fref / N <= 40MHz */
  473. min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC);
  474. max_prediv = fin / (5 * USEC_PER_SEC);
  475. /* constraint: 80MHz <= Fvco <= 1500Mhz */
  476. fvco_min = 80 * USEC_PER_SEC;
  477. fvco_max = 1500 * USEC_PER_SEC;
  478. for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
  479. u64 tmp;
  480. u32 delta;
  481. /* Fvco = Fref * M / N */
  482. tmp = (u64)fout * _prediv;
  483. do_div(tmp, fin);
  484. _fbdiv = tmp;
  485. /*
  486. * Due to the use of a "by 2 pre-scaler," the range of the
  487. * feedback multiplication value M is limited to even division
  488. * numbers, and m must be greater than 6, not bigger than 512.
  489. */
  490. if (_fbdiv < 6 || _fbdiv > 512)
  491. continue;
  492. _fbdiv += _fbdiv % 2;
  493. tmp = (u64)_fbdiv * fin;
  494. do_div(tmp, _prediv);
  495. if (tmp < fvco_min || tmp > fvco_max)
  496. continue;
  497. delta = abs(fout - tmp);
  498. if (delta < min_delta) {
  499. best_prediv = _prediv;
  500. best_fbdiv = _fbdiv;
  501. min_delta = delta;
  502. best_freq = tmp;
  503. }
  504. }
  505. if (best_freq) {
  506. dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
  507. *lane_mbps = dsi->lane_mbps;
  508. dsi->input_div = best_prediv;
  509. dsi->feedback_div = best_fbdiv;
  510. } else {
  511. DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
  512. return -EINVAL;
  513. }
  514. return 0;
  515. }
  516. struct hstt {
  517. unsigned int maxfreq;
  518. struct dw_mipi_dsi_dphy_timing timing;
  519. };
  520. #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \
  521. { \
  522. .maxfreq = _maxfreq, \
  523. .timing = { \
  524. .clk_lp2hs = _c_lp2hs, \
  525. .clk_hs2lp = _c_hs2lp, \
  526. .data_lp2hs = _d_lp2hs, \
  527. .data_hs2lp = _d_hs2lp, \
  528. } \
  529. }
  530. /* Table A-3 High-Speed Transition Times */
  531. struct hstt hstt_table[] = {
  532. HSTT( 90, 32, 20, 26, 13),
  533. HSTT( 100, 35, 23, 28, 14),
  534. HSTT( 110, 32, 22, 26, 13),
  535. HSTT( 130, 31, 20, 27, 13),
  536. HSTT( 140, 33, 22, 26, 14),
  537. HSTT( 150, 33, 21, 26, 14),
  538. HSTT( 170, 32, 20, 27, 13),
  539. HSTT( 180, 36, 23, 30, 15),
  540. HSTT( 200, 40, 22, 33, 15),
  541. HSTT( 220, 40, 22, 33, 15),
  542. HSTT( 240, 44, 24, 36, 16),
  543. HSTT( 250, 48, 24, 38, 17),
  544. HSTT( 270, 48, 24, 38, 17),
  545. HSTT( 300, 50, 27, 41, 18),
  546. HSTT( 330, 56, 28, 45, 18),
  547. HSTT( 360, 59, 28, 48, 19),
  548. HSTT( 400, 61, 30, 50, 20),
  549. HSTT( 450, 67, 31, 55, 21),
  550. HSTT( 500, 73, 31, 59, 22),
  551. HSTT( 550, 79, 36, 63, 24),
  552. HSTT( 600, 83, 37, 68, 25),
  553. HSTT( 650, 90, 38, 73, 27),
  554. HSTT( 700, 95, 40, 77, 28),
  555. HSTT( 750, 102, 40, 84, 28),
  556. HSTT( 800, 106, 42, 87, 30),
  557. HSTT( 850, 113, 44, 93, 31),
  558. HSTT( 900, 118, 47, 98, 32),
  559. HSTT( 950, 124, 47, 102, 34),
  560. HSTT(1000, 130, 49, 107, 35),
  561. HSTT(1050, 135, 51, 111, 37),
  562. HSTT(1100, 139, 51, 114, 38),
  563. HSTT(1150, 146, 54, 120, 40),
  564. HSTT(1200, 153, 57, 125, 41),
  565. HSTT(1250, 158, 58, 130, 42),
  566. HSTT(1300, 163, 58, 135, 44),
  567. HSTT(1350, 168, 60, 140, 45),
  568. HSTT(1400, 172, 64, 144, 47),
  569. HSTT(1450, 176, 65, 148, 48),
  570. HSTT(1500, 181, 66, 153, 50)
  571. };
  572. static int
  573. dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
  574. struct dw_mipi_dsi_dphy_timing *timing)
  575. {
  576. int i;
  577. for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
  578. if (lane_mbps < hstt_table[i].maxfreq)
  579. break;
  580. if (i == ARRAY_SIZE(hstt_table))
  581. i--;
  582. *timing = hstt_table[i].timing;
  583. return 0;
  584. }
  585. static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
  586. .init = dw_mipi_dsi_phy_init,
  587. .power_on = dw_mipi_dsi_phy_power_on,
  588. .power_off = dw_mipi_dsi_phy_power_off,
  589. .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
  590. .get_timing = dw_mipi_dsi_phy_get_timing,
  591. };
  592. static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
  593. {
  594. if (dsi->cdata->lanecfg1_grf_reg)
  595. regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
  596. dsi->cdata->lanecfg1);
  597. if (dsi->cdata->lanecfg2_grf_reg)
  598. regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
  599. dsi->cdata->lanecfg2);
  600. if (dsi->cdata->enable_grf_reg)
  601. regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
  602. dsi->cdata->enable);
  603. }
  604. static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
  605. int mux)
  606. {
  607. regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
  608. mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
  609. }
  610. static int
  611. dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
  612. struct drm_crtc_state *crtc_state,
  613. struct drm_connector_state *conn_state)
  614. {
  615. struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
  616. struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
  617. switch (dsi->format) {
  618. case MIPI_DSI_FMT_RGB888:
  619. s->output_mode = ROCKCHIP_OUT_MODE_P888;
  620. break;
  621. case MIPI_DSI_FMT_RGB666:
  622. s->output_mode = ROCKCHIP_OUT_MODE_P666;
  623. break;
  624. case MIPI_DSI_FMT_RGB565:
  625. s->output_mode = ROCKCHIP_OUT_MODE_P565;
  626. break;
  627. default:
  628. WARN_ON(1);
  629. return -EINVAL;
  630. }
  631. s->output_type = DRM_MODE_CONNECTOR_DSI;
  632. if (dsi->slave)
  633. s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL;
  634. return 0;
  635. }
  636. static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
  637. {
  638. struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
  639. int ret, mux;
  640. mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
  641. &dsi->encoder);
  642. if (mux < 0)
  643. return;
  644. /*
  645. * For the RK3399, the clk of grf must be enabled before writing grf
  646. * register. And for RK3288 or other soc, this grf_clk must be NULL,
  647. * the clk_prepare_enable return true directly.
  648. */
  649. ret = clk_prepare_enable(dsi->grf_clk);
  650. if (ret) {
  651. DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
  652. return;
  653. }
  654. dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
  655. if (dsi->slave)
  656. dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
  657. clk_disable_unprepare(dsi->grf_clk);
  658. }
  659. static const struct drm_encoder_helper_funcs
  660. dw_mipi_dsi_encoder_helper_funcs = {
  661. .atomic_check = dw_mipi_dsi_encoder_atomic_check,
  662. .enable = dw_mipi_dsi_encoder_enable,
  663. };
  664. static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
  665. struct drm_device *drm_dev)
  666. {
  667. struct drm_encoder *encoder = &dsi->encoder;
  668. int ret;
  669. encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
  670. dsi->dev->of_node);
  671. ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
  672. if (ret) {
  673. DRM_ERROR("Failed to initialize encoder with drm\n");
  674. return ret;
  675. }
  676. drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs);
  677. return 0;
  678. }
  679. static struct device
  680. *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
  681. {
  682. const struct of_device_id *match;
  683. struct device_node *node = NULL, *local;
  684. match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
  685. local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
  686. if (!local)
  687. return NULL;
  688. while ((node = of_find_compatible_node(node, NULL,
  689. match->compatible))) {
  690. struct device_node *remote;
  691. /* found ourself */
  692. if (node == dsi->dev->of_node)
  693. continue;
  694. remote = of_graph_get_remote_node(node, 1, 0);
  695. if (!remote)
  696. continue;
  697. /* same display device in port1-ep0 for both */
  698. if (remote == local) {
  699. struct dw_mipi_dsi_rockchip *dsi2;
  700. struct platform_device *pdev;
  701. pdev = of_find_device_by_node(node);
  702. /*
  703. * we have found the second, so will either return it
  704. * or return with an error. In any case won't need the
  705. * nodes anymore nor continue the loop.
  706. */
  707. of_node_put(remote);
  708. of_node_put(node);
  709. of_node_put(local);
  710. if (!pdev)
  711. return ERR_PTR(-EPROBE_DEFER);
  712. dsi2 = platform_get_drvdata(pdev);
  713. if (!dsi2) {
  714. platform_device_put(pdev);
  715. return ERR_PTR(-EPROBE_DEFER);
  716. }
  717. return &pdev->dev;
  718. }
  719. of_node_put(remote);
  720. }
  721. of_node_put(local);
  722. return NULL;
  723. }
  724. static int dw_mipi_dsi_rockchip_bind(struct device *dev,
  725. struct device *master,
  726. void *data)
  727. {
  728. struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
  729. struct drm_device *drm_dev = data;
  730. struct device *second;
  731. bool master1, master2;
  732. int ret;
  733. second = dw_mipi_dsi_rockchip_find_second(dsi);
  734. if (IS_ERR(second))
  735. return PTR_ERR(second);
  736. if (second) {
  737. master1 = of_property_read_bool(dsi->dev->of_node,
  738. "clock-master");
  739. master2 = of_property_read_bool(second->of_node,
  740. "clock-master");
  741. if (master1 && master2) {
  742. DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
  743. return -EINVAL;
  744. }
  745. if (!master1 && !master2) {
  746. DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
  747. return -EINVAL;
  748. }
  749. /* we are the slave in dual-DSI */
  750. if (!master1) {
  751. dsi->is_slave = true;
  752. return 0;
  753. }
  754. dsi->slave = dev_get_drvdata(second);
  755. if (!dsi->slave) {
  756. DRM_DEV_ERROR(dev, "could not get slaves data\n");
  757. return -ENODEV;
  758. }
  759. dsi->slave->is_slave = true;
  760. dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
  761. put_device(second);
  762. }
  763. pm_runtime_get_sync(dsi->dev);
  764. if (dsi->slave)
  765. pm_runtime_get_sync(dsi->slave->dev);
  766. ret = clk_prepare_enable(dsi->pllref_clk);
  767. if (ret) {
  768. DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret);
  769. goto out_pm_runtime;
  770. }
  771. /*
  772. * With the GRF clock running, write lane and dual-mode configurations
  773. * that won't change immediately. If we waited until enable() to do
  774. * this, things like panel preparation would not be able to send
  775. * commands over DSI.
  776. */
  777. ret = clk_prepare_enable(dsi->grf_clk);
  778. if (ret) {
  779. DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
  780. goto out_pll_clk;
  781. }
  782. dw_mipi_dsi_rockchip_config(dsi);
  783. if (dsi->slave)
  784. dw_mipi_dsi_rockchip_config(dsi->slave);
  785. clk_disable_unprepare(dsi->grf_clk);
  786. ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
  787. if (ret) {
  788. DRM_DEV_ERROR(dev, "Failed to create drm encoder\n");
  789. goto out_pll_clk;
  790. }
  791. ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder);
  792. if (ret) {
  793. DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
  794. goto out_pll_clk;
  795. }
  796. dsi->dsi_bound = true;
  797. return 0;
  798. out_pll_clk:
  799. clk_disable_unprepare(dsi->pllref_clk);
  800. out_pm_runtime:
  801. pm_runtime_put(dsi->dev);
  802. if (dsi->slave)
  803. pm_runtime_put(dsi->slave->dev);
  804. return ret;
  805. }
  806. static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
  807. struct device *master,
  808. void *data)
  809. {
  810. struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
  811. if (dsi->is_slave)
  812. return;
  813. dsi->dsi_bound = false;
  814. dw_mipi_dsi_unbind(dsi->dmd);
  815. clk_disable_unprepare(dsi->pllref_clk);
  816. pm_runtime_put(dsi->dev);
  817. if (dsi->slave)
  818. pm_runtime_put(dsi->slave->dev);
  819. }
  820. static const struct component_ops dw_mipi_dsi_rockchip_ops = {
  821. .bind = dw_mipi_dsi_rockchip_bind,
  822. .unbind = dw_mipi_dsi_rockchip_unbind,
  823. };
  824. static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
  825. struct mipi_dsi_device *device)
  826. {
  827. struct dw_mipi_dsi_rockchip *dsi = priv_data;
  828. struct device *second;
  829. int ret;
  830. ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
  831. if (ret) {
  832. DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
  833. ret);
  834. return ret;
  835. }
  836. second = dw_mipi_dsi_rockchip_find_second(dsi);
  837. if (IS_ERR(second))
  838. return PTR_ERR(second);
  839. if (second) {
  840. ret = component_add(second, &dw_mipi_dsi_rockchip_ops);
  841. if (ret) {
  842. DRM_DEV_ERROR(second,
  843. "Failed to register component: %d\n",
  844. ret);
  845. return ret;
  846. }
  847. }
  848. return 0;
  849. }
  850. static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
  851. struct mipi_dsi_device *device)
  852. {
  853. struct dw_mipi_dsi_rockchip *dsi = priv_data;
  854. struct device *second;
  855. second = dw_mipi_dsi_rockchip_find_second(dsi);
  856. if (second && !IS_ERR(second))
  857. component_del(second, &dw_mipi_dsi_rockchip_ops);
  858. component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
  859. return 0;
  860. }
  861. static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
  862. .attach = dw_mipi_dsi_rockchip_host_attach,
  863. .detach = dw_mipi_dsi_rockchip_host_detach,
  864. };
  865. static int __maybe_unused dw_mipi_dsi_rockchip_resume(struct device *dev)
  866. {
  867. struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
  868. int ret;
  869. /*
  870. * Re-configure DSI state, if we were previously initialized. We need
  871. * to do this before rockchip_drm_drv tries to re-enable() any panels.
  872. */
  873. if (dsi->dsi_bound) {
  874. ret = clk_prepare_enable(dsi->grf_clk);
  875. if (ret) {
  876. DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
  877. return ret;
  878. }
  879. dw_mipi_dsi_rockchip_config(dsi);
  880. if (dsi->slave)
  881. dw_mipi_dsi_rockchip_config(dsi->slave);
  882. clk_disable_unprepare(dsi->grf_clk);
  883. }
  884. return 0;
  885. }
  886. static const struct dev_pm_ops dw_mipi_dsi_rockchip_pm_ops = {
  887. SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, dw_mipi_dsi_rockchip_resume)
  888. };
  889. static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
  890. {
  891. struct device *dev = &pdev->dev;
  892. struct device_node *np = dev->of_node;
  893. struct dw_mipi_dsi_rockchip *dsi;
  894. struct resource *res;
  895. const struct rockchip_dw_dsi_chip_data *cdata =
  896. of_device_get_match_data(dev);
  897. int ret, i;
  898. dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
  899. if (!dsi)
  900. return -ENOMEM;
  901. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  902. dsi->base = devm_ioremap_resource(dev, res);
  903. if (IS_ERR(dsi->base)) {
  904. DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
  905. return PTR_ERR(dsi->base);
  906. }
  907. i = 0;
  908. while (cdata[i].reg) {
  909. if (cdata[i].reg == res->start) {
  910. dsi->cdata = &cdata[i];
  911. break;
  912. }
  913. i++;
  914. }
  915. if (!dsi->cdata) {
  916. DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
  917. return -EINVAL;
  918. }
  919. /* try to get a possible external dphy */
  920. dsi->phy = devm_phy_optional_get(dev, "dphy");
  921. if (IS_ERR(dsi->phy)) {
  922. ret = PTR_ERR(dsi->phy);
  923. DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret);
  924. return ret;
  925. }
  926. dsi->pllref_clk = devm_clk_get(dev, "ref");
  927. if (IS_ERR(dsi->pllref_clk)) {
  928. if (dsi->phy) {
  929. /*
  930. * if external phy is present, pll will be
  931. * generated there.
  932. */
  933. dsi->pllref_clk = NULL;
  934. } else {
  935. ret = PTR_ERR(dsi->pllref_clk);
  936. DRM_DEV_ERROR(dev,
  937. "Unable to get pll reference clock: %d\n",
  938. ret);
  939. return ret;
  940. }
  941. }
  942. if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
  943. dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
  944. if (IS_ERR(dsi->phy_cfg_clk)) {
  945. ret = PTR_ERR(dsi->phy_cfg_clk);
  946. DRM_DEV_ERROR(dev,
  947. "Unable to get phy_cfg_clk: %d\n", ret);
  948. return ret;
  949. }
  950. }
  951. if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
  952. dsi->grf_clk = devm_clk_get(dev, "grf");
  953. if (IS_ERR(dsi->grf_clk)) {
  954. ret = PTR_ERR(dsi->grf_clk);
  955. DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret);
  956. return ret;
  957. }
  958. }
  959. dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  960. if (IS_ERR(dsi->grf_regmap)) {
  961. DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n");
  962. return PTR_ERR(dsi->grf_regmap);
  963. }
  964. dsi->dev = dev;
  965. dsi->pdata.base = dsi->base;
  966. dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
  967. dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
  968. dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
  969. dsi->pdata.priv_data = dsi;
  970. platform_set_drvdata(pdev, dsi);
  971. dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
  972. if (IS_ERR(dsi->dmd)) {
  973. ret = PTR_ERR(dsi->dmd);
  974. if (ret != -EPROBE_DEFER)
  975. DRM_DEV_ERROR(dev,
  976. "Failed to probe dw_mipi_dsi: %d\n", ret);
  977. return ret;
  978. }
  979. return 0;
  980. }
  981. static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
  982. {
  983. struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
  984. dw_mipi_dsi_remove(dsi->dmd);
  985. return 0;
  986. }
  987. static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = {
  988. {
  989. .reg = 0xff450000,
  990. .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1,
  991. .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
  992. .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
  993. PX30_DSI_LCDC_SEL),
  994. .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1,
  995. .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
  996. PX30_DSI_FORCERXMODE |
  997. PX30_DSI_FORCETXSTOPMODE),
  998. .max_data_lanes = 4,
  999. },
  1000. { /* sentinel */ }
  1001. };
  1002. static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = {
  1003. {
  1004. .reg = 0xff960000,
  1005. .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
  1006. .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
  1007. .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
  1008. .max_data_lanes = 4,
  1009. },
  1010. {
  1011. .reg = 0xff964000,
  1012. .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
  1013. .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
  1014. .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
  1015. .max_data_lanes = 4,
  1016. },
  1017. { /* sentinel */ }
  1018. };
  1019. static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = {
  1020. {
  1021. .reg = 0xff960000,
  1022. .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
  1023. .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
  1024. .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
  1025. RK3399_DSI0_LCDC_SEL),
  1026. .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22,
  1027. .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST |
  1028. RK3399_DSI0_TURNDISABLE |
  1029. RK3399_DSI0_FORCETXSTOPMODE |
  1030. RK3399_DSI0_FORCERXMODE),
  1031. .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
  1032. .max_data_lanes = 4,
  1033. },
  1034. {
  1035. .reg = 0xff968000,
  1036. .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
  1037. .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL),
  1038. .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL,
  1039. RK3399_DSI1_LCDC_SEL),
  1040. .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23,
  1041. .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE |
  1042. RK3399_DSI1_FORCETXSTOPMODE |
  1043. RK3399_DSI1_FORCERXMODE |
  1044. RK3399_DSI1_ENABLE),
  1045. .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24,
  1046. .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ |
  1047. RK3399_TXRX_ENABLECLK,
  1048. RK3399_TXRX_MASTERSLAVEZ |
  1049. RK3399_TXRX_ENABLECLK |
  1050. RK3399_TXRX_BASEDIR),
  1051. .enable_grf_reg = RK3399_GRF_SOC_CON23,
  1052. .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE),
  1053. .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK,
  1054. .max_data_lanes = 4,
  1055. },
  1056. { /* sentinel */ }
  1057. };
  1058. static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = {
  1059. {
  1060. .compatible = "rockchip,px30-mipi-dsi",
  1061. .data = &px30_chip_data,
  1062. }, {
  1063. .compatible = "rockchip,rk3288-mipi-dsi",
  1064. .data = &rk3288_chip_data,
  1065. }, {
  1066. .compatible = "rockchip,rk3399-mipi-dsi",
  1067. .data = &rk3399_chip_data,
  1068. },
  1069. { /* sentinel */ }
  1070. };
  1071. MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids);
  1072. struct platform_driver dw_mipi_dsi_rockchip_driver = {
  1073. .probe = dw_mipi_dsi_rockchip_probe,
  1074. .remove = dw_mipi_dsi_rockchip_remove,
  1075. .driver = {
  1076. .of_match_table = dw_mipi_dsi_rockchip_dt_ids,
  1077. .pm = &dw_mipi_dsi_rockchip_pm_ops,
  1078. .name = "dw-mipi-dsi-rockchip",
  1079. },
  1080. };