analogix_dp-rockchip.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Rockchip SoC DP (Display Port) interface driver.
  4. *
  5. * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
  6. * Author: Andy Yan <andy.yan@rock-chips.com>
  7. * Yakir Yang <ykk@rock-chips.com>
  8. * Jeff Chen <jeff.chen@rock-chips.com>
  9. */
  10. #include <linux/component.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_graph.h>
  14. #include <linux/regmap.h>
  15. #include <linux/reset.h>
  16. #include <linux/clk.h>
  17. #include <video/of_videomode.h>
  18. #include <video/videomode.h>
  19. #include <drm/drm_atomic.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/bridge/analogix_dp.h>
  22. #include <drm/drm_dp_helper.h>
  23. #include <drm/drm_of.h>
  24. #include <drm/drm_panel.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_simple_kms_helper.h>
  27. #include "rockchip_drm_drv.h"
  28. #include "rockchip_drm_vop.h"
  29. #define RK3288_GRF_SOC_CON6 0x25c
  30. #define RK3288_EDP_LCDC_SEL BIT(5)
  31. #define RK3399_GRF_SOC_CON20 0x6250
  32. #define RK3399_EDP_LCDC_SEL BIT(5)
  33. #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
  34. #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
  35. #define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
  36. /**
  37. * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
  38. * @lcdsel_grf_reg: grf register offset of lcdc select
  39. * @lcdsel_big: reg value of selecting vop big for eDP
  40. * @lcdsel_lit: reg value of selecting vop little for eDP
  41. * @chip_type: specific chip type
  42. */
  43. struct rockchip_dp_chip_data {
  44. u32 lcdsel_grf_reg;
  45. u32 lcdsel_big;
  46. u32 lcdsel_lit;
  47. u32 chip_type;
  48. };
  49. struct rockchip_dp_device {
  50. struct drm_device *drm_dev;
  51. struct device *dev;
  52. struct drm_encoder encoder;
  53. struct drm_display_mode mode;
  54. struct clk *pclk;
  55. struct clk *grfclk;
  56. struct regmap *grf;
  57. struct reset_control *rst;
  58. const struct rockchip_dp_chip_data *data;
  59. struct analogix_dp_device *adp;
  60. struct analogix_dp_plat_data plat_data;
  61. };
  62. static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
  63. {
  64. reset_control_assert(dp->rst);
  65. usleep_range(10, 20);
  66. reset_control_deassert(dp->rst);
  67. return 0;
  68. }
  69. static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
  70. {
  71. struct rockchip_dp_device *dp = to_dp(plat_data);
  72. int ret;
  73. ret = clk_prepare_enable(dp->pclk);
  74. if (ret < 0) {
  75. DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
  76. return ret;
  77. }
  78. ret = rockchip_dp_pre_init(dp);
  79. if (ret < 0) {
  80. DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
  81. clk_disable_unprepare(dp->pclk);
  82. return ret;
  83. }
  84. return ret;
  85. }
  86. static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
  87. {
  88. struct rockchip_dp_device *dp = to_dp(plat_data);
  89. clk_disable_unprepare(dp->pclk);
  90. return 0;
  91. }
  92. static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
  93. struct drm_connector *connector)
  94. {
  95. struct drm_display_info *di = &connector->display_info;
  96. /* VOP couldn't output YUV video format for eDP rightly */
  97. u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;
  98. if ((di->color_formats & mask)) {
  99. DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
  100. di->color_formats &= ~mask;
  101. di->color_formats |= DRM_COLOR_FORMAT_RGB444;
  102. di->bpc = 8;
  103. }
  104. return 0;
  105. }
  106. static bool
  107. rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
  108. const struct drm_display_mode *mode,
  109. struct drm_display_mode *adjusted_mode)
  110. {
  111. /* do nothing */
  112. return true;
  113. }
  114. static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
  115. struct drm_display_mode *mode,
  116. struct drm_display_mode *adjusted)
  117. {
  118. /* do nothing */
  119. }
  120. static
  121. struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
  122. struct drm_atomic_state *state)
  123. {
  124. struct drm_connector *connector;
  125. struct drm_connector_state *conn_state;
  126. connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
  127. if (!connector)
  128. return NULL;
  129. conn_state = drm_atomic_get_new_connector_state(state, connector);
  130. if (!conn_state)
  131. return NULL;
  132. return conn_state->crtc;
  133. }
  134. static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
  135. struct drm_atomic_state *state)
  136. {
  137. struct rockchip_dp_device *dp = to_dp(encoder);
  138. struct drm_crtc *crtc;
  139. struct drm_crtc_state *old_crtc_state;
  140. int ret;
  141. u32 val;
  142. crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
  143. if (!crtc)
  144. return;
  145. old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
  146. /* Coming back from self refresh, nothing to do */
  147. if (old_crtc_state && old_crtc_state->self_refresh_active)
  148. return;
  149. ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
  150. if (ret < 0)
  151. return;
  152. if (ret)
  153. val = dp->data->lcdsel_lit;
  154. else
  155. val = dp->data->lcdsel_big;
  156. DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
  157. ret = clk_prepare_enable(dp->grfclk);
  158. if (ret < 0) {
  159. DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
  160. return;
  161. }
  162. ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
  163. if (ret != 0)
  164. DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
  165. clk_disable_unprepare(dp->grfclk);
  166. }
  167. static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
  168. struct drm_atomic_state *state)
  169. {
  170. struct rockchip_dp_device *dp = to_dp(encoder);
  171. struct drm_crtc *crtc;
  172. struct drm_crtc_state *new_crtc_state = NULL;
  173. int ret;
  174. crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
  175. /* No crtc means we're doing a full shutdown */
  176. if (!crtc)
  177. return;
  178. new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
  179. /* If we're not entering self-refresh, no need to wait for vact */
  180. if (!new_crtc_state || !new_crtc_state->self_refresh_active)
  181. return;
  182. ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
  183. if (ret)
  184. DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
  185. }
  186. static int
  187. rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
  188. struct drm_crtc_state *crtc_state,
  189. struct drm_connector_state *conn_state)
  190. {
  191. struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
  192. struct drm_display_info *di = &conn_state->connector->display_info;
  193. /*
  194. * The hardware IC designed that VOP must output the RGB10 video
  195. * format to eDP controller, and if eDP panel only support RGB8,
  196. * then eDP controller should cut down the video data, not via VOP
  197. * controller, that's why we need to hardcode the VOP output mode
  198. * to RGA10 here.
  199. */
  200. s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
  201. s->output_type = DRM_MODE_CONNECTOR_eDP;
  202. s->output_bpc = di->bpc;
  203. return 0;
  204. }
  205. static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
  206. .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
  207. .mode_set = rockchip_dp_drm_encoder_mode_set,
  208. .atomic_enable = rockchip_dp_drm_encoder_enable,
  209. .atomic_disable = rockchip_dp_drm_encoder_disable,
  210. .atomic_check = rockchip_dp_drm_encoder_atomic_check,
  211. };
  212. static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
  213. {
  214. struct device *dev = dp->dev;
  215. struct device_node *np = dev->of_node;
  216. dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  217. if (IS_ERR(dp->grf)) {
  218. DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
  219. return PTR_ERR(dp->grf);
  220. }
  221. dp->grfclk = devm_clk_get(dev, "grf");
  222. if (PTR_ERR(dp->grfclk) == -ENOENT) {
  223. dp->grfclk = NULL;
  224. } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
  225. return -EPROBE_DEFER;
  226. } else if (IS_ERR(dp->grfclk)) {
  227. DRM_DEV_ERROR(dev, "failed to get grf clock\n");
  228. return PTR_ERR(dp->grfclk);
  229. }
  230. dp->pclk = devm_clk_get(dev, "pclk");
  231. if (IS_ERR(dp->pclk)) {
  232. DRM_DEV_ERROR(dev, "failed to get pclk property\n");
  233. return PTR_ERR(dp->pclk);
  234. }
  235. dp->rst = devm_reset_control_get(dev, "dp");
  236. if (IS_ERR(dp->rst)) {
  237. DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
  238. return PTR_ERR(dp->rst);
  239. }
  240. return 0;
  241. }
  242. static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
  243. {
  244. struct drm_encoder *encoder = &dp->encoder;
  245. struct drm_device *drm_dev = dp->drm_dev;
  246. struct device *dev = dp->dev;
  247. int ret;
  248. encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
  249. dev->of_node);
  250. DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
  251. ret = drm_simple_encoder_init(drm_dev, encoder,
  252. DRM_MODE_ENCODER_TMDS);
  253. if (ret) {
  254. DRM_ERROR("failed to initialize encoder with drm\n");
  255. return ret;
  256. }
  257. drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
  258. return 0;
  259. }
  260. static int rockchip_dp_bind(struct device *dev, struct device *master,
  261. void *data)
  262. {
  263. struct rockchip_dp_device *dp = dev_get_drvdata(dev);
  264. struct drm_device *drm_dev = data;
  265. int ret;
  266. dp->drm_dev = drm_dev;
  267. ret = rockchip_dp_drm_create_encoder(dp);
  268. if (ret) {
  269. DRM_ERROR("failed to create drm encoder\n");
  270. return ret;
  271. }
  272. dp->plat_data.encoder = &dp->encoder;
  273. ret = analogix_dp_bind(dp->adp, drm_dev);
  274. if (ret)
  275. goto err_cleanup_encoder;
  276. return 0;
  277. err_cleanup_encoder:
  278. dp->encoder.funcs->destroy(&dp->encoder);
  279. return ret;
  280. }
  281. static void rockchip_dp_unbind(struct device *dev, struct device *master,
  282. void *data)
  283. {
  284. struct rockchip_dp_device *dp = dev_get_drvdata(dev);
  285. analogix_dp_unbind(dp->adp);
  286. dp->encoder.funcs->destroy(&dp->encoder);
  287. }
  288. static const struct component_ops rockchip_dp_component_ops = {
  289. .bind = rockchip_dp_bind,
  290. .unbind = rockchip_dp_unbind,
  291. };
  292. static int rockchip_dp_probe(struct platform_device *pdev)
  293. {
  294. struct device *dev = &pdev->dev;
  295. const struct rockchip_dp_chip_data *dp_data;
  296. struct drm_panel *panel = NULL;
  297. struct rockchip_dp_device *dp;
  298. int ret;
  299. dp_data = of_device_get_match_data(dev);
  300. if (!dp_data)
  301. return -ENODEV;
  302. ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
  303. if (ret < 0)
  304. return ret;
  305. dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
  306. if (!dp)
  307. return -ENOMEM;
  308. dp->dev = dev;
  309. dp->adp = ERR_PTR(-ENODEV);
  310. dp->data = dp_data;
  311. dp->plat_data.panel = panel;
  312. dp->plat_data.dev_type = dp->data->chip_type;
  313. dp->plat_data.power_on_start = rockchip_dp_poweron_start;
  314. dp->plat_data.power_off = rockchip_dp_powerdown;
  315. dp->plat_data.get_modes = rockchip_dp_get_modes;
  316. ret = rockchip_dp_of_probe(dp);
  317. if (ret < 0)
  318. return ret;
  319. platform_set_drvdata(pdev, dp);
  320. dp->adp = analogix_dp_probe(dev, &dp->plat_data);
  321. if (IS_ERR(dp->adp))
  322. return PTR_ERR(dp->adp);
  323. return component_add(dev, &rockchip_dp_component_ops);
  324. }
  325. static int rockchip_dp_remove(struct platform_device *pdev)
  326. {
  327. struct rockchip_dp_device *dp = platform_get_drvdata(pdev);
  328. component_del(&pdev->dev, &rockchip_dp_component_ops);
  329. analogix_dp_remove(dp->adp);
  330. return 0;
  331. }
  332. #ifdef CONFIG_PM_SLEEP
  333. static int rockchip_dp_suspend(struct device *dev)
  334. {
  335. struct rockchip_dp_device *dp = dev_get_drvdata(dev);
  336. if (IS_ERR(dp->adp))
  337. return 0;
  338. return analogix_dp_suspend(dp->adp);
  339. }
  340. static int rockchip_dp_resume(struct device *dev)
  341. {
  342. struct rockchip_dp_device *dp = dev_get_drvdata(dev);
  343. if (IS_ERR(dp->adp))
  344. return 0;
  345. return analogix_dp_resume(dp->adp);
  346. }
  347. #endif
  348. static const struct dev_pm_ops rockchip_dp_pm_ops = {
  349. #ifdef CONFIG_PM_SLEEP
  350. .suspend_late = rockchip_dp_suspend,
  351. .resume_early = rockchip_dp_resume,
  352. #endif
  353. };
  354. static const struct rockchip_dp_chip_data rk3399_edp = {
  355. .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
  356. .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
  357. .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
  358. .chip_type = RK3399_EDP,
  359. };
  360. static const struct rockchip_dp_chip_data rk3288_dp = {
  361. .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
  362. .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
  363. .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
  364. .chip_type = RK3288_DP,
  365. };
  366. static const struct of_device_id rockchip_dp_dt_ids[] = {
  367. {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
  368. {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
  369. {}
  370. };
  371. MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
  372. struct platform_driver rockchip_dp_driver = {
  373. .probe = rockchip_dp_probe,
  374. .remove = rockchip_dp_remove,
  375. .driver = {
  376. .name = "rockchip-dp",
  377. .pm = &rockchip_dp_pm_ops,
  378. .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
  379. },
  380. };