panel-tpo-tpg110.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Panel driver for the TPO TPG110 400CH LTPS TFT LCD Single Chip
  4. * Digital Driver.
  5. *
  6. * This chip drives a TFT LCD, so it does not know what kind of
  7. * display is actually connected to it, so the width and height of that
  8. * display needs to be supplied from the machine configuration.
  9. *
  10. * Author:
  11. * Linus Walleij <linus.walleij@linaro.org>
  12. */
  13. #include <drm/drm_modes.h>
  14. #include <drm/drm_panel.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <linux/gpio/consumer.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spi/spi.h>
  24. #define TPG110_TEST 0x00
  25. #define TPG110_CHIPID 0x01
  26. #define TPG110_CTRL1 0x02
  27. #define TPG110_RES_MASK GENMASK(2, 0)
  28. #define TPG110_RES_800X480 0x07
  29. #define TPG110_RES_640X480 0x06
  30. #define TPG110_RES_480X272 0x05
  31. #define TPG110_RES_480X640 0x04
  32. #define TPG110_RES_480X272_D 0x01 /* Dual scan: outputs 800x480 */
  33. #define TPG110_RES_400X240_D 0x00 /* Dual scan: outputs 800x480 */
  34. #define TPG110_CTRL2 0x03
  35. #define TPG110_CTRL2_PM BIT(0)
  36. #define TPG110_CTRL2_RES_PM_CTRL BIT(7)
  37. /**
  38. * struct tpg110_panel_mode - lookup struct for the supported modes
  39. */
  40. struct tpg110_panel_mode {
  41. /**
  42. * @name: the name of this panel
  43. */
  44. const char *name;
  45. /**
  46. * @magic: the magic value from the detection register
  47. */
  48. u32 magic;
  49. /**
  50. * @mode: the DRM display mode for this panel
  51. */
  52. struct drm_display_mode mode;
  53. /**
  54. * @bus_flags: the DRM bus flags for this panel e.g. inverted clock
  55. */
  56. u32 bus_flags;
  57. };
  58. /**
  59. * struct tpg110 - state container for the TPG110 panel
  60. */
  61. struct tpg110 {
  62. /**
  63. * @dev: the container device
  64. */
  65. struct device *dev;
  66. /**
  67. * @spi: the corresponding SPI device
  68. */
  69. struct spi_device *spi;
  70. /**
  71. * @panel: the DRM panel instance for this device
  72. */
  73. struct drm_panel panel;
  74. /**
  75. * @panel_type: the panel mode as detected
  76. */
  77. const struct tpg110_panel_mode *panel_mode;
  78. /**
  79. * @width: the width of this panel in mm
  80. */
  81. u32 width;
  82. /**
  83. * @height: the height of this panel in mm
  84. */
  85. u32 height;
  86. /**
  87. * @grestb: reset GPIO line
  88. */
  89. struct gpio_desc *grestb;
  90. };
  91. /*
  92. * TPG110 modes, these are the simple modes, the dualscan modes that
  93. * take 400x240 or 480x272 in and display as 800x480 are not listed.
  94. */
  95. static const struct tpg110_panel_mode tpg110_modes[] = {
  96. {
  97. .name = "800x480 RGB",
  98. .magic = TPG110_RES_800X480,
  99. .mode = {
  100. .clock = 33200,
  101. .hdisplay = 800,
  102. .hsync_start = 800 + 40,
  103. .hsync_end = 800 + 40 + 1,
  104. .htotal = 800 + 40 + 1 + 216,
  105. .vdisplay = 480,
  106. .vsync_start = 480 + 10,
  107. .vsync_end = 480 + 10 + 1,
  108. .vtotal = 480 + 10 + 1 + 35,
  109. },
  110. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  111. },
  112. {
  113. .name = "640x480 RGB",
  114. .magic = TPG110_RES_640X480,
  115. .mode = {
  116. .clock = 25200,
  117. .hdisplay = 640,
  118. .hsync_start = 640 + 24,
  119. .hsync_end = 640 + 24 + 1,
  120. .htotal = 640 + 24 + 1 + 136,
  121. .vdisplay = 480,
  122. .vsync_start = 480 + 18,
  123. .vsync_end = 480 + 18 + 1,
  124. .vtotal = 480 + 18 + 1 + 27,
  125. },
  126. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  127. },
  128. {
  129. .name = "480x272 RGB",
  130. .magic = TPG110_RES_480X272,
  131. .mode = {
  132. .clock = 9000,
  133. .hdisplay = 480,
  134. .hsync_start = 480 + 2,
  135. .hsync_end = 480 + 2 + 1,
  136. .htotal = 480 + 2 + 1 + 43,
  137. .vdisplay = 272,
  138. .vsync_start = 272 + 2,
  139. .vsync_end = 272 + 2 + 1,
  140. .vtotal = 272 + 2 + 1 + 12,
  141. },
  142. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  143. },
  144. {
  145. .name = "480x640 RGB",
  146. .magic = TPG110_RES_480X640,
  147. .mode = {
  148. .clock = 20500,
  149. .hdisplay = 480,
  150. .hsync_start = 480 + 2,
  151. .hsync_end = 480 + 2 + 1,
  152. .htotal = 480 + 2 + 1 + 43,
  153. .vdisplay = 640,
  154. .vsync_start = 640 + 4,
  155. .vsync_end = 640 + 4 + 1,
  156. .vtotal = 640 + 4 + 1 + 8,
  157. },
  158. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  159. },
  160. {
  161. .name = "400x240 RGB",
  162. .magic = TPG110_RES_400X240_D,
  163. .mode = {
  164. .clock = 8300,
  165. .hdisplay = 400,
  166. .hsync_start = 400 + 20,
  167. .hsync_end = 400 + 20 + 1,
  168. .htotal = 400 + 20 + 1 + 108,
  169. .vdisplay = 240,
  170. .vsync_start = 240 + 2,
  171. .vsync_end = 240 + 2 + 1,
  172. .vtotal = 240 + 2 + 1 + 20,
  173. },
  174. .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
  175. },
  176. };
  177. static inline struct tpg110 *
  178. to_tpg110(struct drm_panel *panel)
  179. {
  180. return container_of(panel, struct tpg110, panel);
  181. }
  182. static u8 tpg110_readwrite_reg(struct tpg110 *tpg, bool write,
  183. u8 address, u8 outval)
  184. {
  185. struct spi_message m;
  186. struct spi_transfer t[2];
  187. u8 buf[2];
  188. int ret;
  189. spi_message_init(&m);
  190. memset(t, 0, sizeof(t));
  191. if (write) {
  192. /*
  193. * Clear address bit 0, 1 when writing, just to be sure
  194. * The actual bit indicating a write here is bit 1, bit
  195. * 0 is just surplus to pad it up to 8 bits.
  196. */
  197. buf[0] = address << 2;
  198. buf[0] &= ~0x03;
  199. buf[1] = outval;
  200. t[0].bits_per_word = 8;
  201. t[0].tx_buf = &buf[0];
  202. t[0].len = 1;
  203. t[1].tx_buf = &buf[1];
  204. t[1].len = 1;
  205. t[1].bits_per_word = 8;
  206. } else {
  207. /* Set address bit 0 to 1 to read */
  208. buf[0] = address << 1;
  209. buf[0] |= 0x01;
  210. /*
  211. * The last bit/clock is Hi-Z turnaround cycle, so we need
  212. * to send only 7 bits here. The 8th bit is the high impedance
  213. * turn-around cycle.
  214. */
  215. t[0].bits_per_word = 7;
  216. t[0].tx_buf = &buf[0];
  217. t[0].len = 1;
  218. t[1].rx_buf = &buf[1];
  219. t[1].len = 1;
  220. t[1].bits_per_word = 8;
  221. }
  222. spi_message_add_tail(&t[0], &m);
  223. spi_message_add_tail(&t[1], &m);
  224. ret = spi_sync(tpg->spi, &m);
  225. if (ret) {
  226. dev_err(tpg->dev, "SPI message error %d\n", ret);
  227. return ret;
  228. }
  229. if (write)
  230. return 0;
  231. /* Read */
  232. return buf[1];
  233. }
  234. static u8 tpg110_read_reg(struct tpg110 *tpg, u8 address)
  235. {
  236. return tpg110_readwrite_reg(tpg, false, address, 0);
  237. }
  238. static void tpg110_write_reg(struct tpg110 *tpg, u8 address, u8 outval)
  239. {
  240. tpg110_readwrite_reg(tpg, true, address, outval);
  241. }
  242. static int tpg110_startup(struct tpg110 *tpg)
  243. {
  244. u8 val;
  245. int i;
  246. /* De-assert the reset signal */
  247. gpiod_set_value_cansleep(tpg->grestb, 0);
  248. usleep_range(1000, 2000);
  249. dev_dbg(tpg->dev, "de-asserted GRESTB\n");
  250. /* Test display communication */
  251. tpg110_write_reg(tpg, TPG110_TEST, 0x55);
  252. val = tpg110_read_reg(tpg, TPG110_TEST);
  253. if (val != 0x55) {
  254. dev_err(tpg->dev, "failed communication test\n");
  255. return -ENODEV;
  256. }
  257. val = tpg110_read_reg(tpg, TPG110_CHIPID);
  258. dev_info(tpg->dev, "TPG110 chip ID: %d version: %d\n",
  259. val >> 4, val & 0x0f);
  260. /* Show display resolution */
  261. val = tpg110_read_reg(tpg, TPG110_CTRL1);
  262. val &= TPG110_RES_MASK;
  263. switch (val) {
  264. case TPG110_RES_400X240_D:
  265. dev_info(tpg->dev, "IN 400x240 RGB -> OUT 800x480 RGB (dual scan)\n");
  266. break;
  267. case TPG110_RES_480X272_D:
  268. dev_info(tpg->dev, "IN 480x272 RGB -> OUT 800x480 RGB (dual scan)\n");
  269. break;
  270. case TPG110_RES_480X640:
  271. dev_info(tpg->dev, "480x640 RGB\n");
  272. break;
  273. case TPG110_RES_480X272:
  274. dev_info(tpg->dev, "480x272 RGB\n");
  275. break;
  276. case TPG110_RES_640X480:
  277. dev_info(tpg->dev, "640x480 RGB\n");
  278. break;
  279. case TPG110_RES_800X480:
  280. dev_info(tpg->dev, "800x480 RGB\n");
  281. break;
  282. default:
  283. dev_err(tpg->dev, "ILLEGAL RESOLUTION 0x%02x\n", val);
  284. break;
  285. }
  286. /* From the producer side, this is the same resolution */
  287. if (val == TPG110_RES_480X272_D)
  288. val = TPG110_RES_480X272;
  289. for (i = 0; i < ARRAY_SIZE(tpg110_modes); i++) {
  290. const struct tpg110_panel_mode *pm;
  291. pm = &tpg110_modes[i];
  292. if (pm->magic == val) {
  293. tpg->panel_mode = pm;
  294. break;
  295. }
  296. }
  297. if (i == ARRAY_SIZE(tpg110_modes)) {
  298. dev_err(tpg->dev, "unsupported mode (%02x) detected\n", val);
  299. return -ENODEV;
  300. }
  301. val = tpg110_read_reg(tpg, TPG110_CTRL2);
  302. dev_info(tpg->dev, "resolution and standby is controlled by %s\n",
  303. (val & TPG110_CTRL2_RES_PM_CTRL) ? "software" : "hardware");
  304. /* Take control over resolution and standby */
  305. val |= TPG110_CTRL2_RES_PM_CTRL;
  306. tpg110_write_reg(tpg, TPG110_CTRL2, val);
  307. return 0;
  308. }
  309. static int tpg110_disable(struct drm_panel *panel)
  310. {
  311. struct tpg110 *tpg = to_tpg110(panel);
  312. u8 val;
  313. /* Put chip into standby */
  314. val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
  315. val &= ~TPG110_CTRL2_PM;
  316. tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
  317. return 0;
  318. }
  319. static int tpg110_enable(struct drm_panel *panel)
  320. {
  321. struct tpg110 *tpg = to_tpg110(panel);
  322. u8 val;
  323. /* Take chip out of standby */
  324. val = tpg110_read_reg(tpg, TPG110_CTRL2_PM);
  325. val |= TPG110_CTRL2_PM;
  326. tpg110_write_reg(tpg, TPG110_CTRL2_PM, val);
  327. return 0;
  328. }
  329. /**
  330. * tpg110_get_modes() - return the appropriate mode
  331. * @panel: the panel to get the mode for
  332. *
  333. * This currently does not present a forest of modes, instead it
  334. * presents the mode that is configured for the system under use,
  335. * and which is detected by reading the registers of the display.
  336. */
  337. static int tpg110_get_modes(struct drm_panel *panel,
  338. struct drm_connector *connector)
  339. {
  340. struct tpg110 *tpg = to_tpg110(panel);
  341. struct drm_display_mode *mode;
  342. connector->display_info.width_mm = tpg->width;
  343. connector->display_info.height_mm = tpg->height;
  344. connector->display_info.bus_flags = tpg->panel_mode->bus_flags;
  345. mode = drm_mode_duplicate(connector->dev, &tpg->panel_mode->mode);
  346. drm_mode_set_name(mode);
  347. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  348. mode->width_mm = tpg->width;
  349. mode->height_mm = tpg->height;
  350. drm_mode_probed_add(connector, mode);
  351. return 1;
  352. }
  353. static const struct drm_panel_funcs tpg110_drm_funcs = {
  354. .disable = tpg110_disable,
  355. .enable = tpg110_enable,
  356. .get_modes = tpg110_get_modes,
  357. };
  358. static int tpg110_probe(struct spi_device *spi)
  359. {
  360. struct device *dev = &spi->dev;
  361. struct device_node *np = dev->of_node;
  362. struct tpg110 *tpg;
  363. int ret;
  364. tpg = devm_kzalloc(dev, sizeof(*tpg), GFP_KERNEL);
  365. if (!tpg)
  366. return -ENOMEM;
  367. tpg->dev = dev;
  368. /* We get the physical display dimensions from the DT */
  369. ret = of_property_read_u32(np, "width-mm", &tpg->width);
  370. if (ret)
  371. dev_err(dev, "no panel width specified\n");
  372. ret = of_property_read_u32(np, "height-mm", &tpg->height);
  373. if (ret)
  374. dev_err(dev, "no panel height specified\n");
  375. /* This asserts the GRESTB signal, putting the display into reset */
  376. tpg->grestb = devm_gpiod_get(dev, "grestb", GPIOD_OUT_HIGH);
  377. if (IS_ERR(tpg->grestb)) {
  378. dev_err(dev, "no GRESTB GPIO\n");
  379. return -ENODEV;
  380. }
  381. spi->bits_per_word = 8;
  382. spi->mode |= SPI_3WIRE_HIZ;
  383. ret = spi_setup(spi);
  384. if (ret < 0) {
  385. dev_err(dev, "spi setup failed.\n");
  386. return ret;
  387. }
  388. tpg->spi = spi;
  389. ret = tpg110_startup(tpg);
  390. if (ret)
  391. return ret;
  392. drm_panel_init(&tpg->panel, dev, &tpg110_drm_funcs,
  393. DRM_MODE_CONNECTOR_DPI);
  394. ret = drm_panel_of_backlight(&tpg->panel);
  395. if (ret)
  396. return ret;
  397. spi_set_drvdata(spi, tpg);
  398. drm_panel_add(&tpg->panel);
  399. return 0;
  400. }
  401. static int tpg110_remove(struct spi_device *spi)
  402. {
  403. struct tpg110 *tpg = spi_get_drvdata(spi);
  404. drm_panel_remove(&tpg->panel);
  405. return 0;
  406. }
  407. static const struct of_device_id tpg110_match[] = {
  408. { .compatible = "tpo,tpg110", },
  409. {},
  410. };
  411. MODULE_DEVICE_TABLE(of, tpg110_match);
  412. static struct spi_driver tpg110_driver = {
  413. .probe = tpg110_probe,
  414. .remove = tpg110_remove,
  415. .driver = {
  416. .name = "tpo-tpg110-panel",
  417. .of_match_table = tpg110_match,
  418. },
  419. };
  420. module_spi_driver(tpg110_driver);
  421. MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
  422. MODULE_DESCRIPTION("TPO TPG110 panel driver");
  423. MODULE_LICENSE("GPL v2");