panel-sitronix-st7701.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019, Amarula Solutions.
  4. * Author: Jagan Teki <jagan@amarulasolutions.com>
  5. */
  6. #include <drm/drm_mipi_dsi.h>
  7. #include <drm/drm_modes.h>
  8. #include <drm/drm_panel.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/delay.h>
  11. #include <linux/module.h>
  12. #include <linux/of_device.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <video/mipi_display.h>
  15. /* Command2 BKx selection command */
  16. #define DSI_CMD2BKX_SEL 0xFF
  17. /* Command2, BK0 commands */
  18. #define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
  19. #define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
  20. #define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
  21. #define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
  22. #define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
  23. /* Command2, BK1 commands */
  24. #define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
  25. #define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
  26. #define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
  27. #define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
  28. #define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
  29. #define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
  30. #define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
  31. #define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
  32. #define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
  33. #define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
  34. /**
  35. * Command2 with BK function selection.
  36. *
  37. * BIT[4, 0]: [CN2, BKXSEL]
  38. * 10 = CMD2BK0, Command2 BK0
  39. * 11 = CMD2BK1, Command2 BK1
  40. * 00 = Command2 disable
  41. */
  42. #define DSI_CMD2BK1_SEL 0x11
  43. #define DSI_CMD2BK0_SEL 0x10
  44. #define DSI_CMD2BKX_SEL_NONE 0x00
  45. /* Command2, BK0 bytes */
  46. #define DSI_LINESET_LINE 0x69
  47. #define DSI_LINESET_LDE_EN BIT(7)
  48. #define DSI_LINESET_LINEDELTA GENMASK(1, 0)
  49. #define DSI_CMD2_BK0_LNESET_B1 DSI_LINESET_LINEDELTA
  50. #define DSI_CMD2_BK0_LNESET_B0 (DSI_LINESET_LDE_EN | DSI_LINESET_LINE)
  51. #define DSI_INVSEL_DEFAULT GENMASK(5, 4)
  52. #define DSI_INVSEL_NLINV GENMASK(2, 0)
  53. #define DSI_INVSEL_RTNI GENMASK(2, 1)
  54. #define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI
  55. #define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV)
  56. #define DSI_CMD2_BK0_PORCTRL_B0(m) ((m)->vtotal - (m)->vsync_end)
  57. #define DSI_CMD2_BK0_PORCTRL_B1(m) ((m)->vsync_start - (m)->vdisplay)
  58. /* Command2, BK1 bytes */
  59. #define DSI_CMD2_BK1_VRHA_SET 0x45
  60. #define DSI_CMD2_BK1_VCOM_SET 0x13
  61. #define DSI_CMD2_BK1_VGHSS_SET GENMASK(2, 0)
  62. #define DSI_CMD2_BK1_TESTCMD_VAL BIT(7)
  63. #define DSI_VGLS_DEFAULT BIT(6)
  64. #define DSI_VGLS_SEL GENMASK(2, 0)
  65. #define DSI_CMD2_BK1_VGLS_SET (DSI_VGLS_DEFAULT | DSI_VGLS_SEL)
  66. #define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */
  67. #define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */
  68. #define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */
  69. #define DSI_CMD2_BK1_PWCTLR1_SET (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \
  70. DSI_PWCTLR1_APOS)
  71. #define DSI_PWCTLR2_AVDD BIT(5) /* AVDD 6.6v */
  72. #define DSI_PWCTLR2_AVCL 0x0 /* AVCL -4.4v */
  73. #define DSI_CMD2_BK1_PWCTLR2_SET (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL)
  74. #define DSI_SPD1_T2D BIT(3)
  75. #define DSI_CMD2_BK1_SPD1_SET (GENMASK(6, 4) | DSI_SPD1_T2D)
  76. #define DSI_CMD2_BK1_SPD2_SET DSI_CMD2_BK1_SPD1_SET
  77. #define DSI_MIPISET1_EOT_EN BIT(3)
  78. #define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN)
  79. struct st7701_panel_desc {
  80. const struct drm_display_mode *mode;
  81. unsigned int lanes;
  82. unsigned long flags;
  83. enum mipi_dsi_pixel_format format;
  84. const char *const *supply_names;
  85. unsigned int num_supplies;
  86. unsigned int panel_sleep_delay;
  87. };
  88. struct st7701 {
  89. struct drm_panel panel;
  90. struct mipi_dsi_device *dsi;
  91. const struct st7701_panel_desc *desc;
  92. struct regulator_bulk_data *supplies;
  93. struct gpio_desc *reset;
  94. unsigned int sleep_delay;
  95. };
  96. static inline struct st7701 *panel_to_st7701(struct drm_panel *panel)
  97. {
  98. return container_of(panel, struct st7701, panel);
  99. }
  100. static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq,
  101. size_t len)
  102. {
  103. return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len);
  104. }
  105. #define ST7701_DSI(st7701, seq...) \
  106. { \
  107. const u8 d[] = { seq }; \
  108. st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \
  109. }
  110. static void st7701_init_sequence(struct st7701 *st7701)
  111. {
  112. const struct drm_display_mode *mode = st7701->desc->mode;
  113. ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
  114. /* We need to wait 5ms before sending new commands */
  115. msleep(5);
  116. ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
  117. msleep(st7701->sleep_delay);
  118. /* Command2, BK0 */
  119. ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
  120. 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL);
  121. ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,
  122. 0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12,
  123. 0x2B, 0x34, 0x1F);
  124. ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,
  125. 0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E,
  126. 0x2C, 0x34, 0x1F);
  127. ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
  128. DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1);
  129. ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
  130. DSI_CMD2_BK0_PORCTRL_B0(mode),
  131. DSI_CMD2_BK0_PORCTRL_B1(mode));
  132. ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
  133. DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1);
  134. /* Command2, BK1 */
  135. ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
  136. 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL);
  137. ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, DSI_CMD2_BK1_VRHA_SET);
  138. ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, DSI_CMD2_BK1_VCOM_SET);
  139. ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, DSI_CMD2_BK1_VGHSS_SET);
  140. ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL);
  141. ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, DSI_CMD2_BK1_VGLS_SET);
  142. ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, DSI_CMD2_BK1_PWCTLR1_SET);
  143. ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, DSI_CMD2_BK1_PWCTLR2_SET);
  144. ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, DSI_CMD2_BK1_SPD1_SET);
  145. ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, DSI_CMD2_BK1_SPD2_SET);
  146. ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, DSI_CMD2_BK1_MIPISET1_SET);
  147. /**
  148. * ST7701_SPEC_V1.2 is unable to provide enough information above this
  149. * specific command sequence, so grab the same from vendor BSP driver.
  150. */
  151. ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02);
  152. ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
  153. 0x00, 0x00, 0x44, 0x44);
  154. ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
  155. 0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
  156. ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
  157. ST7701_DSI(st7701, 0xE4, 0x44, 0x44);
  158. ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
  159. 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
  160. ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
  161. ST7701_DSI(st7701, 0xE7, 0x44, 0x44);
  162. ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
  163. 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
  164. ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
  165. ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
  166. ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
  167. 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
  168. /* disable Command2 */
  169. ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
  170. 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);
  171. }
  172. static int st7701_prepare(struct drm_panel *panel)
  173. {
  174. struct st7701 *st7701 = panel_to_st7701(panel);
  175. int ret;
  176. gpiod_set_value(st7701->reset, 0);
  177. ret = regulator_bulk_enable(st7701->desc->num_supplies,
  178. st7701->supplies);
  179. if (ret < 0)
  180. return ret;
  181. msleep(20);
  182. gpiod_set_value(st7701->reset, 1);
  183. msleep(150);
  184. st7701_init_sequence(st7701);
  185. return 0;
  186. }
  187. static int st7701_enable(struct drm_panel *panel)
  188. {
  189. struct st7701 *st7701 = panel_to_st7701(panel);
  190. ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
  191. return 0;
  192. }
  193. static int st7701_disable(struct drm_panel *panel)
  194. {
  195. struct st7701 *st7701 = panel_to_st7701(panel);
  196. ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
  197. return 0;
  198. }
  199. static int st7701_unprepare(struct drm_panel *panel)
  200. {
  201. struct st7701 *st7701 = panel_to_st7701(panel);
  202. ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
  203. msleep(st7701->sleep_delay);
  204. gpiod_set_value(st7701->reset, 0);
  205. /**
  206. * During the Resetting period, the display will be blanked
  207. * (The display is entering blanking sequence, which maximum
  208. * time is 120 ms, when Reset Starts in Sleep Out –mode. The
  209. * display remains the blank state in Sleep In –mode.) and
  210. * then return to Default condition for Hardware Reset.
  211. *
  212. * So we need wait sleep_delay time to make sure reset completed.
  213. */
  214. msleep(st7701->sleep_delay);
  215. regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies);
  216. return 0;
  217. }
  218. static int st7701_get_modes(struct drm_panel *panel,
  219. struct drm_connector *connector)
  220. {
  221. struct st7701 *st7701 = panel_to_st7701(panel);
  222. const struct drm_display_mode *desc_mode = st7701->desc->mode;
  223. struct drm_display_mode *mode;
  224. mode = drm_mode_duplicate(connector->dev, desc_mode);
  225. if (!mode) {
  226. dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n",
  227. desc_mode->hdisplay, desc_mode->vdisplay,
  228. drm_mode_vrefresh(desc_mode));
  229. return -ENOMEM;
  230. }
  231. drm_mode_set_name(mode);
  232. drm_mode_probed_add(connector, mode);
  233. connector->display_info.width_mm = desc_mode->width_mm;
  234. connector->display_info.height_mm = desc_mode->height_mm;
  235. return 1;
  236. }
  237. static const struct drm_panel_funcs st7701_funcs = {
  238. .disable = st7701_disable,
  239. .unprepare = st7701_unprepare,
  240. .prepare = st7701_prepare,
  241. .enable = st7701_enable,
  242. .get_modes = st7701_get_modes,
  243. };
  244. static const struct drm_display_mode ts8550b_mode = {
  245. .clock = 27500,
  246. .hdisplay = 480,
  247. .hsync_start = 480 + 38,
  248. .hsync_end = 480 + 38 + 12,
  249. .htotal = 480 + 38 + 12 + 12,
  250. .vdisplay = 854,
  251. .vsync_start = 854 + 18,
  252. .vsync_end = 854 + 18 + 8,
  253. .vtotal = 854 + 18 + 8 + 4,
  254. .width_mm = 69,
  255. .height_mm = 139,
  256. .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  257. };
  258. static const char * const ts8550b_supply_names[] = {
  259. "VCC",
  260. "IOVCC",
  261. };
  262. static const struct st7701_panel_desc ts8550b_desc = {
  263. .mode = &ts8550b_mode,
  264. .lanes = 2,
  265. .flags = MIPI_DSI_MODE_VIDEO,
  266. .format = MIPI_DSI_FMT_RGB888,
  267. .supply_names = ts8550b_supply_names,
  268. .num_supplies = ARRAY_SIZE(ts8550b_supply_names),
  269. .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
  270. };
  271. static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
  272. {
  273. const struct st7701_panel_desc *desc;
  274. struct st7701 *st7701;
  275. int ret, i;
  276. st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL);
  277. if (!st7701)
  278. return -ENOMEM;
  279. desc = of_device_get_match_data(&dsi->dev);
  280. dsi->mode_flags = desc->flags;
  281. dsi->format = desc->format;
  282. dsi->lanes = desc->lanes;
  283. st7701->supplies = devm_kcalloc(&dsi->dev, desc->num_supplies,
  284. sizeof(*st7701->supplies),
  285. GFP_KERNEL);
  286. if (!st7701->supplies)
  287. return -ENOMEM;
  288. for (i = 0; i < desc->num_supplies; i++)
  289. st7701->supplies[i].supply = desc->supply_names[i];
  290. ret = devm_regulator_bulk_get(&dsi->dev, desc->num_supplies,
  291. st7701->supplies);
  292. if (ret < 0)
  293. return ret;
  294. st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW);
  295. if (IS_ERR(st7701->reset)) {
  296. dev_err(&dsi->dev, "Couldn't get our reset GPIO\n");
  297. return PTR_ERR(st7701->reset);
  298. }
  299. drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs,
  300. DRM_MODE_CONNECTOR_DSI);
  301. /**
  302. * Once sleep out has been issued, ST7701 IC required to wait 120ms
  303. * before initiating new commands.
  304. *
  305. * On top of that some panels might need an extra delay to wait, so
  306. * add panel specific delay for those cases. As now this panel specific
  307. * delay information is referenced from those panel BSP driver, example
  308. * ts8550b and there is no valid documentation for that.
  309. */
  310. st7701->sleep_delay = 120 + desc->panel_sleep_delay;
  311. ret = drm_panel_of_backlight(&st7701->panel);
  312. if (ret)
  313. return ret;
  314. drm_panel_add(&st7701->panel);
  315. mipi_dsi_set_drvdata(dsi, st7701);
  316. st7701->dsi = dsi;
  317. st7701->desc = desc;
  318. return mipi_dsi_attach(dsi);
  319. }
  320. static int st7701_dsi_remove(struct mipi_dsi_device *dsi)
  321. {
  322. struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi);
  323. mipi_dsi_detach(dsi);
  324. drm_panel_remove(&st7701->panel);
  325. return 0;
  326. }
  327. static const struct of_device_id st7701_of_match[] = {
  328. { .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
  329. { }
  330. };
  331. MODULE_DEVICE_TABLE(of, st7701_of_match);
  332. static struct mipi_dsi_driver st7701_dsi_driver = {
  333. .probe = st7701_dsi_probe,
  334. .remove = st7701_dsi_remove,
  335. .driver = {
  336. .name = "st7701",
  337. .of_match_table = st7701_of_match,
  338. },
  339. };
  340. module_mipi_dsi_driver(st7701_dsi_driver);
  341. MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
  342. MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver");
  343. MODULE_LICENSE("GPL");