panel-samsung-s6e8aa0.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MIPI-DSI based s6e8aa0 AMOLED LCD 5.3 inch panel driver.
  4. *
  5. * Copyright (c) 2013 Samsung Electronics Co., Ltd
  6. *
  7. * Inki Dae, <inki.dae@samsung.com>
  8. * Donghwa Lee, <dh09.lee@samsung.com>
  9. * Joongmock Shin <jmock.shin@samsung.com>
  10. * Eunchul Kim <chulspro.kim@samsung.com>
  11. * Tomasz Figa <t.figa@samsung.com>
  12. * Andrzej Hajda <a.hajda@samsung.com>
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <video/mipi_display.h>
  20. #include <video/of_videomode.h>
  21. #include <video/videomode.h>
  22. #include <drm/drm_mipi_dsi.h>
  23. #include <drm/drm_modes.h>
  24. #include <drm/drm_panel.h>
  25. #define LDI_MTP_LENGTH 24
  26. #define GAMMA_LEVEL_NUM 25
  27. #define GAMMA_TABLE_LEN 26
  28. #define PANELCTL_SS_MASK (1 << 5)
  29. #define PANELCTL_SS_1_800 (0 << 5)
  30. #define PANELCTL_SS_800_1 (1 << 5)
  31. #define PANELCTL_GTCON_MASK (7 << 2)
  32. #define PANELCTL_GTCON_110 (6 << 2)
  33. #define PANELCTL_GTCON_111 (7 << 2)
  34. #define PANELCTL_CLK1_CON_MASK (7 << 3)
  35. #define PANELCTL_CLK1_000 (0 << 3)
  36. #define PANELCTL_CLK1_001 (1 << 3)
  37. #define PANELCTL_CLK2_CON_MASK (7 << 0)
  38. #define PANELCTL_CLK2_000 (0 << 0)
  39. #define PANELCTL_CLK2_001 (1 << 0)
  40. #define PANELCTL_INT1_CON_MASK (7 << 3)
  41. #define PANELCTL_INT1_000 (0 << 3)
  42. #define PANELCTL_INT1_001 (1 << 3)
  43. #define PANELCTL_INT2_CON_MASK (7 << 0)
  44. #define PANELCTL_INT2_000 (0 << 0)
  45. #define PANELCTL_INT2_001 (1 << 0)
  46. #define PANELCTL_BICTL_CON_MASK (7 << 3)
  47. #define PANELCTL_BICTL_000 (0 << 3)
  48. #define PANELCTL_BICTL_001 (1 << 3)
  49. #define PANELCTL_BICTLB_CON_MASK (7 << 0)
  50. #define PANELCTL_BICTLB_000 (0 << 0)
  51. #define PANELCTL_BICTLB_001 (1 << 0)
  52. #define PANELCTL_EM_CLK1_CON_MASK (7 << 3)
  53. #define PANELCTL_EM_CLK1_110 (6 << 3)
  54. #define PANELCTL_EM_CLK1_111 (7 << 3)
  55. #define PANELCTL_EM_CLK1B_CON_MASK (7 << 0)
  56. #define PANELCTL_EM_CLK1B_110 (6 << 0)
  57. #define PANELCTL_EM_CLK1B_111 (7 << 0)
  58. #define PANELCTL_EM_CLK2_CON_MASK (7 << 3)
  59. #define PANELCTL_EM_CLK2_110 (6 << 3)
  60. #define PANELCTL_EM_CLK2_111 (7 << 3)
  61. #define PANELCTL_EM_CLK2B_CON_MASK (7 << 0)
  62. #define PANELCTL_EM_CLK2B_110 (6 << 0)
  63. #define PANELCTL_EM_CLK2B_111 (7 << 0)
  64. #define PANELCTL_EM_INT1_CON_MASK (7 << 3)
  65. #define PANELCTL_EM_INT1_000 (0 << 3)
  66. #define PANELCTL_EM_INT1_001 (1 << 3)
  67. #define PANELCTL_EM_INT2_CON_MASK (7 << 0)
  68. #define PANELCTL_EM_INT2_000 (0 << 0)
  69. #define PANELCTL_EM_INT2_001 (1 << 0)
  70. #define AID_DISABLE (0x4)
  71. #define AID_1 (0x5)
  72. #define AID_2 (0x6)
  73. #define AID_3 (0x7)
  74. typedef u8 s6e8aa0_gamma_table[GAMMA_TABLE_LEN];
  75. struct s6e8aa0_variant {
  76. u8 version;
  77. const s6e8aa0_gamma_table *gamma_tables;
  78. };
  79. struct s6e8aa0 {
  80. struct device *dev;
  81. struct drm_panel panel;
  82. struct regulator_bulk_data supplies[2];
  83. struct gpio_desc *reset_gpio;
  84. u32 power_on_delay;
  85. u32 reset_delay;
  86. u32 init_delay;
  87. bool flip_horizontal;
  88. bool flip_vertical;
  89. struct videomode vm;
  90. u32 width_mm;
  91. u32 height_mm;
  92. u8 version;
  93. u8 id;
  94. const struct s6e8aa0_variant *variant;
  95. int brightness;
  96. /* This field is tested by functions directly accessing DSI bus before
  97. * transfer, transfer is skipped if it is set. In case of transfer
  98. * failure or unexpected response the field is set to error value.
  99. * Such construct allows to eliminate many checks in higher level
  100. * functions.
  101. */
  102. int error;
  103. };
  104. static inline struct s6e8aa0 *panel_to_s6e8aa0(struct drm_panel *panel)
  105. {
  106. return container_of(panel, struct s6e8aa0, panel);
  107. }
  108. static int s6e8aa0_clear_error(struct s6e8aa0 *ctx)
  109. {
  110. int ret = ctx->error;
  111. ctx->error = 0;
  112. return ret;
  113. }
  114. static void s6e8aa0_dcs_write(struct s6e8aa0 *ctx, const void *data, size_t len)
  115. {
  116. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  117. ssize_t ret;
  118. if (ctx->error < 0)
  119. return;
  120. ret = mipi_dsi_dcs_write_buffer(dsi, data, len);
  121. if (ret < 0) {
  122. dev_err(ctx->dev, "error %zd writing dcs seq: %*ph\n", ret,
  123. (int)len, data);
  124. ctx->error = ret;
  125. }
  126. }
  127. static int s6e8aa0_dcs_read(struct s6e8aa0 *ctx, u8 cmd, void *data, size_t len)
  128. {
  129. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  130. int ret;
  131. if (ctx->error < 0)
  132. return ctx->error;
  133. ret = mipi_dsi_dcs_read(dsi, cmd, data, len);
  134. if (ret < 0) {
  135. dev_err(ctx->dev, "error %d reading dcs seq(%#x)\n", ret, cmd);
  136. ctx->error = ret;
  137. }
  138. return ret;
  139. }
  140. #define s6e8aa0_dcs_write_seq(ctx, seq...) \
  141. ({\
  142. const u8 d[] = { seq };\
  143. BUILD_BUG_ON_MSG(ARRAY_SIZE(d) > 64, "DCS sequence too big for stack");\
  144. s6e8aa0_dcs_write(ctx, d, ARRAY_SIZE(d));\
  145. })
  146. #define s6e8aa0_dcs_write_seq_static(ctx, seq...) \
  147. ({\
  148. static const u8 d[] = { seq };\
  149. s6e8aa0_dcs_write(ctx, d, ARRAY_SIZE(d));\
  150. })
  151. static void s6e8aa0_apply_level_1_key(struct s6e8aa0 *ctx)
  152. {
  153. s6e8aa0_dcs_write_seq_static(ctx, 0xf0, 0x5a, 0x5a);
  154. }
  155. static void s6e8aa0_panel_cond_set_v142(struct s6e8aa0 *ctx)
  156. {
  157. static const u8 aids[] = {
  158. 0x04, 0x04, 0x04, 0x04, 0x04, 0x60, 0x80, 0xA0
  159. };
  160. u8 aid = aids[ctx->id >> 5];
  161. u8 cfg = 0x3d;
  162. u8 clk_con = 0xc8;
  163. u8 int_con = 0x08;
  164. u8 bictl_con = 0x48;
  165. u8 em_clk1_con = 0xff;
  166. u8 em_clk2_con = 0xff;
  167. u8 em_int_con = 0xc8;
  168. if (ctx->flip_vertical) {
  169. /* GTCON */
  170. cfg &= ~(PANELCTL_GTCON_MASK);
  171. cfg |= (PANELCTL_GTCON_110);
  172. }
  173. if (ctx->flip_horizontal) {
  174. /* SS */
  175. cfg &= ~(PANELCTL_SS_MASK);
  176. cfg |= (PANELCTL_SS_1_800);
  177. }
  178. if (ctx->flip_horizontal || ctx->flip_vertical) {
  179. /* CLK1,2_CON */
  180. clk_con &= ~(PANELCTL_CLK1_CON_MASK |
  181. PANELCTL_CLK2_CON_MASK);
  182. clk_con |= (PANELCTL_CLK1_000 | PANELCTL_CLK2_001);
  183. /* INT1,2_CON */
  184. int_con &= ~(PANELCTL_INT1_CON_MASK |
  185. PANELCTL_INT2_CON_MASK);
  186. int_con |= (PANELCTL_INT1_000 | PANELCTL_INT2_001);
  187. /* BICTL,B_CON */
  188. bictl_con &= ~(PANELCTL_BICTL_CON_MASK |
  189. PANELCTL_BICTLB_CON_MASK);
  190. bictl_con |= (PANELCTL_BICTL_000 |
  191. PANELCTL_BICTLB_001);
  192. /* EM_CLK1,1B_CON */
  193. em_clk1_con &= ~(PANELCTL_EM_CLK1_CON_MASK |
  194. PANELCTL_EM_CLK1B_CON_MASK);
  195. em_clk1_con |= (PANELCTL_EM_CLK1_110 |
  196. PANELCTL_EM_CLK1B_110);
  197. /* EM_CLK2,2B_CON */
  198. em_clk2_con &= ~(PANELCTL_EM_CLK2_CON_MASK |
  199. PANELCTL_EM_CLK2B_CON_MASK);
  200. em_clk2_con |= (PANELCTL_EM_CLK2_110 |
  201. PANELCTL_EM_CLK2B_110);
  202. /* EM_INT1,2_CON */
  203. em_int_con &= ~(PANELCTL_EM_INT1_CON_MASK |
  204. PANELCTL_EM_INT2_CON_MASK);
  205. em_int_con |= (PANELCTL_EM_INT1_000 |
  206. PANELCTL_EM_INT2_001);
  207. }
  208. s6e8aa0_dcs_write_seq(ctx,
  209. 0xf8, cfg, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00,
  210. 0x3c, 0x78, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00,
  211. 0x00, 0x20, aid, 0x08, 0x6e, 0x00, 0x00, 0x00,
  212. 0x02, 0x07, 0x07, 0x23, 0x23, 0xc0, clk_con, int_con,
  213. bictl_con, 0xc1, 0x00, 0xc1, em_clk1_con, em_clk2_con,
  214. em_int_con);
  215. }
  216. static void s6e8aa0_panel_cond_set(struct s6e8aa0 *ctx)
  217. {
  218. if (ctx->version < 142)
  219. s6e8aa0_dcs_write_seq_static(ctx,
  220. 0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x94, 0x00,
  221. 0x3c, 0x78, 0x10, 0x27, 0x08, 0x6e, 0x00, 0x00,
  222. 0x00, 0x00, 0x04, 0x08, 0x6e, 0x00, 0x00, 0x00,
  223. 0x00, 0x07, 0x07, 0x23, 0x6e, 0xc0, 0xc1, 0x01,
  224. 0x81, 0xc1, 0x00, 0xc3, 0xf6, 0xf6, 0xc1
  225. );
  226. else
  227. s6e8aa0_panel_cond_set_v142(ctx);
  228. }
  229. static void s6e8aa0_display_condition_set(struct s6e8aa0 *ctx)
  230. {
  231. s6e8aa0_dcs_write_seq_static(ctx, 0xf2, 0x80, 0x03, 0x0d);
  232. }
  233. static void s6e8aa0_etc_source_control(struct s6e8aa0 *ctx)
  234. {
  235. s6e8aa0_dcs_write_seq_static(ctx, 0xf6, 0x00, 0x02, 0x00);
  236. }
  237. static void s6e8aa0_etc_pentile_control(struct s6e8aa0 *ctx)
  238. {
  239. static const u8 pent32[] = {
  240. 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xc0, 0x44, 0x44, 0xc0, 0x00
  241. };
  242. static const u8 pent142[] = {
  243. 0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0, 0x00
  244. };
  245. if (ctx->version < 142)
  246. s6e8aa0_dcs_write(ctx, pent32, ARRAY_SIZE(pent32));
  247. else
  248. s6e8aa0_dcs_write(ctx, pent142, ARRAY_SIZE(pent142));
  249. }
  250. static void s6e8aa0_etc_power_control(struct s6e8aa0 *ctx)
  251. {
  252. static const u8 pwr142[] = {
  253. 0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x1e, 0x33, 0x02
  254. };
  255. static const u8 pwr32[] = {
  256. 0xf4, 0xcf, 0x0a, 0x15, 0x10, 0x19, 0x33, 0x02
  257. };
  258. if (ctx->version < 142)
  259. s6e8aa0_dcs_write(ctx, pwr32, ARRAY_SIZE(pwr32));
  260. else
  261. s6e8aa0_dcs_write(ctx, pwr142, ARRAY_SIZE(pwr142));
  262. }
  263. static void s6e8aa0_etc_elvss_control(struct s6e8aa0 *ctx)
  264. {
  265. u8 id = ctx->id ? 0 : 0x95;
  266. s6e8aa0_dcs_write_seq(ctx, 0xb1, 0x04, id);
  267. }
  268. static void s6e8aa0_elvss_nvm_set_v142(struct s6e8aa0 *ctx)
  269. {
  270. u8 br;
  271. switch (ctx->brightness) {
  272. case 0 ... 6: /* 30cd ~ 100cd */
  273. br = 0xdf;
  274. break;
  275. case 7 ... 11: /* 120cd ~ 150cd */
  276. br = 0xdd;
  277. break;
  278. case 12 ... 15: /* 180cd ~ 210cd */
  279. default:
  280. br = 0xd9;
  281. break;
  282. case 16 ... 24: /* 240cd ~ 300cd */
  283. br = 0xd0;
  284. break;
  285. }
  286. s6e8aa0_dcs_write_seq(ctx, 0xd9, 0x14, 0x40, 0x0c, 0xcb, 0xce, 0x6e,
  287. 0xc4, 0x0f, 0x40, 0x41, br, 0x00, 0x60, 0x19);
  288. }
  289. static void s6e8aa0_elvss_nvm_set(struct s6e8aa0 *ctx)
  290. {
  291. if (ctx->version < 142)
  292. s6e8aa0_dcs_write_seq_static(ctx,
  293. 0xd9, 0x14, 0x40, 0x0c, 0xcb, 0xce, 0x6e, 0xc4, 0x07,
  294. 0x40, 0x41, 0xc1, 0x00, 0x60, 0x19);
  295. else
  296. s6e8aa0_elvss_nvm_set_v142(ctx);
  297. };
  298. static void s6e8aa0_apply_level_2_key(struct s6e8aa0 *ctx)
  299. {
  300. s6e8aa0_dcs_write_seq_static(ctx, 0xfc, 0x5a, 0x5a);
  301. }
  302. static const s6e8aa0_gamma_table s6e8aa0_gamma_tables_v142[GAMMA_LEVEL_NUM] = {
  303. {
  304. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x62, 0x55, 0x55,
  305. 0xaf, 0xb1, 0xb1, 0xbd, 0xce, 0xb7, 0x9a, 0xb1,
  306. 0x90, 0xb2, 0xc4, 0xae, 0x00, 0x60, 0x00, 0x40,
  307. 0x00, 0x70,
  308. }, {
  309. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x74, 0x68, 0x69,
  310. 0xb8, 0xc1, 0xb7, 0xbd, 0xcd, 0xb8, 0x93, 0xab,
  311. 0x88, 0xb4, 0xc4, 0xb1, 0x00, 0x6b, 0x00, 0x4d,
  312. 0x00, 0x7d,
  313. }, {
  314. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x95, 0x8a, 0x89,
  315. 0xb4, 0xc6, 0xb2, 0xc5, 0xd2, 0xbf, 0x90, 0xa8,
  316. 0x85, 0xb5, 0xc4, 0xb3, 0x00, 0x7b, 0x00, 0x5d,
  317. 0x00, 0x8f,
  318. }, {
  319. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x9f, 0x98, 0x92,
  320. 0xb3, 0xc4, 0xb0, 0xbc, 0xcc, 0xb4, 0x91, 0xa6,
  321. 0x87, 0xb5, 0xc5, 0xb4, 0x00, 0x87, 0x00, 0x6a,
  322. 0x00, 0x9e,
  323. }, {
  324. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x99, 0x93, 0x8b,
  325. 0xb2, 0xc2, 0xb0, 0xbd, 0xce, 0xb4, 0x90, 0xa6,
  326. 0x87, 0xb3, 0xc3, 0xb2, 0x00, 0x8d, 0x00, 0x70,
  327. 0x00, 0xa4,
  328. }, {
  329. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xa5, 0x99,
  330. 0xb2, 0xc2, 0xb0, 0xbb, 0xcd, 0xb1, 0x93, 0xa7,
  331. 0x8a, 0xb2, 0xc1, 0xb0, 0x00, 0x92, 0x00, 0x75,
  332. 0x00, 0xaa,
  333. }, {
  334. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa0, 0xa0, 0x93,
  335. 0xb6, 0xc4, 0xb4, 0xb5, 0xc8, 0xaa, 0x94, 0xa9,
  336. 0x8c, 0xb2, 0xc0, 0xb0, 0x00, 0x97, 0x00, 0x7a,
  337. 0x00, 0xaf,
  338. }, {
  339. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xa7, 0x96,
  340. 0xb3, 0xc2, 0xb0, 0xba, 0xcb, 0xb0, 0x94, 0xa8,
  341. 0x8c, 0xb0, 0xbf, 0xaf, 0x00, 0x9f, 0x00, 0x83,
  342. 0x00, 0xb9,
  343. }, {
  344. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x9d, 0xa2, 0x90,
  345. 0xb6, 0xc5, 0xb3, 0xb8, 0xc9, 0xae, 0x94, 0xa8,
  346. 0x8d, 0xaf, 0xbd, 0xad, 0x00, 0xa4, 0x00, 0x88,
  347. 0x00, 0xbf,
  348. }, {
  349. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa6, 0xac, 0x97,
  350. 0xb4, 0xc4, 0xb1, 0xbb, 0xcb, 0xb2, 0x93, 0xa7,
  351. 0x8d, 0xae, 0xbc, 0xad, 0x00, 0xa7, 0x00, 0x8c,
  352. 0x00, 0xc3,
  353. }, {
  354. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa2, 0xa9, 0x93,
  355. 0xb6, 0xc5, 0xb2, 0xba, 0xc9, 0xb0, 0x93, 0xa7,
  356. 0x8d, 0xae, 0xbb, 0xac, 0x00, 0xab, 0x00, 0x90,
  357. 0x00, 0xc8,
  358. }, {
  359. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0x9e, 0xa6, 0x8f,
  360. 0xb7, 0xc6, 0xb3, 0xb8, 0xc8, 0xb0, 0x93, 0xa6,
  361. 0x8c, 0xae, 0xbb, 0xad, 0x00, 0xae, 0x00, 0x93,
  362. 0x00, 0xcc,
  363. }, {
  364. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xab, 0xb4, 0x9c,
  365. 0xb3, 0xc3, 0xaf, 0xb7, 0xc7, 0xaf, 0x93, 0xa6,
  366. 0x8c, 0xaf, 0xbc, 0xad, 0x00, 0xb1, 0x00, 0x97,
  367. 0x00, 0xcf,
  368. }, {
  369. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa6, 0xb1, 0x98,
  370. 0xb1, 0xc2, 0xab, 0xba, 0xc9, 0xb2, 0x93, 0xa6,
  371. 0x8d, 0xae, 0xba, 0xab, 0x00, 0xb5, 0x00, 0x9b,
  372. 0x00, 0xd4,
  373. }, {
  374. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xae, 0x94,
  375. 0xb2, 0xc3, 0xac, 0xbb, 0xca, 0xb4, 0x91, 0xa4,
  376. 0x8a, 0xae, 0xba, 0xac, 0x00, 0xb8, 0x00, 0x9e,
  377. 0x00, 0xd8,
  378. }, {
  379. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xab, 0xb7, 0x9c,
  380. 0xae, 0xc0, 0xa9, 0xba, 0xc9, 0xb3, 0x92, 0xa5,
  381. 0x8b, 0xad, 0xb9, 0xab, 0x00, 0xbb, 0x00, 0xa1,
  382. 0x00, 0xdc,
  383. }, {
  384. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xb4, 0x97,
  385. 0xb0, 0xc1, 0xaa, 0xb9, 0xc8, 0xb2, 0x92, 0xa5,
  386. 0x8c, 0xae, 0xb9, 0xab, 0x00, 0xbe, 0x00, 0xa4,
  387. 0x00, 0xdf,
  388. }, {
  389. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xb0, 0x94,
  390. 0xb0, 0xc2, 0xab, 0xbb, 0xc9, 0xb3, 0x91, 0xa4,
  391. 0x8b, 0xad, 0xb8, 0xaa, 0x00, 0xc1, 0x00, 0xa8,
  392. 0x00, 0xe2,
  393. }, {
  394. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa3, 0xb0, 0x94,
  395. 0xae, 0xbf, 0xa8, 0xb9, 0xc8, 0xb3, 0x92, 0xa4,
  396. 0x8b, 0xad, 0xb7, 0xa9, 0x00, 0xc4, 0x00, 0xab,
  397. 0x00, 0xe6,
  398. }, {
  399. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xb6, 0x98,
  400. 0xaf, 0xc0, 0xa8, 0xb8, 0xc7, 0xb2, 0x93, 0xa5,
  401. 0x8d, 0xad, 0xb7, 0xa9, 0x00, 0xc7, 0x00, 0xae,
  402. 0x00, 0xe9,
  403. }, {
  404. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa4, 0xb3, 0x95,
  405. 0xaf, 0xc1, 0xa9, 0xb9, 0xc8, 0xb3, 0x92, 0xa4,
  406. 0x8b, 0xad, 0xb7, 0xaa, 0x00, 0xc9, 0x00, 0xb0,
  407. 0x00, 0xec,
  408. }, {
  409. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa4, 0xb3, 0x95,
  410. 0xac, 0xbe, 0xa6, 0xbb, 0xc9, 0xb4, 0x90, 0xa3,
  411. 0x8a, 0xad, 0xb7, 0xa9, 0x00, 0xcc, 0x00, 0xb4,
  412. 0x00, 0xf0,
  413. }, {
  414. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa0, 0xb0, 0x91,
  415. 0xae, 0xc0, 0xa6, 0xba, 0xc8, 0xb4, 0x91, 0xa4,
  416. 0x8b, 0xad, 0xb7, 0xa9, 0x00, 0xcf, 0x00, 0xb7,
  417. 0x00, 0xf3,
  418. }, {
  419. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa7, 0xb8, 0x98,
  420. 0xab, 0xbd, 0xa4, 0xbb, 0xc9, 0xb5, 0x91, 0xa3,
  421. 0x8b, 0xac, 0xb6, 0xa8, 0x00, 0xd1, 0x00, 0xb9,
  422. 0x00, 0xf6,
  423. }, {
  424. 0xfa, 0x01, 0x71, 0x31, 0x7b, 0xa4, 0xb5, 0x95,
  425. 0xa9, 0xbc, 0xa1, 0xbb, 0xc9, 0xb5, 0x91, 0xa3,
  426. 0x8a, 0xad, 0xb6, 0xa8, 0x00, 0xd6, 0x00, 0xbf,
  427. 0x00, 0xfc,
  428. },
  429. };
  430. static const s6e8aa0_gamma_table s6e8aa0_gamma_tables_v96[GAMMA_LEVEL_NUM] = {
  431. {
  432. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  433. 0xdf, 0x1f, 0xd7, 0xdc, 0xb7, 0xe1, 0xc0, 0xaf,
  434. 0xc4, 0xd2, 0xd0, 0xcf, 0x00, 0x4d, 0x00, 0x40,
  435. 0x00, 0x5f,
  436. }, {
  437. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  438. 0xd5, 0x35, 0xcf, 0xdc, 0xc1, 0xe1, 0xbf, 0xb3,
  439. 0xc1, 0xd2, 0xd1, 0xce, 0x00, 0x53, 0x00, 0x46,
  440. 0x00, 0x67,
  441. }, {
  442. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  443. 0xd2, 0x64, 0xcf, 0xdb, 0xc6, 0xe1, 0xbd, 0xb3,
  444. 0xbd, 0xd2, 0xd2, 0xce, 0x00, 0x59, 0x00, 0x4b,
  445. 0x00, 0x6e,
  446. }, {
  447. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  448. 0xd0, 0x7c, 0xcf, 0xdb, 0xc9, 0xe0, 0xbc, 0xb4,
  449. 0xbb, 0xcf, 0xd1, 0xcc, 0x00, 0x5f, 0x00, 0x50,
  450. 0x00, 0x75,
  451. }, {
  452. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  453. 0xd0, 0x8e, 0xd1, 0xdb, 0xcc, 0xdf, 0xbb, 0xb6,
  454. 0xb9, 0xd0, 0xd1, 0xcd, 0x00, 0x63, 0x00, 0x54,
  455. 0x00, 0x7a,
  456. }, {
  457. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  458. 0xd1, 0x9e, 0xd5, 0xda, 0xcd, 0xdd, 0xbb, 0xb7,
  459. 0xb9, 0xce, 0xce, 0xc9, 0x00, 0x68, 0x00, 0x59,
  460. 0x00, 0x81,
  461. }, {
  462. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x00, 0xff,
  463. 0xd0, 0xa5, 0xd6, 0xda, 0xcf, 0xdd, 0xbb, 0xb7,
  464. 0xb8, 0xcc, 0xcd, 0xc7, 0x00, 0x6c, 0x00, 0x5c,
  465. 0x00, 0x86,
  466. }, {
  467. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x1f, 0xfe,
  468. 0xd0, 0xae, 0xd7, 0xd9, 0xd0, 0xdb, 0xb9, 0xb6,
  469. 0xb5, 0xca, 0xcc, 0xc5, 0x00, 0x74, 0x00, 0x63,
  470. 0x00, 0x90,
  471. }, {
  472. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x1f, 0xf9,
  473. 0xcf, 0xb0, 0xd6, 0xd9, 0xd1, 0xdb, 0xb9, 0xb6,
  474. 0xb4, 0xca, 0xcb, 0xc5, 0x00, 0x77, 0x00, 0x66,
  475. 0x00, 0x94,
  476. }, {
  477. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xff, 0x1f, 0xf7,
  478. 0xcf, 0xb3, 0xd7, 0xd8, 0xd1, 0xd9, 0xb7, 0xb6,
  479. 0xb3, 0xc9, 0xca, 0xc3, 0x00, 0x7b, 0x00, 0x69,
  480. 0x00, 0x99,
  481. }, {
  482. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xfd, 0x2f, 0xf7,
  483. 0xdf, 0xb5, 0xd6, 0xd8, 0xd1, 0xd8, 0xb6, 0xb5,
  484. 0xb2, 0xca, 0xcb, 0xc4, 0x00, 0x7e, 0x00, 0x6c,
  485. 0x00, 0x9d,
  486. }, {
  487. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xfa, 0x2f, 0xf5,
  488. 0xce, 0xb6, 0xd5, 0xd7, 0xd2, 0xd8, 0xb6, 0xb4,
  489. 0xb0, 0xc7, 0xc9, 0xc1, 0x00, 0x84, 0x00, 0x71,
  490. 0x00, 0xa5,
  491. }, {
  492. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xf7, 0x2f, 0xf2,
  493. 0xce, 0xb9, 0xd5, 0xd8, 0xd2, 0xd8, 0xb4, 0xb4,
  494. 0xaf, 0xc7, 0xc9, 0xc1, 0x00, 0x87, 0x00, 0x73,
  495. 0x00, 0xa8,
  496. }, {
  497. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xf5, 0x2f, 0xf0,
  498. 0xdf, 0xba, 0xd5, 0xd7, 0xd2, 0xd7, 0xb4, 0xb4,
  499. 0xaf, 0xc5, 0xc7, 0xbf, 0x00, 0x8a, 0x00, 0x76,
  500. 0x00, 0xac,
  501. }, {
  502. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xf2, 0x2f, 0xed,
  503. 0xcE, 0xbb, 0xd4, 0xd6, 0xd2, 0xd6, 0xb5, 0xb4,
  504. 0xaF, 0xc5, 0xc7, 0xbf, 0x00, 0x8c, 0x00, 0x78,
  505. 0x00, 0xaf,
  506. }, {
  507. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xef, 0x2f, 0xeb,
  508. 0xcd, 0xbb, 0xd2, 0xd7, 0xd3, 0xd6, 0xb3, 0xb4,
  509. 0xae, 0xc5, 0xc6, 0xbe, 0x00, 0x91, 0x00, 0x7d,
  510. 0x00, 0xb6,
  511. }, {
  512. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xee, 0x2f, 0xea,
  513. 0xce, 0xbd, 0xd4, 0xd6, 0xd2, 0xd5, 0xb2, 0xb3,
  514. 0xad, 0xc3, 0xc4, 0xbb, 0x00, 0x94, 0x00, 0x7f,
  515. 0x00, 0xba,
  516. }, {
  517. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xec, 0x2f, 0xe8,
  518. 0xce, 0xbe, 0xd3, 0xd6, 0xd3, 0xd5, 0xb2, 0xb2,
  519. 0xac, 0xc3, 0xc5, 0xbc, 0x00, 0x96, 0x00, 0x81,
  520. 0x00, 0xbd,
  521. }, {
  522. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xeb, 0x2f, 0xe7,
  523. 0xce, 0xbf, 0xd3, 0xd6, 0xd2, 0xd5, 0xb1, 0xb2,
  524. 0xab, 0xc2, 0xc4, 0xbb, 0x00, 0x99, 0x00, 0x83,
  525. 0x00, 0xc0,
  526. }, {
  527. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xef, 0x5f, 0xe9,
  528. 0xca, 0xbf, 0xd3, 0xd5, 0xd2, 0xd4, 0xb2, 0xb2,
  529. 0xab, 0xc1, 0xc4, 0xba, 0x00, 0x9b, 0x00, 0x85,
  530. 0x00, 0xc3,
  531. }, {
  532. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xea, 0x5f, 0xe8,
  533. 0xee, 0xbf, 0xd2, 0xd5, 0xd2, 0xd4, 0xb1, 0xb2,
  534. 0xab, 0xc1, 0xc2, 0xb9, 0x00, 0x9D, 0x00, 0x87,
  535. 0x00, 0xc6,
  536. }, {
  537. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe9, 0x5f, 0xe7,
  538. 0xcd, 0xbf, 0xd2, 0xd6, 0xd2, 0xd4, 0xb1, 0xb2,
  539. 0xab, 0xbe, 0xc0, 0xb7, 0x00, 0xa1, 0x00, 0x8a,
  540. 0x00, 0xca,
  541. }, {
  542. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe8, 0x61, 0xe6,
  543. 0xcd, 0xbf, 0xd1, 0xd6, 0xd3, 0xd4, 0xaf, 0xb0,
  544. 0xa9, 0xbe, 0xc1, 0xb7, 0x00, 0xa3, 0x00, 0x8b,
  545. 0x00, 0xce,
  546. }, {
  547. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe8, 0x62, 0xe5,
  548. 0xcc, 0xc0, 0xd0, 0xd6, 0xd2, 0xd4, 0xaf, 0xb1,
  549. 0xa9, 0xbd, 0xc0, 0xb6, 0x00, 0xa5, 0x00, 0x8d,
  550. 0x00, 0xd0,
  551. }, {
  552. 0xfa, 0x01, 0x1f, 0x1f, 0x1f, 0xe7, 0x7f, 0xe3,
  553. 0xcc, 0xc1, 0xd0, 0xd5, 0xd3, 0xd3, 0xae, 0xaf,
  554. 0xa8, 0xbe, 0xc0, 0xb7, 0x00, 0xa8, 0x00, 0x90,
  555. 0x00, 0xd3,
  556. }
  557. };
  558. static const s6e8aa0_gamma_table s6e8aa0_gamma_tables_v32[GAMMA_LEVEL_NUM] = {
  559. {
  560. 0xfa, 0x01, 0x43, 0x14, 0x45, 0x72, 0x5e, 0x6b,
  561. 0xa1, 0xa7, 0x9a, 0xb4, 0xcb, 0xb8, 0x92, 0xac,
  562. 0x97, 0xb4, 0xc3, 0xb5, 0x00, 0x4e, 0x00, 0x37,
  563. 0x00, 0x58,
  564. }, {
  565. 0xfa, 0x01, 0x43, 0x14, 0x45, 0x85, 0x71, 0x7d,
  566. 0xa6, 0xb6, 0xa1, 0xb5, 0xca, 0xba, 0x93, 0xac,
  567. 0x98, 0xb2, 0xc0, 0xaf, 0x00, 0x59, 0x00, 0x43,
  568. 0x00, 0x64,
  569. }, {
  570. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa4, 0x94, 0x9e,
  571. 0xa0, 0xbb, 0x9c, 0xc3, 0xd2, 0xc6, 0x93, 0xaa,
  572. 0x95, 0xb7, 0xc2, 0xb4, 0x00, 0x65, 0x00, 0x50,
  573. 0x00, 0x74,
  574. }, {
  575. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xa1, 0xa6,
  576. 0xa0, 0xb9, 0x9b, 0xc3, 0xd1, 0xc8, 0x90, 0xa6,
  577. 0x90, 0xbb, 0xc3, 0xb7, 0x00, 0x6f, 0x00, 0x5b,
  578. 0x00, 0x80,
  579. }, {
  580. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa6, 0x9d, 0x9f,
  581. 0x9f, 0xb8, 0x9a, 0xc7, 0xd5, 0xcc, 0x90, 0xa5,
  582. 0x8f, 0xb8, 0xc1, 0xb6, 0x00, 0x74, 0x00, 0x60,
  583. 0x00, 0x85,
  584. }, {
  585. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb3, 0xae, 0xae,
  586. 0x9e, 0xb7, 0x9a, 0xc8, 0xd6, 0xce, 0x91, 0xa6,
  587. 0x90, 0xb6, 0xc0, 0xb3, 0x00, 0x78, 0x00, 0x65,
  588. 0x00, 0x8a,
  589. }, {
  590. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xa9, 0xa8,
  591. 0xa3, 0xb9, 0x9e, 0xc4, 0xd3, 0xcb, 0x94, 0xa6,
  592. 0x90, 0xb6, 0xbf, 0xb3, 0x00, 0x7c, 0x00, 0x69,
  593. 0x00, 0x8e,
  594. }, {
  595. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xaf, 0xaf, 0xa9,
  596. 0xa5, 0xbc, 0xa2, 0xc7, 0xd5, 0xcd, 0x93, 0xa5,
  597. 0x8f, 0xb4, 0xbd, 0xb1, 0x00, 0x83, 0x00, 0x70,
  598. 0x00, 0x96,
  599. }, {
  600. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa9, 0xab, 0xa3,
  601. 0xaa, 0xbf, 0xa7, 0xc5, 0xd3, 0xcb, 0x93, 0xa5,
  602. 0x8f, 0xb2, 0xbb, 0xb0, 0x00, 0x86, 0x00, 0x74,
  603. 0x00, 0x9b,
  604. }, {
  605. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb1, 0xb5, 0xab,
  606. 0xab, 0xc0, 0xa9, 0xc7, 0xd4, 0xcc, 0x94, 0xa4,
  607. 0x8f, 0xb1, 0xbb, 0xaf, 0x00, 0x8a, 0x00, 0x77,
  608. 0x00, 0x9e,
  609. }, {
  610. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb2, 0xa7,
  611. 0xae, 0xc2, 0xab, 0xc5, 0xd3, 0xca, 0x93, 0xa4,
  612. 0x8f, 0xb1, 0xba, 0xae, 0x00, 0x8d, 0x00, 0x7b,
  613. 0x00, 0xa2,
  614. }, {
  615. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa9, 0xaf, 0xa3,
  616. 0xb0, 0xc3, 0xae, 0xc4, 0xd1, 0xc8, 0x93, 0xa4,
  617. 0x8f, 0xb1, 0xba, 0xaf, 0x00, 0x8f, 0x00, 0x7d,
  618. 0x00, 0xa5,
  619. }, {
  620. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb4, 0xbd, 0xaf,
  621. 0xae, 0xc1, 0xab, 0xc2, 0xd0, 0xc6, 0x94, 0xa4,
  622. 0x8f, 0xb1, 0xba, 0xaf, 0x00, 0x92, 0x00, 0x80,
  623. 0x00, 0xa8,
  624. }, {
  625. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb0, 0xb9, 0xac,
  626. 0xad, 0xc1, 0xab, 0xc4, 0xd1, 0xc7, 0x95, 0xa4,
  627. 0x90, 0xb0, 0xb9, 0xad, 0x00, 0x95, 0x00, 0x84,
  628. 0x00, 0xac,
  629. }, {
  630. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb6, 0xa7,
  631. 0xaf, 0xc2, 0xae, 0xc5, 0xd1, 0xc7, 0x93, 0xa3,
  632. 0x8e, 0xb0, 0xb9, 0xad, 0x00, 0x98, 0x00, 0x86,
  633. 0x00, 0xaf,
  634. }, {
  635. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb4, 0xbf, 0xaf,
  636. 0xad, 0xc1, 0xab, 0xc3, 0xd0, 0xc6, 0x94, 0xa3,
  637. 0x8f, 0xaf, 0xb8, 0xac, 0x00, 0x9a, 0x00, 0x89,
  638. 0x00, 0xb2,
  639. }, {
  640. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb0, 0xbc, 0xac,
  641. 0xaf, 0xc2, 0xad, 0xc2, 0xcf, 0xc4, 0x94, 0xa3,
  642. 0x90, 0xaf, 0xb8, 0xad, 0x00, 0x9c, 0x00, 0x8b,
  643. 0x00, 0xb5,
  644. }, {
  645. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb9, 0xa7,
  646. 0xb1, 0xc4, 0xaf, 0xc3, 0xcf, 0xc5, 0x94, 0xa3,
  647. 0x8f, 0xae, 0xb7, 0xac, 0x00, 0x9f, 0x00, 0x8e,
  648. 0x00, 0xb8,
  649. }, {
  650. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xb9, 0xa7,
  651. 0xaf, 0xc2, 0xad, 0xc1, 0xce, 0xc3, 0x95, 0xa3,
  652. 0x90, 0xad, 0xb6, 0xab, 0x00, 0xa2, 0x00, 0x91,
  653. 0x00, 0xbb,
  654. }, {
  655. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb1, 0xbe, 0xac,
  656. 0xb1, 0xc4, 0xaf, 0xc1, 0xcd, 0xc1, 0x95, 0xa4,
  657. 0x91, 0xad, 0xb6, 0xab, 0x00, 0xa4, 0x00, 0x93,
  658. 0x00, 0xbd,
  659. }, {
  660. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xbb, 0xa8,
  661. 0xb3, 0xc5, 0xb2, 0xc1, 0xcd, 0xc2, 0x95, 0xa3,
  662. 0x90, 0xad, 0xb6, 0xab, 0x00, 0xa6, 0x00, 0x95,
  663. 0x00, 0xc0,
  664. }, {
  665. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xbb, 0xa8,
  666. 0xb0, 0xc3, 0xaf, 0xc2, 0xce, 0xc2, 0x94, 0xa2,
  667. 0x90, 0xac, 0xb6, 0xab, 0x00, 0xa8, 0x00, 0x98,
  668. 0x00, 0xc3,
  669. }, {
  670. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xa9, 0xb8, 0xa5,
  671. 0xb3, 0xc5, 0xb2, 0xc1, 0xcc, 0xc0, 0x95, 0xa2,
  672. 0x90, 0xad, 0xb6, 0xab, 0x00, 0xaa, 0x00, 0x9a,
  673. 0x00, 0xc5,
  674. }, {
  675. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xb0, 0xc0, 0xac,
  676. 0xb0, 0xc3, 0xaf, 0xc1, 0xcd, 0xc1, 0x95, 0xa2,
  677. 0x90, 0xac, 0xb5, 0xa9, 0x00, 0xac, 0x00, 0x9c,
  678. 0x00, 0xc8,
  679. }, {
  680. 0xfa, 0x01, 0x43, 0x14, 0x45, 0xad, 0xbd, 0xa8,
  681. 0xaf, 0xc2, 0xaf, 0xc1, 0xcc, 0xc0, 0x95, 0xa2,
  682. 0x90, 0xac, 0xb5, 0xaa, 0x00, 0xb1, 0x00, 0xa1,
  683. 0x00, 0xcc,
  684. },
  685. };
  686. static const struct s6e8aa0_variant s6e8aa0_variants[] = {
  687. {
  688. .version = 32,
  689. .gamma_tables = s6e8aa0_gamma_tables_v32,
  690. }, {
  691. .version = 96,
  692. .gamma_tables = s6e8aa0_gamma_tables_v96,
  693. }, {
  694. .version = 142,
  695. .gamma_tables = s6e8aa0_gamma_tables_v142,
  696. }, {
  697. .version = 210,
  698. .gamma_tables = s6e8aa0_gamma_tables_v142,
  699. }
  700. };
  701. static void s6e8aa0_brightness_set(struct s6e8aa0 *ctx)
  702. {
  703. const u8 *gamma;
  704. if (ctx->error)
  705. return;
  706. gamma = ctx->variant->gamma_tables[ctx->brightness];
  707. if (ctx->version >= 142)
  708. s6e8aa0_elvss_nvm_set(ctx);
  709. s6e8aa0_dcs_write(ctx, gamma, GAMMA_TABLE_LEN);
  710. /* update gamma table. */
  711. s6e8aa0_dcs_write_seq_static(ctx, 0xf7, 0x03);
  712. }
  713. static void s6e8aa0_panel_init(struct s6e8aa0 *ctx)
  714. {
  715. s6e8aa0_apply_level_1_key(ctx);
  716. s6e8aa0_apply_level_2_key(ctx);
  717. msleep(20);
  718. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE);
  719. msleep(40);
  720. s6e8aa0_panel_cond_set(ctx);
  721. s6e8aa0_display_condition_set(ctx);
  722. s6e8aa0_brightness_set(ctx);
  723. s6e8aa0_etc_source_control(ctx);
  724. s6e8aa0_etc_pentile_control(ctx);
  725. s6e8aa0_elvss_nvm_set(ctx);
  726. s6e8aa0_etc_power_control(ctx);
  727. s6e8aa0_etc_elvss_control(ctx);
  728. msleep(ctx->init_delay);
  729. }
  730. static void s6e8aa0_set_maximum_return_packet_size(struct s6e8aa0 *ctx,
  731. u16 size)
  732. {
  733. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  734. int ret;
  735. if (ctx->error < 0)
  736. return;
  737. ret = mipi_dsi_set_maximum_return_packet_size(dsi, size);
  738. if (ret < 0) {
  739. dev_err(ctx->dev,
  740. "error %d setting maximum return packet size to %d\n",
  741. ret, size);
  742. ctx->error = ret;
  743. }
  744. }
  745. static void s6e8aa0_read_mtp_id(struct s6e8aa0 *ctx)
  746. {
  747. u8 id[3];
  748. int ret, i;
  749. ret = s6e8aa0_dcs_read(ctx, 0xd1, id, ARRAY_SIZE(id));
  750. if (ret < 0 || ret < ARRAY_SIZE(id) || id[0] == 0x00) {
  751. dev_err(ctx->dev, "read id failed\n");
  752. ctx->error = -EIO;
  753. return;
  754. }
  755. dev_info(ctx->dev, "ID: 0x%2x, 0x%2x, 0x%2x\n", id[0], id[1], id[2]);
  756. for (i = 0; i < ARRAY_SIZE(s6e8aa0_variants); ++i) {
  757. if (id[1] == s6e8aa0_variants[i].version)
  758. break;
  759. }
  760. if (i >= ARRAY_SIZE(s6e8aa0_variants)) {
  761. dev_err(ctx->dev, "unsupported display version %d\n", id[1]);
  762. ctx->error = -EINVAL;
  763. return;
  764. }
  765. ctx->variant = &s6e8aa0_variants[i];
  766. ctx->version = id[1];
  767. ctx->id = id[2];
  768. }
  769. static void s6e8aa0_set_sequence(struct s6e8aa0 *ctx)
  770. {
  771. s6e8aa0_set_maximum_return_packet_size(ctx, 3);
  772. s6e8aa0_read_mtp_id(ctx);
  773. s6e8aa0_panel_init(ctx);
  774. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_ON);
  775. }
  776. static int s6e8aa0_power_on(struct s6e8aa0 *ctx)
  777. {
  778. int ret;
  779. ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
  780. if (ret < 0)
  781. return ret;
  782. msleep(ctx->power_on_delay);
  783. gpiod_set_value(ctx->reset_gpio, 0);
  784. usleep_range(10000, 11000);
  785. gpiod_set_value(ctx->reset_gpio, 1);
  786. msleep(ctx->reset_delay);
  787. return 0;
  788. }
  789. static int s6e8aa0_power_off(struct s6e8aa0 *ctx)
  790. {
  791. return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
  792. }
  793. static int s6e8aa0_disable(struct drm_panel *panel)
  794. {
  795. return 0;
  796. }
  797. static int s6e8aa0_unprepare(struct drm_panel *panel)
  798. {
  799. struct s6e8aa0 *ctx = panel_to_s6e8aa0(panel);
  800. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE);
  801. s6e8aa0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF);
  802. msleep(40);
  803. s6e8aa0_clear_error(ctx);
  804. return s6e8aa0_power_off(ctx);
  805. }
  806. static int s6e8aa0_prepare(struct drm_panel *panel)
  807. {
  808. struct s6e8aa0 *ctx = panel_to_s6e8aa0(panel);
  809. int ret;
  810. ret = s6e8aa0_power_on(ctx);
  811. if (ret < 0)
  812. return ret;
  813. s6e8aa0_set_sequence(ctx);
  814. ret = ctx->error;
  815. if (ret < 0)
  816. s6e8aa0_unprepare(panel);
  817. return ret;
  818. }
  819. static int s6e8aa0_enable(struct drm_panel *panel)
  820. {
  821. return 0;
  822. }
  823. static int s6e8aa0_get_modes(struct drm_panel *panel,
  824. struct drm_connector *connector)
  825. {
  826. struct s6e8aa0 *ctx = panel_to_s6e8aa0(panel);
  827. struct drm_display_mode *mode;
  828. mode = drm_mode_create(connector->dev);
  829. if (!mode) {
  830. dev_err(panel->dev, "failed to create a new display mode\n");
  831. return 0;
  832. }
  833. drm_display_mode_from_videomode(&ctx->vm, mode);
  834. mode->width_mm = ctx->width_mm;
  835. mode->height_mm = ctx->height_mm;
  836. connector->display_info.width_mm = mode->width_mm;
  837. connector->display_info.height_mm = mode->height_mm;
  838. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  839. drm_mode_probed_add(connector, mode);
  840. return 1;
  841. }
  842. static const struct drm_panel_funcs s6e8aa0_drm_funcs = {
  843. .disable = s6e8aa0_disable,
  844. .unprepare = s6e8aa0_unprepare,
  845. .prepare = s6e8aa0_prepare,
  846. .enable = s6e8aa0_enable,
  847. .get_modes = s6e8aa0_get_modes,
  848. };
  849. static int s6e8aa0_parse_dt(struct s6e8aa0 *ctx)
  850. {
  851. struct device *dev = ctx->dev;
  852. struct device_node *np = dev->of_node;
  853. int ret;
  854. ret = of_get_videomode(np, &ctx->vm, 0);
  855. if (ret < 0)
  856. return ret;
  857. of_property_read_u32(np, "power-on-delay", &ctx->power_on_delay);
  858. of_property_read_u32(np, "reset-delay", &ctx->reset_delay);
  859. of_property_read_u32(np, "init-delay", &ctx->init_delay);
  860. of_property_read_u32(np, "panel-width-mm", &ctx->width_mm);
  861. of_property_read_u32(np, "panel-height-mm", &ctx->height_mm);
  862. ctx->flip_horizontal = of_property_read_bool(np, "flip-horizontal");
  863. ctx->flip_vertical = of_property_read_bool(np, "flip-vertical");
  864. return 0;
  865. }
  866. static int s6e8aa0_probe(struct mipi_dsi_device *dsi)
  867. {
  868. struct device *dev = &dsi->dev;
  869. struct s6e8aa0 *ctx;
  870. int ret;
  871. ctx = devm_kzalloc(dev, sizeof(struct s6e8aa0), GFP_KERNEL);
  872. if (!ctx)
  873. return -ENOMEM;
  874. mipi_dsi_set_drvdata(dsi, ctx);
  875. ctx->dev = dev;
  876. dsi->lanes = 4;
  877. dsi->format = MIPI_DSI_FMT_RGB888;
  878. dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST
  879. | MIPI_DSI_MODE_VIDEO_HFP | MIPI_DSI_MODE_VIDEO_HBP
  880. | MIPI_DSI_MODE_VIDEO_HSA | MIPI_DSI_MODE_EOT_PACKET
  881. | MIPI_DSI_MODE_VSYNC_FLUSH | MIPI_DSI_MODE_VIDEO_AUTO_VERT;
  882. ret = s6e8aa0_parse_dt(ctx);
  883. if (ret < 0)
  884. return ret;
  885. ctx->supplies[0].supply = "vdd3";
  886. ctx->supplies[1].supply = "vci";
  887. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
  888. ctx->supplies);
  889. if (ret < 0) {
  890. dev_err(dev, "failed to get regulators: %d\n", ret);
  891. return ret;
  892. }
  893. ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
  894. if (IS_ERR(ctx->reset_gpio)) {
  895. dev_err(dev, "cannot get reset-gpios %ld\n",
  896. PTR_ERR(ctx->reset_gpio));
  897. return PTR_ERR(ctx->reset_gpio);
  898. }
  899. ctx->brightness = GAMMA_LEVEL_NUM - 1;
  900. drm_panel_init(&ctx->panel, dev, &s6e8aa0_drm_funcs,
  901. DRM_MODE_CONNECTOR_DSI);
  902. drm_panel_add(&ctx->panel);
  903. ret = mipi_dsi_attach(dsi);
  904. if (ret < 0)
  905. drm_panel_remove(&ctx->panel);
  906. return ret;
  907. }
  908. static int s6e8aa0_remove(struct mipi_dsi_device *dsi)
  909. {
  910. struct s6e8aa0 *ctx = mipi_dsi_get_drvdata(dsi);
  911. mipi_dsi_detach(dsi);
  912. drm_panel_remove(&ctx->panel);
  913. return 0;
  914. }
  915. static const struct of_device_id s6e8aa0_of_match[] = {
  916. { .compatible = "samsung,s6e8aa0" },
  917. { }
  918. };
  919. MODULE_DEVICE_TABLE(of, s6e8aa0_of_match);
  920. static struct mipi_dsi_driver s6e8aa0_driver = {
  921. .probe = s6e8aa0_probe,
  922. .remove = s6e8aa0_remove,
  923. .driver = {
  924. .name = "panel-samsung-s6e8aa0",
  925. .of_match_table = s6e8aa0_of_match,
  926. },
  927. };
  928. module_mipi_dsi_driver(s6e8aa0_driver);
  929. MODULE_AUTHOR("Donghwa Lee <dh09.lee@samsung.com>");
  930. MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
  931. MODULE_AUTHOR("Joongmock Shin <jmock.shin@samsung.com>");
  932. MODULE_AUTHOR("Eunchul Kim <chulspro.kim@samsung.com>");
  933. MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
  934. MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
  935. MODULE_DESCRIPTION("MIPI-DSI based s6e8aa0 AMOLED LCD Panel Driver");
  936. MODULE_LICENSE("GPL v2");