panel-samsung-s6e63m0.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * S6E63M0 AMOLED LCD drm_panel driver.
  4. *
  5. * Copyright (C) 2019 Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
  6. * Derived from drivers/gpu/drm/panel-samsung-ld9040.c
  7. *
  8. * Andrzej Hajda <a.hajda@samsung.com>
  9. */
  10. #include <drm/drm_modes.h>
  11. #include <drm/drm_panel.h>
  12. #include <linux/backlight.h>
  13. #include <linux/delay.h>
  14. #include <linux/gpio/consumer.h>
  15. #include <linux/module.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <video/mipi_display.h>
  18. #include "panel-samsung-s6e63m0.h"
  19. /* Manufacturer Command Set */
  20. #define MCS_ELVSS_ON 0xb1
  21. #define MCS_MIECTL1 0xc0
  22. #define MCS_BCMODE 0xc1
  23. #define MCS_ERROR_CHECK 0xd5
  24. #define MCS_READ_ID1 0xda
  25. #define MCS_READ_ID2 0xdb
  26. #define MCS_READ_ID3 0xdc
  27. #define MCS_LEVEL_2_KEY 0xf0
  28. #define MCS_MTP_KEY 0xf1
  29. #define MCS_DISCTL 0xf2
  30. #define MCS_SRCCTL 0xf6
  31. #define MCS_IFCTL 0xf7
  32. #define MCS_PANELCTL 0xF8
  33. #define MCS_PGAMMACTL 0xfa
  34. #define S6E63M0_LCD_ID_VALUE_M2 0xA4
  35. #define S6E63M0_LCD_ID_VALUE_SM2 0xB4
  36. #define S6E63M0_LCD_ID_VALUE_SM2_1 0xB6
  37. #define NUM_GAMMA_LEVELS 11
  38. #define GAMMA_TABLE_COUNT 23
  39. #define MAX_BRIGHTNESS (NUM_GAMMA_LEVELS - 1)
  40. /* array of gamma tables for gamma value 2.2 */
  41. static u8 const s6e63m0_gamma_22[NUM_GAMMA_LEVELS][GAMMA_TABLE_COUNT] = {
  42. { MCS_PGAMMACTL, 0x00,
  43. 0x18, 0x08, 0x24, 0x78, 0xEC, 0x3D, 0xC8,
  44. 0xC2, 0xB6, 0xC4, 0xC7, 0xB6, 0xD5, 0xD7,
  45. 0xCC, 0x00, 0x39, 0x00, 0x36, 0x00, 0x51 },
  46. { MCS_PGAMMACTL, 0x00,
  47. 0x18, 0x08, 0x24, 0x73, 0x4A, 0x3D, 0xC0,
  48. 0xC2, 0xB1, 0xBB, 0xBE, 0xAC, 0xCE, 0xCF,
  49. 0xC5, 0x00, 0x5D, 0x00, 0x5E, 0x00, 0x82 },
  50. { MCS_PGAMMACTL, 0x00,
  51. 0x18, 0x08, 0x24, 0x70, 0x51, 0x3E, 0xBF,
  52. 0xC1, 0xAF, 0xB9, 0xBC, 0xAB, 0xCC, 0xCC,
  53. 0xC2, 0x00, 0x65, 0x00, 0x67, 0x00, 0x8D },
  54. { MCS_PGAMMACTL, 0x00,
  55. 0x18, 0x08, 0x24, 0x6C, 0x54, 0x3A, 0xBC,
  56. 0xBF, 0xAC, 0xB7, 0xBB, 0xA9, 0xC9, 0xC9,
  57. 0xBE, 0x00, 0x71, 0x00, 0x73, 0x00, 0x9E },
  58. { MCS_PGAMMACTL, 0x00,
  59. 0x18, 0x08, 0x24, 0x69, 0x54, 0x37, 0xBB,
  60. 0xBE, 0xAC, 0xB4, 0xB7, 0xA6, 0xC7, 0xC8,
  61. 0xBC, 0x00, 0x7B, 0x00, 0x7E, 0x00, 0xAB },
  62. { MCS_PGAMMACTL, 0x00,
  63. 0x18, 0x08, 0x24, 0x66, 0x55, 0x34, 0xBA,
  64. 0xBD, 0xAB, 0xB1, 0xB5, 0xA3, 0xC5, 0xC6,
  65. 0xB9, 0x00, 0x85, 0x00, 0x88, 0x00, 0xBA },
  66. { MCS_PGAMMACTL, 0x00,
  67. 0x18, 0x08, 0x24, 0x63, 0x53, 0x31, 0xB8,
  68. 0xBC, 0xA9, 0xB0, 0xB5, 0xA2, 0xC4, 0xC4,
  69. 0xB8, 0x00, 0x8B, 0x00, 0x8E, 0x00, 0xC2 },
  70. { MCS_PGAMMACTL, 0x00,
  71. 0x18, 0x08, 0x24, 0x62, 0x54, 0x30, 0xB9,
  72. 0xBB, 0xA9, 0xB0, 0xB3, 0xA1, 0xC1, 0xC3,
  73. 0xB7, 0x00, 0x91, 0x00, 0x95, 0x00, 0xDA },
  74. { MCS_PGAMMACTL, 0x00,
  75. 0x18, 0x08, 0x24, 0x66, 0x58, 0x34, 0xB6,
  76. 0xBA, 0xA7, 0xAF, 0xB3, 0xA0, 0xC1, 0xC2,
  77. 0xB7, 0x00, 0x97, 0x00, 0x9A, 0x00, 0xD1 },
  78. { MCS_PGAMMACTL, 0x00,
  79. 0x18, 0x08, 0x24, 0x64, 0x56, 0x33, 0xB6,
  80. 0xBA, 0xA8, 0xAC, 0xB1, 0x9D, 0xC1, 0xC1,
  81. 0xB7, 0x00, 0x9C, 0x00, 0x9F, 0x00, 0xD6 },
  82. { MCS_PGAMMACTL, 0x00,
  83. 0x18, 0x08, 0x24, 0x5f, 0x50, 0x2d, 0xB6,
  84. 0xB9, 0xA7, 0xAd, 0xB1, 0x9f, 0xbe, 0xC0,
  85. 0xB5, 0x00, 0xa0, 0x00, 0xa4, 0x00, 0xdb },
  86. };
  87. struct s6e63m0 {
  88. struct device *dev;
  89. int (*dcs_read)(struct device *dev, const u8 cmd, u8 *val);
  90. int (*dcs_write)(struct device *dev, const u8 *data, size_t len);
  91. struct drm_panel panel;
  92. struct backlight_device *bl_dev;
  93. u8 lcd_type;
  94. struct regulator_bulk_data supplies[2];
  95. struct gpio_desc *reset_gpio;
  96. bool prepared;
  97. bool enabled;
  98. /*
  99. * This field is tested by functions directly accessing bus before
  100. * transfer, transfer is skipped if it is set. In case of transfer
  101. * failure or unexpected response the field is set to error value.
  102. * Such construct allows to eliminate many checks in higher level
  103. * functions.
  104. */
  105. int error;
  106. };
  107. static const struct drm_display_mode default_mode = {
  108. .clock = 25628,
  109. .hdisplay = 480,
  110. .hsync_start = 480 + 16,
  111. .hsync_end = 480 + 16 + 2,
  112. .htotal = 480 + 16 + 2 + 16,
  113. .vdisplay = 800,
  114. .vsync_start = 800 + 28,
  115. .vsync_end = 800 + 28 + 2,
  116. .vtotal = 800 + 28 + 2 + 1,
  117. .width_mm = 53,
  118. .height_mm = 89,
  119. .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
  120. };
  121. static inline struct s6e63m0 *panel_to_s6e63m0(struct drm_panel *panel)
  122. {
  123. return container_of(panel, struct s6e63m0, panel);
  124. }
  125. static int s6e63m0_clear_error(struct s6e63m0 *ctx)
  126. {
  127. int ret = ctx->error;
  128. ctx->error = 0;
  129. return ret;
  130. }
  131. static void s6e63m0_dcs_read(struct s6e63m0 *ctx, const u8 cmd, u8 *data)
  132. {
  133. if (ctx->error < 0)
  134. return;
  135. ctx->error = ctx->dcs_read(ctx->dev, cmd, data);
  136. }
  137. static void s6e63m0_dcs_write(struct s6e63m0 *ctx, const u8 *data, size_t len)
  138. {
  139. if (ctx->error < 0 || len == 0)
  140. return;
  141. ctx->error = ctx->dcs_write(ctx->dev, data, len);
  142. }
  143. #define s6e63m0_dcs_write_seq_static(ctx, seq ...) \
  144. ({ \
  145. static const u8 d[] = { seq }; \
  146. s6e63m0_dcs_write(ctx, d, ARRAY_SIZE(d)); \
  147. })
  148. static int s6e63m0_check_lcd_type(struct s6e63m0 *ctx)
  149. {
  150. u8 id1, id2, id3;
  151. int ret;
  152. s6e63m0_dcs_read(ctx, MCS_READ_ID1, &id1);
  153. s6e63m0_dcs_read(ctx, MCS_READ_ID2, &id2);
  154. s6e63m0_dcs_read(ctx, MCS_READ_ID3, &id3);
  155. ret = s6e63m0_clear_error(ctx);
  156. if (ret) {
  157. dev_err(ctx->dev, "error checking LCD type (%d)\n", ret);
  158. ctx->lcd_type = 0x00;
  159. return ret;
  160. }
  161. dev_info(ctx->dev, "MTP ID: %02x %02x %02x\n", id1, id2, id3);
  162. /* We attempt to detect what panel is mounted on the controller */
  163. switch (id2) {
  164. case S6E63M0_LCD_ID_VALUE_M2:
  165. dev_info(ctx->dev, "detected LCD panel AMS397GE MIPI M2\n");
  166. break;
  167. case S6E63M0_LCD_ID_VALUE_SM2:
  168. case S6E63M0_LCD_ID_VALUE_SM2_1:
  169. dev_info(ctx->dev, "detected LCD panel AMS397GE MIPI SM2\n");
  170. break;
  171. default:
  172. dev_info(ctx->dev, "unknown LCD panel type %02x\n", id2);
  173. break;
  174. }
  175. ctx->lcd_type = id2;
  176. return 0;
  177. }
  178. static void s6e63m0_init(struct s6e63m0 *ctx)
  179. {
  180. s6e63m0_dcs_write_seq_static(ctx, MCS_PANELCTL,
  181. 0x01, 0x27, 0x27, 0x07, 0x07, 0x54, 0x9f,
  182. 0x63, 0x86, 0x1a, 0x33, 0x0d, 0x00, 0x00);
  183. s6e63m0_dcs_write_seq_static(ctx, MCS_DISCTL,
  184. 0x02, 0x03, 0x1c, 0x10, 0x10);
  185. s6e63m0_dcs_write_seq_static(ctx, MCS_IFCTL,
  186. 0x03, 0x00, 0x00);
  187. s6e63m0_dcs_write_seq_static(ctx, MCS_PGAMMACTL,
  188. 0x00, 0x18, 0x08, 0x24, 0x64, 0x56, 0x33,
  189. 0xb6, 0xba, 0xa8, 0xac, 0xb1, 0x9d, 0xc1,
  190. 0xc1, 0xb7, 0x00, 0x9c, 0x00, 0x9f, 0x00,
  191. 0xd6);
  192. s6e63m0_dcs_write_seq_static(ctx, MCS_PGAMMACTL,
  193. 0x01);
  194. s6e63m0_dcs_write_seq_static(ctx, MCS_SRCCTL,
  195. 0x00, 0x8c, 0x07);
  196. s6e63m0_dcs_write_seq_static(ctx, 0xb3,
  197. 0xc);
  198. s6e63m0_dcs_write_seq_static(ctx, 0xb5,
  199. 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17,
  200. 0x13, 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b,
  201. 0x1a, 0x17, 0x2b, 0x26, 0x22, 0x20, 0x3a,
  202. 0x34, 0x30, 0x2c, 0x29, 0x26, 0x25, 0x23,
  203. 0x21, 0x20, 0x1e, 0x1e);
  204. s6e63m0_dcs_write_seq_static(ctx, 0xb6,
  205. 0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44,
  206. 0x44, 0x55, 0x55, 0x66, 0x66, 0x66, 0x66,
  207. 0x66, 0x66);
  208. s6e63m0_dcs_write_seq_static(ctx, 0xb7,
  209. 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17,
  210. 0x13, 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b,
  211. 0x1a, 0x17, 0x2b, 0x26, 0x22, 0x20, 0x3a,
  212. 0x34, 0x30, 0x2c, 0x29, 0x26, 0x25, 0x23,
  213. 0x21, 0x20, 0x1e, 0x1e, 0x00, 0x00, 0x11,
  214. 0x22, 0x33, 0x44, 0x44, 0x44, 0x55, 0x55,
  215. 0x66, 0x66, 0x66, 0x66, 0x66, 0x66);
  216. s6e63m0_dcs_write_seq_static(ctx, 0xb9,
  217. 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17,
  218. 0x13, 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b,
  219. 0x1a, 0x17, 0x2b, 0x26, 0x22, 0x20, 0x3a,
  220. 0x34, 0x30, 0x2c, 0x29, 0x26, 0x25, 0x23,
  221. 0x21, 0x20, 0x1e, 0x1e);
  222. s6e63m0_dcs_write_seq_static(ctx, 0xba,
  223. 0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44,
  224. 0x44, 0x55, 0x55, 0x66, 0x66, 0x66, 0x66,
  225. 0x66, 0x66);
  226. s6e63m0_dcs_write_seq_static(ctx, MCS_BCMODE,
  227. 0x4d, 0x96, 0x1d, 0x00, 0x00, 0x01, 0xdf,
  228. 0x00, 0x00, 0x03, 0x1f, 0x00, 0x00, 0x00,
  229. 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x06,
  230. 0x09, 0x0d, 0x0f, 0x12, 0x15, 0x18);
  231. s6e63m0_dcs_write_seq_static(ctx, 0xb2,
  232. 0x10, 0x10, 0x0b, 0x05);
  233. s6e63m0_dcs_write_seq_static(ctx, MCS_MIECTL1,
  234. 0x01);
  235. s6e63m0_dcs_write_seq_static(ctx, MCS_ELVSS_ON,
  236. 0x0b);
  237. }
  238. static int s6e63m0_power_on(struct s6e63m0 *ctx)
  239. {
  240. int ret;
  241. ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
  242. if (ret < 0)
  243. return ret;
  244. msleep(25);
  245. /* Be sure to send a reset pulse */
  246. gpiod_set_value(ctx->reset_gpio, 1);
  247. msleep(5);
  248. gpiod_set_value(ctx->reset_gpio, 0);
  249. msleep(120);
  250. return 0;
  251. }
  252. static int s6e63m0_power_off(struct s6e63m0 *ctx)
  253. {
  254. int ret;
  255. gpiod_set_value(ctx->reset_gpio, 1);
  256. msleep(120);
  257. ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
  258. if (ret < 0)
  259. return ret;
  260. return 0;
  261. }
  262. static int s6e63m0_disable(struct drm_panel *panel)
  263. {
  264. struct s6e63m0 *ctx = panel_to_s6e63m0(panel);
  265. if (!ctx->enabled)
  266. return 0;
  267. backlight_disable(ctx->bl_dev);
  268. s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_OFF);
  269. msleep(10);
  270. s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_ENTER_SLEEP_MODE);
  271. msleep(120);
  272. ctx->enabled = false;
  273. return 0;
  274. }
  275. static int s6e63m0_unprepare(struct drm_panel *panel)
  276. {
  277. struct s6e63m0 *ctx = panel_to_s6e63m0(panel);
  278. int ret;
  279. if (!ctx->prepared)
  280. return 0;
  281. s6e63m0_clear_error(ctx);
  282. ret = s6e63m0_power_off(ctx);
  283. if (ret < 0)
  284. return ret;
  285. ctx->prepared = false;
  286. return 0;
  287. }
  288. static int s6e63m0_prepare(struct drm_panel *panel)
  289. {
  290. struct s6e63m0 *ctx = panel_to_s6e63m0(panel);
  291. int ret;
  292. if (ctx->prepared)
  293. return 0;
  294. ret = s6e63m0_power_on(ctx);
  295. if (ret < 0)
  296. return ret;
  297. /* Magic to unlock level 2 control of the display */
  298. s6e63m0_dcs_write_seq_static(ctx, MCS_LEVEL_2_KEY, 0x5a, 0x5a);
  299. /* Magic to unlock MTP reading */
  300. s6e63m0_dcs_write_seq_static(ctx, MCS_MTP_KEY, 0x5a, 0x5a);
  301. ret = s6e63m0_check_lcd_type(ctx);
  302. if (ret < 0)
  303. return ret;
  304. s6e63m0_init(ctx);
  305. ret = s6e63m0_clear_error(ctx);
  306. if (ret < 0)
  307. s6e63m0_unprepare(panel);
  308. ctx->prepared = true;
  309. return ret;
  310. }
  311. static int s6e63m0_enable(struct drm_panel *panel)
  312. {
  313. struct s6e63m0 *ctx = panel_to_s6e63m0(panel);
  314. if (ctx->enabled)
  315. return 0;
  316. s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_EXIT_SLEEP_MODE);
  317. msleep(120);
  318. s6e63m0_dcs_write_seq_static(ctx, MIPI_DCS_SET_DISPLAY_ON);
  319. msleep(10);
  320. s6e63m0_dcs_write_seq_static(ctx, MCS_ERROR_CHECK,
  321. 0xE7, 0x14, 0x60, 0x17, 0x0A, 0x49, 0xC3,
  322. 0x8F, 0x19, 0x64, 0x91, 0x84, 0x76, 0x20,
  323. 0x0F, 0x00);
  324. backlight_enable(ctx->bl_dev);
  325. ctx->enabled = true;
  326. return 0;
  327. }
  328. static int s6e63m0_get_modes(struct drm_panel *panel,
  329. struct drm_connector *connector)
  330. {
  331. struct drm_display_mode *mode;
  332. mode = drm_mode_duplicate(connector->dev, &default_mode);
  333. if (!mode) {
  334. dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
  335. default_mode.hdisplay, default_mode.vdisplay,
  336. drm_mode_vrefresh(&default_mode));
  337. return -ENOMEM;
  338. }
  339. drm_mode_set_name(mode);
  340. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  341. drm_mode_probed_add(connector, mode);
  342. return 1;
  343. }
  344. static const struct drm_panel_funcs s6e63m0_drm_funcs = {
  345. .disable = s6e63m0_disable,
  346. .unprepare = s6e63m0_unprepare,
  347. .prepare = s6e63m0_prepare,
  348. .enable = s6e63m0_enable,
  349. .get_modes = s6e63m0_get_modes,
  350. };
  351. static int s6e63m0_set_brightness(struct backlight_device *bd)
  352. {
  353. struct s6e63m0 *ctx = bl_get_data(bd);
  354. int brightness = bd->props.brightness;
  355. /* disable and set new gamma */
  356. s6e63m0_dcs_write(ctx, s6e63m0_gamma_22[brightness],
  357. ARRAY_SIZE(s6e63m0_gamma_22[brightness]));
  358. /* update gamma table. */
  359. s6e63m0_dcs_write_seq_static(ctx, MCS_PGAMMACTL, 0x01);
  360. return s6e63m0_clear_error(ctx);
  361. }
  362. static const struct backlight_ops s6e63m0_backlight_ops = {
  363. .update_status = s6e63m0_set_brightness,
  364. };
  365. static int s6e63m0_backlight_register(struct s6e63m0 *ctx)
  366. {
  367. struct backlight_properties props = {
  368. .type = BACKLIGHT_RAW,
  369. .brightness = MAX_BRIGHTNESS,
  370. .max_brightness = MAX_BRIGHTNESS
  371. };
  372. struct device *dev = ctx->dev;
  373. int ret = 0;
  374. ctx->bl_dev = devm_backlight_device_register(dev, "panel", dev, ctx,
  375. &s6e63m0_backlight_ops,
  376. &props);
  377. if (IS_ERR(ctx->bl_dev)) {
  378. ret = PTR_ERR(ctx->bl_dev);
  379. dev_err(dev, "error registering backlight device (%d)\n", ret);
  380. }
  381. return ret;
  382. }
  383. int s6e63m0_probe(struct device *dev,
  384. int (*dcs_read)(struct device *dev, const u8 cmd, u8 *val),
  385. int (*dcs_write)(struct device *dev, const u8 *data, size_t len),
  386. bool dsi_mode)
  387. {
  388. struct s6e63m0 *ctx;
  389. int ret;
  390. ctx = devm_kzalloc(dev, sizeof(struct s6e63m0), GFP_KERNEL);
  391. if (!ctx)
  392. return -ENOMEM;
  393. ctx->dcs_read = dcs_read;
  394. ctx->dcs_write = dcs_write;
  395. dev_set_drvdata(dev, ctx);
  396. ctx->dev = dev;
  397. ctx->enabled = false;
  398. ctx->prepared = false;
  399. ctx->supplies[0].supply = "vdd3";
  400. ctx->supplies[1].supply = "vci";
  401. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
  402. ctx->supplies);
  403. if (ret < 0) {
  404. dev_err(dev, "failed to get regulators: %d\n", ret);
  405. return ret;
  406. }
  407. ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
  408. if (IS_ERR(ctx->reset_gpio)) {
  409. dev_err(dev, "cannot get reset-gpios %ld\n", PTR_ERR(ctx->reset_gpio));
  410. return PTR_ERR(ctx->reset_gpio);
  411. }
  412. drm_panel_init(&ctx->panel, dev, &s6e63m0_drm_funcs,
  413. dsi_mode ? DRM_MODE_CONNECTOR_DSI :
  414. DRM_MODE_CONNECTOR_DPI);
  415. ret = s6e63m0_backlight_register(ctx);
  416. if (ret < 0)
  417. return ret;
  418. drm_panel_add(&ctx->panel);
  419. return 0;
  420. }
  421. EXPORT_SYMBOL_GPL(s6e63m0_probe);
  422. int s6e63m0_remove(struct device *dev)
  423. {
  424. struct s6e63m0 *ctx = dev_get_drvdata(dev);
  425. drm_panel_remove(&ctx->panel);
  426. return 0;
  427. }
  428. EXPORT_SYMBOL_GPL(s6e63m0_remove);
  429. MODULE_AUTHOR("Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>");
  430. MODULE_DESCRIPTION("s6e63m0 LCD Driver");
  431. MODULE_LICENSE("GPL v2");