panel-raydium-rm68200.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2017
  4. *
  5. * Authors: Philippe Cornu <philippe.cornu@st.com>
  6. * Yannick Fertre <yannick.fertre@st.com>
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/mod_devicetable.h>
  11. #include <linux/module.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <video/mipi_display.h>
  14. #include <drm/drm_mipi_dsi.h>
  15. #include <drm/drm_modes.h>
  16. #include <drm/drm_panel.h>
  17. /*** Manufacturer Command Set ***/
  18. #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
  19. #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
  20. #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  21. #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  22. #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  23. #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  24. /* CMD2 P0 commands (Display Options and Power) */
  25. #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
  26. #define MCS_SGOPCTR 0x16 /* Source Bias Current */
  27. #define MCS_SDCTR 0x1A /* Source Output Delay Time */
  28. #define MCS_INVCTR 0x1B /* Inversion Type */
  29. #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
  30. #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
  31. #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
  32. #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
  33. #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
  34. #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
  35. #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
  36. #define MCS_SETVGN 0x52 /* VG M/S N Control */
  37. #define MCS_SETVGP 0x54 /* VG M/S P Control */
  38. #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
  39. /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  40. #define GOA_VSTV1 0x00
  41. #define GOA_VSTV2 0x07
  42. #define GOA_VCLK1 0x0E
  43. #define GOA_VCLK2 0x17
  44. #define GOA_VCLK_OPT1 0x20
  45. #define GOA_BICLK1 0x2A
  46. #define GOA_BICLK2 0x37
  47. #define GOA_BICLK3 0x44
  48. #define GOA_BICLK4 0x4F
  49. #define GOA_BICLK_OPT1 0x5B
  50. #define GOA_BICLK_OPT2 0x60
  51. #define MCS_GOA_GPO1 0x6D
  52. #define MCS_GOA_GPO2 0x71
  53. #define MCS_GOA_EQ 0x74
  54. #define MCS_GOA_CLK_GALLON 0x7C
  55. #define MCS_GOA_FS_SEL0 0x7E
  56. #define MCS_GOA_FS_SEL1 0x87
  57. #define MCS_GOA_FS_SEL2 0x91
  58. #define MCS_GOA_FS_SEL3 0x9B
  59. #define MCS_GOA_BS_SEL0 0xAC
  60. #define MCS_GOA_BS_SEL1 0xB5
  61. #define MCS_GOA_BS_SEL2 0xBF
  62. #define MCS_GOA_BS_SEL3 0xC9
  63. #define MCS_GOA_BS_SEL4 0xD3
  64. /* CMD2 P3 commands (Gamma) */
  65. #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
  66. #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
  67. struct rm68200 {
  68. struct device *dev;
  69. struct drm_panel panel;
  70. struct gpio_desc *reset_gpio;
  71. struct regulator *supply;
  72. bool prepared;
  73. bool enabled;
  74. };
  75. static const struct drm_display_mode default_mode = {
  76. .clock = 52582,
  77. .hdisplay = 720,
  78. .hsync_start = 720 + 38,
  79. .hsync_end = 720 + 38 + 8,
  80. .htotal = 720 + 38 + 8 + 38,
  81. .vdisplay = 1280,
  82. .vsync_start = 1280 + 12,
  83. .vsync_end = 1280 + 12 + 4,
  84. .vtotal = 1280 + 12 + 4 + 12,
  85. .flags = 0,
  86. .width_mm = 68,
  87. .height_mm = 122,
  88. };
  89. static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
  90. {
  91. return container_of(panel, struct rm68200, panel);
  92. }
  93. static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
  94. size_t len)
  95. {
  96. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  97. int err;
  98. err = mipi_dsi_dcs_write_buffer(dsi, data, len);
  99. if (err < 0)
  100. dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
  101. }
  102. static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
  103. {
  104. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  105. int err;
  106. err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
  107. if (err < 0)
  108. dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err);
  109. }
  110. #define dcs_write_seq(ctx, seq...) \
  111. ({ \
  112. static const u8 d[] = { seq }; \
  113. \
  114. rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
  115. })
  116. /*
  117. * This panel is not able to auto-increment all cmd addresses so for some of
  118. * them, we need to send them one by one...
  119. */
  120. #define dcs_write_cmd_seq(ctx, cmd, seq...) \
  121. ({ \
  122. static const u8 d[] = { seq }; \
  123. unsigned int i; \
  124. \
  125. for (i = 0; i < ARRAY_SIZE(d) ; i++) \
  126. rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
  127. })
  128. static void rm68200_init_sequence(struct rm68200 *ctx)
  129. {
  130. /* Enter CMD2 with page 0 */
  131. dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
  132. dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
  133. dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
  134. dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
  135. dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
  136. dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
  137. dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
  138. dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
  139. dcs_write_seq(ctx, MCS_INVCTR, 0x00);
  140. dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
  141. dcs_write_seq(ctx, MCS_SDCTR, 0x06);
  142. dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
  143. dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
  144. dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
  145. dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
  146. dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
  147. dcs_write_seq(ctx, GOA_VSTV1, 0x05);
  148. dcs_write_seq(ctx, 0x02, 0x0B);
  149. dcs_write_seq(ctx, 0x03, 0x0F);
  150. dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
  151. dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
  152. 0x50);
  153. dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
  154. 0x00, 0x85, 0x08);
  155. dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
  156. 0x00, 0x85, 0x08);
  157. dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  158. 0x00, 0x00, 0x00, 0x00);
  159. dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
  160. dcs_write_seq(ctx, 0x2D, 0x01);
  161. dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
  162. 0x00);
  163. dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
  164. dcs_write_seq(ctx, 0x3D, 0x40);
  165. dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
  166. dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  167. 0x00, 0x00, 0x00, 0x00, 0x00);
  168. dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  169. 0x00, 0x00);
  170. dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
  171. dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
  172. dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  173. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  174. dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
  175. dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
  176. dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
  177. 0x00, 0x00);
  178. dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
  179. dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
  180. 0x16, 0x12, 0x08, 0x3F);
  181. dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
  182. 0x0A, 0x0E, 0x3F, 0x3F, 0x00);
  183. dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
  184. 0x05, 0x01, 0x3F, 0x3F, 0x0F);
  185. dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
  186. 0x3F);
  187. dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
  188. dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
  189. dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
  190. 0x15, 0x11, 0x0F, 0x3F);
  191. dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
  192. 0x0D, 0x09, 0x3F, 0x3F, 0x07);
  193. dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
  194. 0x02, 0x06, 0x3F, 0x3F, 0x08);
  195. dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
  196. 0x3F, 0x3F, 0x0E, 0x10, 0x14);
  197. dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
  198. dcs_write_seq(ctx, 0xDC, 0x02);
  199. dcs_write_seq(ctx, 0xDE, 0x12);
  200. dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
  201. dcs_write_seq(ctx, 0x01, 0x75);
  202. dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
  203. dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
  204. 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
  205. 0x12, 0x0C, 0x00);
  206. dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
  207. 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
  208. 0x12, 0x0C, 0x00);
  209. /* Exit CMD2 */
  210. dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
  211. }
  212. static int rm68200_disable(struct drm_panel *panel)
  213. {
  214. struct rm68200 *ctx = panel_to_rm68200(panel);
  215. if (!ctx->enabled)
  216. return 0;
  217. ctx->enabled = false;
  218. return 0;
  219. }
  220. static int rm68200_unprepare(struct drm_panel *panel)
  221. {
  222. struct rm68200 *ctx = panel_to_rm68200(panel);
  223. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  224. int ret;
  225. if (!ctx->prepared)
  226. return 0;
  227. ret = mipi_dsi_dcs_set_display_off(dsi);
  228. if (ret)
  229. dev_warn(panel->dev, "failed to set display off: %d\n", ret);
  230. ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
  231. if (ret)
  232. dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
  233. msleep(120);
  234. if (ctx->reset_gpio) {
  235. gpiod_set_value_cansleep(ctx->reset_gpio, 1);
  236. msleep(20);
  237. }
  238. regulator_disable(ctx->supply);
  239. ctx->prepared = false;
  240. return 0;
  241. }
  242. static int rm68200_prepare(struct drm_panel *panel)
  243. {
  244. struct rm68200 *ctx = panel_to_rm68200(panel);
  245. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  246. int ret;
  247. if (ctx->prepared)
  248. return 0;
  249. ret = regulator_enable(ctx->supply);
  250. if (ret < 0) {
  251. dev_err(ctx->dev, "failed to enable supply: %d\n", ret);
  252. return ret;
  253. }
  254. if (ctx->reset_gpio) {
  255. gpiod_set_value_cansleep(ctx->reset_gpio, 1);
  256. msleep(20);
  257. gpiod_set_value_cansleep(ctx->reset_gpio, 0);
  258. msleep(100);
  259. }
  260. rm68200_init_sequence(ctx);
  261. ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
  262. if (ret)
  263. return ret;
  264. msleep(125);
  265. ret = mipi_dsi_dcs_set_display_on(dsi);
  266. if (ret)
  267. return ret;
  268. msleep(20);
  269. ctx->prepared = true;
  270. return 0;
  271. }
  272. static int rm68200_enable(struct drm_panel *panel)
  273. {
  274. struct rm68200 *ctx = panel_to_rm68200(panel);
  275. if (ctx->enabled)
  276. return 0;
  277. ctx->enabled = true;
  278. return 0;
  279. }
  280. static int rm68200_get_modes(struct drm_panel *panel,
  281. struct drm_connector *connector)
  282. {
  283. struct drm_display_mode *mode;
  284. mode = drm_mode_duplicate(connector->dev, &default_mode);
  285. if (!mode) {
  286. dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
  287. default_mode.hdisplay, default_mode.vdisplay,
  288. drm_mode_vrefresh(&default_mode));
  289. return -ENOMEM;
  290. }
  291. drm_mode_set_name(mode);
  292. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  293. drm_mode_probed_add(connector, mode);
  294. connector->display_info.width_mm = mode->width_mm;
  295. connector->display_info.height_mm = mode->height_mm;
  296. return 1;
  297. }
  298. static const struct drm_panel_funcs rm68200_drm_funcs = {
  299. .disable = rm68200_disable,
  300. .unprepare = rm68200_unprepare,
  301. .prepare = rm68200_prepare,
  302. .enable = rm68200_enable,
  303. .get_modes = rm68200_get_modes,
  304. };
  305. static int rm68200_probe(struct mipi_dsi_device *dsi)
  306. {
  307. struct device *dev = &dsi->dev;
  308. struct rm68200 *ctx;
  309. int ret;
  310. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  311. if (!ctx)
  312. return -ENOMEM;
  313. ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
  314. if (IS_ERR(ctx->reset_gpio)) {
  315. ret = PTR_ERR(ctx->reset_gpio);
  316. dev_err(dev, "cannot get reset GPIO: %d\n", ret);
  317. return ret;
  318. }
  319. ctx->supply = devm_regulator_get(dev, "power");
  320. if (IS_ERR(ctx->supply)) {
  321. ret = PTR_ERR(ctx->supply);
  322. if (ret != -EPROBE_DEFER)
  323. dev_err(dev, "cannot get regulator: %d\n", ret);
  324. return ret;
  325. }
  326. mipi_dsi_set_drvdata(dsi, ctx);
  327. ctx->dev = dev;
  328. dsi->lanes = 2;
  329. dsi->format = MIPI_DSI_FMT_RGB888;
  330. dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  331. MIPI_DSI_MODE_LPM;
  332. drm_panel_init(&ctx->panel, dev, &rm68200_drm_funcs,
  333. DRM_MODE_CONNECTOR_DSI);
  334. ret = drm_panel_of_backlight(&ctx->panel);
  335. if (ret)
  336. return ret;
  337. drm_panel_add(&ctx->panel);
  338. ret = mipi_dsi_attach(dsi);
  339. if (ret < 0) {
  340. dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
  341. drm_panel_remove(&ctx->panel);
  342. return ret;
  343. }
  344. return 0;
  345. }
  346. static int rm68200_remove(struct mipi_dsi_device *dsi)
  347. {
  348. struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
  349. mipi_dsi_detach(dsi);
  350. drm_panel_remove(&ctx->panel);
  351. return 0;
  352. }
  353. static const struct of_device_id raydium_rm68200_of_match[] = {
  354. { .compatible = "raydium,rm68200" },
  355. { }
  356. };
  357. MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
  358. static struct mipi_dsi_driver raydium_rm68200_driver = {
  359. .probe = rm68200_probe,
  360. .remove = rm68200_remove,
  361. .driver = {
  362. .name = "panel-raydium-rm68200",
  363. .of_match_table = raydium_rm68200_of_match,
  364. },
  365. };
  366. module_mipi_dsi_driver(raydium_rm68200_driver);
  367. MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
  368. MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
  369. MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
  370. MODULE_LICENSE("GPL v2");