panel-orisetech-otm8009a.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2017
  4. *
  5. * Authors: Philippe Cornu <philippe.cornu@st.com>
  6. * Yannick Fertre <yannick.fertre@st.com>
  7. */
  8. #include <linux/backlight.h>
  9. #include <linux/delay.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/module.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <video/mipi_display.h>
  14. #include <drm/drm_mipi_dsi.h>
  15. #include <drm/drm_modes.h>
  16. #include <drm/drm_panel.h>
  17. #define OTM8009A_BACKLIGHT_DEFAULT 240
  18. #define OTM8009A_BACKLIGHT_MAX 255
  19. /* Manufacturer Command Set */
  20. #define MCS_ADRSFT 0x0000 /* Address Shift Function */
  21. #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
  22. #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
  23. #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
  24. #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
  25. #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
  26. #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
  27. #define MCS_NO_DOC1 0xC48A /* Command not documented */
  28. #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
  29. #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
  30. #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */
  31. #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */
  32. #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */
  33. #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */
  34. #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */
  35. #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */
  36. #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */
  37. #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */
  38. #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */
  39. #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */
  40. #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */
  41. #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */
  42. #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */
  43. #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */
  44. #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */
  45. #define MCS_GOAVST 0xCE80 /* GOA VST Setting */
  46. #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */
  47. #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */
  48. #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */
  49. #define MCS_NO_DOC2 0xCFD0 /* Command not documented */
  50. #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */
  51. #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */
  52. #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */
  53. #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */
  54. #define MCS_NO_DOC3 0xF5B6 /* Command not documented */
  55. #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
  56. #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
  57. struct otm8009a {
  58. struct device *dev;
  59. struct drm_panel panel;
  60. struct backlight_device *bl_dev;
  61. struct gpio_desc *reset_gpio;
  62. struct regulator *supply;
  63. bool prepared;
  64. bool enabled;
  65. };
  66. static const struct drm_display_mode default_mode = {
  67. .clock = 29700,
  68. .hdisplay = 480,
  69. .hsync_start = 480 + 98,
  70. .hsync_end = 480 + 98 + 32,
  71. .htotal = 480 + 98 + 32 + 98,
  72. .vdisplay = 800,
  73. .vsync_start = 800 + 15,
  74. .vsync_end = 800 + 15 + 10,
  75. .vtotal = 800 + 15 + 10 + 14,
  76. .flags = 0,
  77. .width_mm = 52,
  78. .height_mm = 86,
  79. };
  80. static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
  81. {
  82. return container_of(panel, struct otm8009a, panel);
  83. }
  84. static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data,
  85. size_t len)
  86. {
  87. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  88. if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0)
  89. dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n");
  90. }
  91. static void otm8009a_dcs_write_buf_hs(struct otm8009a *ctx, const void *data,
  92. size_t len)
  93. {
  94. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  95. /* data will be sent in dsi hs mode (ie. no lpm) */
  96. dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
  97. otm8009a_dcs_write_buf(ctx, data, len);
  98. /* restore back the dsi lpm mode */
  99. dsi->mode_flags |= MIPI_DSI_MODE_LPM;
  100. }
  101. #define dcs_write_seq(ctx, seq...) \
  102. ({ \
  103. static const u8 d[] = { seq }; \
  104. otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
  105. })
  106. #define dcs_write_cmd_at(ctx, cmd, seq...) \
  107. ({ \
  108. dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \
  109. dcs_write_seq(ctx, (cmd) >> 8, seq); \
  110. })
  111. static int otm8009a_init_sequence(struct otm8009a *ctx)
  112. {
  113. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  114. int ret;
  115. /* Enter CMD2 */
  116. dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
  117. /* Enter Orise Command2 */
  118. dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09);
  119. dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30);
  120. mdelay(10);
  121. dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40);
  122. mdelay(10);
  123. dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9);
  124. dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34);
  125. dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50);
  126. dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E);
  127. dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */
  128. dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01);
  129. dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34);
  130. dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33);
  131. dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79);
  132. dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B);
  133. dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83);
  134. dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83);
  135. dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E);
  136. dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01);
  137. dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
  138. dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
  139. 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
  140. dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
  141. 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
  142. dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
  143. 0x01, 0x02, 0x00, 0x00);
  144. dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00);
  145. dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  146. dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  147. 0, 0, 0, 0, 0);
  148. dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  149. 0, 0, 0, 0, 0);
  150. dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  151. dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
  152. 0, 0, 0, 0, 0);
  153. dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
  154. 4, 0, 0, 0, 0);
  155. dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  156. dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  157. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
  158. dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
  159. 0x00, 0x00, 0x00, 0x00);
  160. dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  161. 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
  162. dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
  163. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  164. dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
  165. 0x00, 0x00, 0x00, 0x00);
  166. dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  167. 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
  168. dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
  169. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  170. dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66);
  171. dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06);
  172. dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
  173. 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
  174. 0x01);
  175. dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
  176. 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
  177. 0x01);
  178. /* Exit CMD2 */
  179. dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
  180. ret = mipi_dsi_dcs_nop(dsi);
  181. if (ret)
  182. return ret;
  183. ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
  184. if (ret)
  185. return ret;
  186. /* Wait for sleep out exit */
  187. mdelay(120);
  188. /* Default portrait 480x800 rgb24 */
  189. dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
  190. ret = mipi_dsi_dcs_set_column_address(dsi, 0,
  191. default_mode.hdisplay - 1);
  192. if (ret)
  193. return ret;
  194. ret = mipi_dsi_dcs_set_page_address(dsi, 0, default_mode.vdisplay - 1);
  195. if (ret)
  196. return ret;
  197. /* See otm8009a driver documentation for pixel format descriptions */
  198. ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |
  199. MIPI_DCS_PIXEL_FMT_24BIT << 4);
  200. if (ret)
  201. return ret;
  202. /* Disable CABC feature */
  203. dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
  204. ret = mipi_dsi_dcs_set_display_on(dsi);
  205. if (ret)
  206. return ret;
  207. ret = mipi_dsi_dcs_nop(dsi);
  208. if (ret)
  209. return ret;
  210. /* Send Command GRAM memory write (no parameters) */
  211. dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START);
  212. /* Wait a short while to let the panel be ready before the 1st frame */
  213. mdelay(10);
  214. return 0;
  215. }
  216. static int otm8009a_disable(struct drm_panel *panel)
  217. {
  218. struct otm8009a *ctx = panel_to_otm8009a(panel);
  219. struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
  220. int ret;
  221. if (!ctx->enabled)
  222. return 0; /* This is not an issue so we return 0 here */
  223. backlight_disable(ctx->bl_dev);
  224. ret = mipi_dsi_dcs_set_display_off(dsi);
  225. if (ret)
  226. return ret;
  227. ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
  228. if (ret)
  229. return ret;
  230. msleep(120);
  231. ctx->enabled = false;
  232. return 0;
  233. }
  234. static int otm8009a_unprepare(struct drm_panel *panel)
  235. {
  236. struct otm8009a *ctx = panel_to_otm8009a(panel);
  237. if (!ctx->prepared)
  238. return 0;
  239. if (ctx->reset_gpio) {
  240. gpiod_set_value_cansleep(ctx->reset_gpio, 1);
  241. msleep(20);
  242. }
  243. regulator_disable(ctx->supply);
  244. ctx->prepared = false;
  245. return 0;
  246. }
  247. static int otm8009a_prepare(struct drm_panel *panel)
  248. {
  249. struct otm8009a *ctx = panel_to_otm8009a(panel);
  250. int ret;
  251. if (ctx->prepared)
  252. return 0;
  253. ret = regulator_enable(ctx->supply);
  254. if (ret < 0) {
  255. dev_err(panel->dev, "failed to enable supply: %d\n", ret);
  256. return ret;
  257. }
  258. if (ctx->reset_gpio) {
  259. gpiod_set_value_cansleep(ctx->reset_gpio, 0);
  260. gpiod_set_value_cansleep(ctx->reset_gpio, 1);
  261. msleep(20);
  262. gpiod_set_value_cansleep(ctx->reset_gpio, 0);
  263. msleep(100);
  264. }
  265. ret = otm8009a_init_sequence(ctx);
  266. if (ret)
  267. return ret;
  268. ctx->prepared = true;
  269. return 0;
  270. }
  271. static int otm8009a_enable(struct drm_panel *panel)
  272. {
  273. struct otm8009a *ctx = panel_to_otm8009a(panel);
  274. if (ctx->enabled)
  275. return 0;
  276. backlight_enable(ctx->bl_dev);
  277. ctx->enabled = true;
  278. return 0;
  279. }
  280. static int otm8009a_get_modes(struct drm_panel *panel,
  281. struct drm_connector *connector)
  282. {
  283. struct drm_display_mode *mode;
  284. mode = drm_mode_duplicate(connector->dev, &default_mode);
  285. if (!mode) {
  286. dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
  287. default_mode.hdisplay, default_mode.vdisplay,
  288. drm_mode_vrefresh(&default_mode));
  289. return -ENOMEM;
  290. }
  291. drm_mode_set_name(mode);
  292. mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
  293. drm_mode_probed_add(connector, mode);
  294. connector->display_info.width_mm = mode->width_mm;
  295. connector->display_info.height_mm = mode->height_mm;
  296. return 1;
  297. }
  298. static const struct drm_panel_funcs otm8009a_drm_funcs = {
  299. .disable = otm8009a_disable,
  300. .unprepare = otm8009a_unprepare,
  301. .prepare = otm8009a_prepare,
  302. .enable = otm8009a_enable,
  303. .get_modes = otm8009a_get_modes,
  304. };
  305. /*
  306. * DSI-BASED BACKLIGHT
  307. */
  308. static int otm8009a_backlight_update_status(struct backlight_device *bd)
  309. {
  310. struct otm8009a *ctx = bl_get_data(bd);
  311. u8 data[2];
  312. if (!ctx->prepared) {
  313. dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n");
  314. return -ENXIO;
  315. }
  316. if (bd->props.power <= FB_BLANK_NORMAL) {
  317. /* Power on the backlight with the requested brightness
  318. * Note We can not use mipi_dsi_dcs_set_display_brightness()
  319. * as otm8009a driver support only 8-bit brightness (1 param).
  320. */
  321. data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
  322. data[1] = bd->props.brightness;
  323. otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
  324. /* set Brightness Control & Backlight on */
  325. data[1] = 0x24;
  326. } else {
  327. /* Power off the backlight: set Brightness Control & Bl off */
  328. data[1] = 0;
  329. }
  330. /* Update Brightness Control & Backlight */
  331. data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
  332. otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
  333. return 0;
  334. }
  335. static const struct backlight_ops otm8009a_backlight_ops = {
  336. .update_status = otm8009a_backlight_update_status,
  337. };
  338. static int otm8009a_probe(struct mipi_dsi_device *dsi)
  339. {
  340. struct device *dev = &dsi->dev;
  341. struct otm8009a *ctx;
  342. int ret;
  343. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  344. if (!ctx)
  345. return -ENOMEM;
  346. ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
  347. if (IS_ERR(ctx->reset_gpio)) {
  348. dev_err(dev, "cannot get reset-gpio\n");
  349. return PTR_ERR(ctx->reset_gpio);
  350. }
  351. ctx->supply = devm_regulator_get(dev, "power");
  352. if (IS_ERR(ctx->supply)) {
  353. ret = PTR_ERR(ctx->supply);
  354. if (ret != -EPROBE_DEFER)
  355. dev_err(dev, "failed to request regulator: %d\n", ret);
  356. return ret;
  357. }
  358. mipi_dsi_set_drvdata(dsi, ctx);
  359. ctx->dev = dev;
  360. dsi->lanes = 2;
  361. dsi->format = MIPI_DSI_FMT_RGB888;
  362. dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  363. MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
  364. drm_panel_init(&ctx->panel, dev, &otm8009a_drm_funcs,
  365. DRM_MODE_CONNECTOR_DSI);
  366. ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev),
  367. dsi->host->dev, ctx,
  368. &otm8009a_backlight_ops,
  369. NULL);
  370. if (IS_ERR(ctx->bl_dev)) {
  371. ret = PTR_ERR(ctx->bl_dev);
  372. dev_err(dev, "failed to register backlight: %d\n", ret);
  373. return ret;
  374. }
  375. ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX;
  376. ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT;
  377. ctx->bl_dev->props.power = FB_BLANK_POWERDOWN;
  378. ctx->bl_dev->props.type = BACKLIGHT_RAW;
  379. drm_panel_add(&ctx->panel);
  380. ret = mipi_dsi_attach(dsi);
  381. if (ret < 0) {
  382. dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n");
  383. drm_panel_remove(&ctx->panel);
  384. return ret;
  385. }
  386. return 0;
  387. }
  388. static int otm8009a_remove(struct mipi_dsi_device *dsi)
  389. {
  390. struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi);
  391. mipi_dsi_detach(dsi);
  392. drm_panel_remove(&ctx->panel);
  393. return 0;
  394. }
  395. static const struct of_device_id orisetech_otm8009a_of_match[] = {
  396. { .compatible = "orisetech,otm8009a" },
  397. { }
  398. };
  399. MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match);
  400. static struct mipi_dsi_driver orisetech_otm8009a_driver = {
  401. .probe = otm8009a_probe,
  402. .remove = otm8009a_remove,
  403. .driver = {
  404. .name = "panel-orisetech-otm8009a",
  405. .of_match_table = orisetech_otm8009a_of_match,
  406. },
  407. };
  408. module_mipi_dsi_driver(orisetech_otm8009a_driver);
  409. MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
  410. MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
  411. MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel");
  412. MODULE_LICENSE("GPL v2");