omap_irq.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  4. * Author: Rob Clark <rob.clark@linaro.org>
  5. */
  6. #include <drm/drm_vblank.h>
  7. #include "omap_drv.h"
  8. struct omap_irq_wait {
  9. struct list_head node;
  10. wait_queue_head_t wq;
  11. u32 irqmask;
  12. int count;
  13. };
  14. /* call with wait_lock and dispc runtime held */
  15. static void omap_irq_update(struct drm_device *dev)
  16. {
  17. struct omap_drm_private *priv = dev->dev_private;
  18. struct omap_irq_wait *wait;
  19. u32 irqmask = priv->irq_mask;
  20. assert_spin_locked(&priv->wait_lock);
  21. list_for_each_entry(wait, &priv->wait_list, node)
  22. irqmask |= wait->irqmask;
  23. DBG("irqmask=%08x", irqmask);
  24. priv->dispc_ops->write_irqenable(priv->dispc, irqmask);
  25. }
  26. static void omap_irq_wait_handler(struct omap_irq_wait *wait)
  27. {
  28. wait->count--;
  29. wake_up(&wait->wq);
  30. }
  31. struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
  32. u32 irqmask, int count)
  33. {
  34. struct omap_drm_private *priv = dev->dev_private;
  35. struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
  36. unsigned long flags;
  37. init_waitqueue_head(&wait->wq);
  38. wait->irqmask = irqmask;
  39. wait->count = count;
  40. spin_lock_irqsave(&priv->wait_lock, flags);
  41. list_add(&wait->node, &priv->wait_list);
  42. omap_irq_update(dev);
  43. spin_unlock_irqrestore(&priv->wait_lock, flags);
  44. return wait;
  45. }
  46. int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
  47. unsigned long timeout)
  48. {
  49. struct omap_drm_private *priv = dev->dev_private;
  50. unsigned long flags;
  51. int ret;
  52. ret = wait_event_timeout(wait->wq, (wait->count <= 0), timeout);
  53. spin_lock_irqsave(&priv->wait_lock, flags);
  54. list_del(&wait->node);
  55. omap_irq_update(dev);
  56. spin_unlock_irqrestore(&priv->wait_lock, flags);
  57. kfree(wait);
  58. return ret == 0 ? -1 : 0;
  59. }
  60. int omap_irq_enable_framedone(struct drm_crtc *crtc, bool enable)
  61. {
  62. struct drm_device *dev = crtc->dev;
  63. struct omap_drm_private *priv = dev->dev_private;
  64. unsigned long flags;
  65. enum omap_channel channel = omap_crtc_channel(crtc);
  66. int framedone_irq =
  67. priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel);
  68. DBG("dev=%p, crtc=%u, enable=%d", dev, channel, enable);
  69. spin_lock_irqsave(&priv->wait_lock, flags);
  70. if (enable)
  71. priv->irq_mask |= framedone_irq;
  72. else
  73. priv->irq_mask &= ~framedone_irq;
  74. omap_irq_update(dev);
  75. spin_unlock_irqrestore(&priv->wait_lock, flags);
  76. return 0;
  77. }
  78. /**
  79. * enable_vblank - enable vblank interrupt events
  80. * @dev: DRM device
  81. * @pipe: which irq to enable
  82. *
  83. * Enable vblank interrupts for @crtc. If the device doesn't have
  84. * a hardware vblank counter, this routine should be a no-op, since
  85. * interrupts will have to stay on to keep the count accurate.
  86. *
  87. * RETURNS
  88. * Zero on success, appropriate errno if the given @crtc's vblank
  89. * interrupt cannot be enabled.
  90. */
  91. int omap_irq_enable_vblank(struct drm_crtc *crtc)
  92. {
  93. struct drm_device *dev = crtc->dev;
  94. struct omap_drm_private *priv = dev->dev_private;
  95. unsigned long flags;
  96. enum omap_channel channel = omap_crtc_channel(crtc);
  97. DBG("dev=%p, crtc=%u", dev, channel);
  98. spin_lock_irqsave(&priv->wait_lock, flags);
  99. priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
  100. channel);
  101. omap_irq_update(dev);
  102. spin_unlock_irqrestore(&priv->wait_lock, flags);
  103. return 0;
  104. }
  105. /**
  106. * disable_vblank - disable vblank interrupt events
  107. * @dev: DRM device
  108. * @pipe: which irq to enable
  109. *
  110. * Disable vblank interrupts for @crtc. If the device doesn't have
  111. * a hardware vblank counter, this routine should be a no-op, since
  112. * interrupts will have to stay on to keep the count accurate.
  113. */
  114. void omap_irq_disable_vblank(struct drm_crtc *crtc)
  115. {
  116. struct drm_device *dev = crtc->dev;
  117. struct omap_drm_private *priv = dev->dev_private;
  118. unsigned long flags;
  119. enum omap_channel channel = omap_crtc_channel(crtc);
  120. DBG("dev=%p, crtc=%u", dev, channel);
  121. spin_lock_irqsave(&priv->wait_lock, flags);
  122. priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
  123. channel);
  124. omap_irq_update(dev);
  125. spin_unlock_irqrestore(&priv->wait_lock, flags);
  126. }
  127. static void omap_irq_fifo_underflow(struct omap_drm_private *priv,
  128. u32 irqstatus)
  129. {
  130. static DEFINE_RATELIMIT_STATE(_rs, DEFAULT_RATELIMIT_INTERVAL,
  131. DEFAULT_RATELIMIT_BURST);
  132. static const struct {
  133. const char *name;
  134. u32 mask;
  135. } sources[] = {
  136. { "gfx", DISPC_IRQ_GFX_FIFO_UNDERFLOW },
  137. { "vid1", DISPC_IRQ_VID1_FIFO_UNDERFLOW },
  138. { "vid2", DISPC_IRQ_VID2_FIFO_UNDERFLOW },
  139. { "vid3", DISPC_IRQ_VID3_FIFO_UNDERFLOW },
  140. };
  141. const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW
  142. | DISPC_IRQ_VID1_FIFO_UNDERFLOW
  143. | DISPC_IRQ_VID2_FIFO_UNDERFLOW
  144. | DISPC_IRQ_VID3_FIFO_UNDERFLOW;
  145. unsigned int i;
  146. spin_lock(&priv->wait_lock);
  147. irqstatus &= priv->irq_mask & mask;
  148. spin_unlock(&priv->wait_lock);
  149. if (!irqstatus)
  150. return;
  151. if (!__ratelimit(&_rs))
  152. return;
  153. DRM_ERROR("FIFO underflow on ");
  154. for (i = 0; i < ARRAY_SIZE(sources); ++i) {
  155. if (sources[i].mask & irqstatus)
  156. pr_cont("%s ", sources[i].name);
  157. }
  158. pr_cont("(0x%08x)\n", irqstatus);
  159. }
  160. static void omap_irq_ocp_error_handler(struct drm_device *dev,
  161. u32 irqstatus)
  162. {
  163. if (!(irqstatus & DISPC_IRQ_OCP_ERR))
  164. return;
  165. dev_err_ratelimited(dev->dev, "OCP error\n");
  166. }
  167. static irqreturn_t omap_irq_handler(int irq, void *arg)
  168. {
  169. struct drm_device *dev = (struct drm_device *) arg;
  170. struct omap_drm_private *priv = dev->dev_private;
  171. struct omap_irq_wait *wait, *n;
  172. unsigned long flags;
  173. unsigned int id;
  174. u32 irqstatus;
  175. irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc);
  176. priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus);
  177. priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */
  178. VERB("irqs: %08x", irqstatus);
  179. for (id = 0; id < priv->num_pipes; id++) {
  180. struct drm_crtc *crtc = priv->pipes[id].crtc;
  181. enum omap_channel channel = omap_crtc_channel(crtc);
  182. if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) {
  183. drm_handle_vblank(dev, id);
  184. omap_crtc_vblank_irq(crtc);
  185. }
  186. if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel))
  187. omap_crtc_error_irq(crtc, irqstatus);
  188. if (irqstatus & priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel))
  189. omap_crtc_framedone_irq(crtc, irqstatus);
  190. }
  191. omap_irq_ocp_error_handler(dev, irqstatus);
  192. omap_irq_fifo_underflow(priv, irqstatus);
  193. spin_lock_irqsave(&priv->wait_lock, flags);
  194. list_for_each_entry_safe(wait, n, &priv->wait_list, node) {
  195. if (wait->irqmask & irqstatus)
  196. omap_irq_wait_handler(wait);
  197. }
  198. spin_unlock_irqrestore(&priv->wait_lock, flags);
  199. return IRQ_HANDLED;
  200. }
  201. static const u32 omap_underflow_irqs[] = {
  202. [OMAP_DSS_GFX] = DISPC_IRQ_GFX_FIFO_UNDERFLOW,
  203. [OMAP_DSS_VIDEO1] = DISPC_IRQ_VID1_FIFO_UNDERFLOW,
  204. [OMAP_DSS_VIDEO2] = DISPC_IRQ_VID2_FIFO_UNDERFLOW,
  205. [OMAP_DSS_VIDEO3] = DISPC_IRQ_VID3_FIFO_UNDERFLOW,
  206. };
  207. /*
  208. * We need a special version, instead of just using drm_irq_install(),
  209. * because we need to register the irq via omapdss. Once omapdss and
  210. * omapdrm are merged together we can assign the dispc hwmod data to
  211. * ourselves and drop these and just use drm_irq_{install,uninstall}()
  212. */
  213. int omap_drm_irq_install(struct drm_device *dev)
  214. {
  215. struct omap_drm_private *priv = dev->dev_private;
  216. unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
  217. unsigned int max_planes;
  218. unsigned int i;
  219. int ret;
  220. spin_lock_init(&priv->wait_lock);
  221. INIT_LIST_HEAD(&priv->wait_list);
  222. priv->irq_mask = DISPC_IRQ_OCP_ERR;
  223. max_planes = min(ARRAY_SIZE(priv->planes),
  224. ARRAY_SIZE(omap_underflow_irqs));
  225. for (i = 0; i < max_planes; ++i) {
  226. if (priv->planes[i])
  227. priv->irq_mask |= omap_underflow_irqs[i];
  228. }
  229. for (i = 0; i < num_mgrs; ++i)
  230. priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i);
  231. priv->dispc_ops->runtime_get(priv->dispc);
  232. priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff);
  233. priv->dispc_ops->runtime_put(priv->dispc);
  234. ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev);
  235. if (ret < 0)
  236. return ret;
  237. dev->irq_enabled = true;
  238. return 0;
  239. }
  240. void omap_drm_irq_uninstall(struct drm_device *dev)
  241. {
  242. struct omap_drm_private *priv = dev->dev_private;
  243. if (!dev->irq_enabled)
  244. return;
  245. dev->irq_enabled = false;
  246. priv->dispc_ops->free_irq(priv->dispc, dev);
  247. }