omap_drv.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  4. * Author: Rob Clark <rob@ti.com>
  5. */
  6. #include <linux/dma-mapping.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/sort.h>
  9. #include <linux/sys_soc.h>
  10. #include <drm/drm_atomic.h>
  11. #include <drm/drm_atomic_helper.h>
  12. #include <drm/drm_bridge.h>
  13. #include <drm/drm_bridge_connector.h>
  14. #include <drm/drm_drv.h>
  15. #include <drm/drm_fb_helper.h>
  16. #include <drm/drm_file.h>
  17. #include <drm/drm_ioctl.h>
  18. #include <drm/drm_panel.h>
  19. #include <drm/drm_prime.h>
  20. #include <drm/drm_probe_helper.h>
  21. #include <drm/drm_vblank.h>
  22. #include "omap_dmm_tiler.h"
  23. #include "omap_drv.h"
  24. #define DRIVER_NAME MODULE_NAME
  25. #define DRIVER_DESC "OMAP DRM"
  26. #define DRIVER_DATE "20110917"
  27. #define DRIVER_MAJOR 1
  28. #define DRIVER_MINOR 0
  29. #define DRIVER_PATCHLEVEL 0
  30. /*
  31. * mode config funcs
  32. */
  33. /* Notes about mapping DSS and DRM entities:
  34. * CRTC: overlay
  35. * encoder: manager.. with some extension to allow one primary CRTC
  36. * and zero or more video CRTC's to be mapped to one encoder?
  37. * connector: dssdev.. manager can be attached/detached from different
  38. * devices
  39. */
  40. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  41. struct drm_atomic_state *old_state)
  42. {
  43. struct drm_crtc_state *new_crtc_state;
  44. struct drm_crtc *crtc;
  45. unsigned int i;
  46. int ret;
  47. for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
  48. if (!new_crtc_state->active)
  49. continue;
  50. ret = omap_crtc_wait_pending(crtc);
  51. if (!ret)
  52. dev_warn(dev->dev,
  53. "atomic complete timeout (pipe %u)!\n", i);
  54. }
  55. }
  56. static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
  57. {
  58. struct drm_device *dev = old_state->dev;
  59. struct omap_drm_private *priv = dev->dev_private;
  60. priv->dispc_ops->runtime_get(priv->dispc);
  61. /* Apply the atomic update. */
  62. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  63. if (priv->omaprev != 0x3430) {
  64. /* With the current dss dispc implementation we have to enable
  65. * the new modeset before we can commit planes. The dispc ovl
  66. * configuration relies on the video mode configuration been
  67. * written into the HW when the ovl configuration is
  68. * calculated.
  69. *
  70. * This approach is not ideal because after a mode change the
  71. * plane update is executed only after the first vblank
  72. * interrupt. The dispc implementation should be fixed so that
  73. * it is able use uncommitted drm state information.
  74. */
  75. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  76. omap_atomic_wait_for_completion(dev, old_state);
  77. drm_atomic_helper_commit_planes(dev, old_state, 0);
  78. drm_atomic_helper_commit_hw_done(old_state);
  79. } else {
  80. /*
  81. * OMAP3 DSS seems to have issues with the work-around above,
  82. * resulting in endless sync losts if a crtc is enabled without
  83. * a plane. For now, skip the WA for OMAP3.
  84. */
  85. drm_atomic_helper_commit_planes(dev, old_state, 0);
  86. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  87. drm_atomic_helper_commit_hw_done(old_state);
  88. }
  89. /*
  90. * Wait for completion of the page flips to ensure that old buffers
  91. * can't be touched by the hardware anymore before cleaning up planes.
  92. */
  93. omap_atomic_wait_for_completion(dev, old_state);
  94. drm_atomic_helper_cleanup_planes(dev, old_state);
  95. priv->dispc_ops->runtime_put(priv->dispc);
  96. }
  97. static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
  98. .atomic_commit_tail = omap_atomic_commit_tail,
  99. };
  100. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  101. .fb_create = omap_framebuffer_create,
  102. .output_poll_changed = drm_fb_helper_output_poll_changed,
  103. .atomic_check = drm_atomic_helper_check,
  104. .atomic_commit = drm_atomic_helper_commit,
  105. };
  106. static void omap_disconnect_pipelines(struct drm_device *ddev)
  107. {
  108. struct omap_drm_private *priv = ddev->dev_private;
  109. unsigned int i;
  110. for (i = 0; i < priv->num_pipes; i++) {
  111. struct omap_drm_pipeline *pipe = &priv->pipes[i];
  112. omapdss_device_disconnect(NULL, pipe->output);
  113. omapdss_device_put(pipe->output);
  114. pipe->output = NULL;
  115. }
  116. memset(&priv->channels, 0, sizeof(priv->channels));
  117. priv->num_pipes = 0;
  118. }
  119. static int omap_connect_pipelines(struct drm_device *ddev)
  120. {
  121. struct omap_drm_private *priv = ddev->dev_private;
  122. struct omap_dss_device *output = NULL;
  123. int r;
  124. for_each_dss_output(output) {
  125. r = omapdss_device_connect(priv->dss, NULL, output);
  126. if (r == -EPROBE_DEFER) {
  127. omapdss_device_put(output);
  128. return r;
  129. } else if (r) {
  130. dev_warn(output->dev, "could not connect output %s\n",
  131. output->name);
  132. } else {
  133. struct omap_drm_pipeline *pipe;
  134. pipe = &priv->pipes[priv->num_pipes++];
  135. pipe->output = omapdss_device_get(output);
  136. if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) {
  137. /* To balance the 'for_each_dss_output' loop */
  138. omapdss_device_put(output);
  139. break;
  140. }
  141. }
  142. }
  143. return 0;
  144. }
  145. static int omap_compare_pipelines(const void *a, const void *b)
  146. {
  147. const struct omap_drm_pipeline *pipe1 = a;
  148. const struct omap_drm_pipeline *pipe2 = b;
  149. if (pipe1->alias_id > pipe2->alias_id)
  150. return 1;
  151. else if (pipe1->alias_id < pipe2->alias_id)
  152. return -1;
  153. return 0;
  154. }
  155. static int omap_modeset_init_properties(struct drm_device *dev)
  156. {
  157. struct omap_drm_private *priv = dev->dev_private;
  158. unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
  159. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
  160. num_planes - 1);
  161. if (!priv->zorder_prop)
  162. return -ENOMEM;
  163. return 0;
  164. }
  165. static int omap_display_id(struct omap_dss_device *output)
  166. {
  167. struct device_node *node = NULL;
  168. if (output->next) {
  169. struct omap_dss_device *display = output;
  170. while (display->next)
  171. display = display->next;
  172. node = display->dev->of_node;
  173. } else if (output->bridge) {
  174. struct drm_bridge *bridge = output->bridge;
  175. while (drm_bridge_get_next_bridge(bridge))
  176. bridge = drm_bridge_get_next_bridge(bridge);
  177. node = bridge->of_node;
  178. }
  179. return node ? of_alias_get_id(node, "display") : -ENODEV;
  180. }
  181. static int omap_modeset_init(struct drm_device *dev)
  182. {
  183. struct omap_drm_private *priv = dev->dev_private;
  184. int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
  185. int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
  186. unsigned int i;
  187. int ret;
  188. u32 plane_crtc_mask;
  189. if (!omapdss_stack_is_ready())
  190. return -EPROBE_DEFER;
  191. drm_mode_config_init(dev);
  192. ret = omap_modeset_init_properties(dev);
  193. if (ret < 0)
  194. return ret;
  195. /*
  196. * This function creates exactly one connector, encoder, crtc,
  197. * and primary plane per each connected dss-device. Each
  198. * connector->encoder->crtc chain is expected to be separate
  199. * and each crtc is connect to a single dss-channel. If the
  200. * configuration does not match the expectations or exceeds
  201. * the available resources, the configuration is rejected.
  202. */
  203. ret = omap_connect_pipelines(dev);
  204. if (ret < 0)
  205. return ret;
  206. if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) {
  207. dev_err(dev->dev, "%s(): Too many connected displays\n",
  208. __func__);
  209. return -EINVAL;
  210. }
  211. /* Create all planes first. They can all be put to any CRTC. */
  212. plane_crtc_mask = (1 << priv->num_pipes) - 1;
  213. for (i = 0; i < num_ovls; i++) {
  214. enum drm_plane_type type = i < priv->num_pipes
  215. ? DRM_PLANE_TYPE_PRIMARY
  216. : DRM_PLANE_TYPE_OVERLAY;
  217. struct drm_plane *plane;
  218. if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
  219. return -EINVAL;
  220. plane = omap_plane_init(dev, i, type, plane_crtc_mask);
  221. if (IS_ERR(plane))
  222. return PTR_ERR(plane);
  223. priv->planes[priv->num_planes++] = plane;
  224. }
  225. /*
  226. * Create the encoders, attach the bridges and get the pipeline alias
  227. * IDs.
  228. */
  229. for (i = 0; i < priv->num_pipes; i++) {
  230. struct omap_drm_pipeline *pipe = &priv->pipes[i];
  231. int id;
  232. pipe->encoder = omap_encoder_init(dev, pipe->output);
  233. if (!pipe->encoder)
  234. return -ENOMEM;
  235. if (pipe->output->bridge) {
  236. ret = drm_bridge_attach(pipe->encoder,
  237. pipe->output->bridge, NULL,
  238. DRM_BRIDGE_ATTACH_NO_CONNECTOR);
  239. if (ret < 0) {
  240. dev_err(priv->dev,
  241. "unable to attach bridge %pOF\n",
  242. pipe->output->bridge->of_node);
  243. return ret;
  244. }
  245. }
  246. id = omap_display_id(pipe->output);
  247. pipe->alias_id = id >= 0 ? id : i;
  248. }
  249. /* Sort the pipelines by DT aliases. */
  250. sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]),
  251. omap_compare_pipelines, NULL);
  252. /*
  253. * Populate the pipeline lookup table by DISPC channel. Only one display
  254. * is allowed per channel.
  255. */
  256. for (i = 0; i < priv->num_pipes; ++i) {
  257. struct omap_drm_pipeline *pipe = &priv->pipes[i];
  258. enum omap_channel channel = pipe->output->dispc_channel;
  259. if (WARN_ON(priv->channels[channel] != NULL))
  260. return -EINVAL;
  261. priv->channels[channel] = pipe;
  262. }
  263. /* Create the connectors and CRTCs. */
  264. for (i = 0; i < priv->num_pipes; i++) {
  265. struct omap_drm_pipeline *pipe = &priv->pipes[i];
  266. struct drm_encoder *encoder = pipe->encoder;
  267. struct drm_crtc *crtc;
  268. if (pipe->output->next) {
  269. pipe->connector = omap_connector_init(dev, pipe->output,
  270. encoder);
  271. if (!pipe->connector)
  272. return -ENOMEM;
  273. } else {
  274. pipe->connector = drm_bridge_connector_init(dev, encoder);
  275. if (IS_ERR(pipe->connector)) {
  276. dev_err(priv->dev,
  277. "unable to create bridge connector for %s\n",
  278. pipe->output->name);
  279. return PTR_ERR(pipe->connector);
  280. }
  281. }
  282. drm_connector_attach_encoder(pipe->connector, encoder);
  283. crtc = omap_crtc_init(dev, pipe, priv->planes[i]);
  284. if (IS_ERR(crtc))
  285. return PTR_ERR(crtc);
  286. encoder->possible_crtcs = 1 << i;
  287. pipe->crtc = crtc;
  288. }
  289. DBG("registered %u planes, %u crtcs/encoders/connectors\n",
  290. priv->num_planes, priv->num_pipes);
  291. dev->mode_config.min_width = 8;
  292. dev->mode_config.min_height = 2;
  293. /*
  294. * Note: these values are used for multiple independent things:
  295. * connector mode filtering, buffer sizes, crtc sizes...
  296. * Use big enough values here to cover all use cases, and do more
  297. * specific checking in the respective code paths.
  298. */
  299. dev->mode_config.max_width = 8192;
  300. dev->mode_config.max_height = 8192;
  301. /* We want the zpos to be normalized */
  302. dev->mode_config.normalize_zpos = true;
  303. dev->mode_config.funcs = &omap_mode_config_funcs;
  304. dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
  305. drm_mode_config_reset(dev);
  306. omap_drm_irq_install(dev);
  307. return 0;
  308. }
  309. static void omap_modeset_fini(struct drm_device *ddev)
  310. {
  311. omap_drm_irq_uninstall(ddev);
  312. drm_mode_config_cleanup(ddev);
  313. }
  314. /*
  315. * Enable the HPD in external components if supported
  316. */
  317. static void omap_modeset_enable_external_hpd(struct drm_device *ddev)
  318. {
  319. struct omap_drm_private *priv = ddev->dev_private;
  320. unsigned int i;
  321. for (i = 0; i < priv->num_pipes; i++) {
  322. struct drm_connector *connector = priv->pipes[i].connector;
  323. if (!connector)
  324. continue;
  325. if (priv->pipes[i].output->bridge)
  326. drm_bridge_connector_enable_hpd(connector);
  327. }
  328. }
  329. /*
  330. * Disable the HPD in external components if supported
  331. */
  332. static void omap_modeset_disable_external_hpd(struct drm_device *ddev)
  333. {
  334. struct omap_drm_private *priv = ddev->dev_private;
  335. unsigned int i;
  336. for (i = 0; i < priv->num_pipes; i++) {
  337. struct drm_connector *connector = priv->pipes[i].connector;
  338. if (!connector)
  339. continue;
  340. if (priv->pipes[i].output->bridge)
  341. drm_bridge_connector_disable_hpd(connector);
  342. }
  343. }
  344. /*
  345. * drm ioctl funcs
  346. */
  347. static int ioctl_get_param(struct drm_device *dev, void *data,
  348. struct drm_file *file_priv)
  349. {
  350. struct omap_drm_private *priv = dev->dev_private;
  351. struct drm_omap_param *args = data;
  352. DBG("%p: param=%llu", dev, args->param);
  353. switch (args->param) {
  354. case OMAP_PARAM_CHIPSET_ID:
  355. args->value = priv->omaprev;
  356. break;
  357. default:
  358. DBG("unknown parameter %lld", args->param);
  359. return -EINVAL;
  360. }
  361. return 0;
  362. }
  363. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  364. static int ioctl_gem_new(struct drm_device *dev, void *data,
  365. struct drm_file *file_priv)
  366. {
  367. struct drm_omap_gem_new *args = data;
  368. u32 flags = args->flags & OMAP_BO_USER_MASK;
  369. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  370. args->size.bytes, flags);
  371. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  372. &args->handle);
  373. }
  374. static int ioctl_gem_info(struct drm_device *dev, void *data,
  375. struct drm_file *file_priv)
  376. {
  377. struct drm_omap_gem_info *args = data;
  378. struct drm_gem_object *obj;
  379. int ret = 0;
  380. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  381. obj = drm_gem_object_lookup(file_priv, args->handle);
  382. if (!obj)
  383. return -ENOENT;
  384. args->size = omap_gem_mmap_size(obj);
  385. args->offset = omap_gem_mmap_offset(obj);
  386. drm_gem_object_put(obj);
  387. return ret;
  388. }
  389. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  390. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
  391. DRM_RENDER_ALLOW),
  392. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
  393. DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
  394. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
  395. DRM_RENDER_ALLOW),
  396. /* Deprecated, to be removed. */
  397. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
  398. DRM_RENDER_ALLOW),
  399. /* Deprecated, to be removed. */
  400. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
  401. DRM_RENDER_ALLOW),
  402. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
  403. DRM_RENDER_ALLOW),
  404. };
  405. /*
  406. * drm driver funcs
  407. */
  408. static int dev_open(struct drm_device *dev, struct drm_file *file)
  409. {
  410. file->driver_priv = NULL;
  411. DBG("open: dev=%p, file=%p", dev, file);
  412. return 0;
  413. }
  414. static const struct vm_operations_struct omap_gem_vm_ops = {
  415. .fault = omap_gem_fault,
  416. .open = drm_gem_vm_open,
  417. .close = drm_gem_vm_close,
  418. };
  419. static const struct file_operations omapdriver_fops = {
  420. .owner = THIS_MODULE,
  421. .open = drm_open,
  422. .unlocked_ioctl = drm_ioctl,
  423. .compat_ioctl = drm_compat_ioctl,
  424. .release = drm_release,
  425. .mmap = omap_gem_mmap,
  426. .poll = drm_poll,
  427. .read = drm_read,
  428. .llseek = noop_llseek,
  429. };
  430. static struct drm_driver omap_drm_driver = {
  431. .driver_features = DRIVER_MODESET | DRIVER_GEM |
  432. DRIVER_ATOMIC | DRIVER_RENDER,
  433. .open = dev_open,
  434. .lastclose = drm_fb_helper_lastclose,
  435. #ifdef CONFIG_DEBUG_FS
  436. .debugfs_init = omap_debugfs_init,
  437. #endif
  438. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  439. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  440. .gem_prime_export = omap_gem_prime_export,
  441. .gem_prime_import = omap_gem_prime_import,
  442. .gem_free_object_unlocked = omap_gem_free_object,
  443. .gem_vm_ops = &omap_gem_vm_ops,
  444. .dumb_create = omap_gem_dumb_create,
  445. .dumb_map_offset = omap_gem_dumb_map_offset,
  446. .ioctls = ioctls,
  447. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  448. .fops = &omapdriver_fops,
  449. .name = DRIVER_NAME,
  450. .desc = DRIVER_DESC,
  451. .date = DRIVER_DATE,
  452. .major = DRIVER_MAJOR,
  453. .minor = DRIVER_MINOR,
  454. .patchlevel = DRIVER_PATCHLEVEL,
  455. };
  456. static const struct soc_device_attribute omapdrm_soc_devices[] = {
  457. { .family = "OMAP3", .data = (void *)0x3430 },
  458. { .family = "OMAP4", .data = (void *)0x4430 },
  459. { .family = "OMAP5", .data = (void *)0x5430 },
  460. { .family = "DRA7", .data = (void *)0x0752 },
  461. { /* sentinel */ }
  462. };
  463. static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
  464. {
  465. const struct soc_device_attribute *soc;
  466. struct drm_device *ddev;
  467. int ret;
  468. DBG("%s", dev_name(dev));
  469. /* Allocate and initialize the DRM device. */
  470. ddev = drm_dev_alloc(&omap_drm_driver, dev);
  471. if (IS_ERR(ddev))
  472. return PTR_ERR(ddev);
  473. priv->ddev = ddev;
  474. ddev->dev_private = priv;
  475. priv->dev = dev;
  476. priv->dss = omapdss_get_dss();
  477. priv->dispc = dispc_get_dispc(priv->dss);
  478. priv->dispc_ops = dispc_get_ops(priv->dss);
  479. omap_crtc_pre_init(priv);
  480. soc = soc_device_match(omapdrm_soc_devices);
  481. priv->omaprev = soc ? (unsigned int)soc->data : 0;
  482. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  483. mutex_init(&priv->list_lock);
  484. INIT_LIST_HEAD(&priv->obj_list);
  485. /* Get memory bandwidth limits */
  486. if (priv->dispc_ops->get_memory_bandwidth_limit)
  487. priv->max_bandwidth =
  488. priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
  489. omap_gem_init(ddev);
  490. ret = omap_modeset_init(ddev);
  491. if (ret) {
  492. dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
  493. goto err_gem_deinit;
  494. }
  495. /* Initialize vblank handling, start with all CRTCs disabled. */
  496. ret = drm_vblank_init(ddev, priv->num_pipes);
  497. if (ret) {
  498. dev_err(priv->dev, "could not init vblank\n");
  499. goto err_cleanup_modeset;
  500. }
  501. omap_fbdev_init(ddev);
  502. drm_kms_helper_poll_init(ddev);
  503. omap_modeset_enable_external_hpd(ddev);
  504. /*
  505. * Register the DRM device with the core and the connectors with
  506. * sysfs.
  507. */
  508. ret = drm_dev_register(ddev, 0);
  509. if (ret)
  510. goto err_cleanup_helpers;
  511. return 0;
  512. err_cleanup_helpers:
  513. omap_modeset_disable_external_hpd(ddev);
  514. drm_kms_helper_poll_fini(ddev);
  515. omap_fbdev_fini(ddev);
  516. err_cleanup_modeset:
  517. omap_modeset_fini(ddev);
  518. err_gem_deinit:
  519. omap_gem_deinit(ddev);
  520. destroy_workqueue(priv->wq);
  521. omap_disconnect_pipelines(ddev);
  522. omap_crtc_pre_uninit(priv);
  523. drm_dev_put(ddev);
  524. return ret;
  525. }
  526. static void omapdrm_cleanup(struct omap_drm_private *priv)
  527. {
  528. struct drm_device *ddev = priv->ddev;
  529. DBG("");
  530. drm_dev_unregister(ddev);
  531. omap_modeset_disable_external_hpd(ddev);
  532. drm_kms_helper_poll_fini(ddev);
  533. omap_fbdev_fini(ddev);
  534. drm_atomic_helper_shutdown(ddev);
  535. omap_modeset_fini(ddev);
  536. omap_gem_deinit(ddev);
  537. destroy_workqueue(priv->wq);
  538. omap_disconnect_pipelines(ddev);
  539. omap_crtc_pre_uninit(priv);
  540. drm_dev_put(ddev);
  541. }
  542. static int pdev_probe(struct platform_device *pdev)
  543. {
  544. struct omap_drm_private *priv;
  545. int ret;
  546. if (omapdss_is_initialized() == false)
  547. return -EPROBE_DEFER;
  548. ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  549. if (ret) {
  550. dev_err(&pdev->dev, "Failed to set the DMA mask\n");
  551. return ret;
  552. }
  553. /* Allocate and initialize the driver private structure. */
  554. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  555. if (!priv)
  556. return -ENOMEM;
  557. platform_set_drvdata(pdev, priv);
  558. ret = omapdrm_init(priv, &pdev->dev);
  559. if (ret < 0)
  560. kfree(priv);
  561. return ret;
  562. }
  563. static int pdev_remove(struct platform_device *pdev)
  564. {
  565. struct omap_drm_private *priv = platform_get_drvdata(pdev);
  566. omapdrm_cleanup(priv);
  567. kfree(priv);
  568. return 0;
  569. }
  570. #ifdef CONFIG_PM_SLEEP
  571. static int omap_drm_suspend(struct device *dev)
  572. {
  573. struct omap_drm_private *priv = dev_get_drvdata(dev);
  574. struct drm_device *drm_dev = priv->ddev;
  575. return drm_mode_config_helper_suspend(drm_dev);
  576. }
  577. static int omap_drm_resume(struct device *dev)
  578. {
  579. struct omap_drm_private *priv = dev_get_drvdata(dev);
  580. struct drm_device *drm_dev = priv->ddev;
  581. drm_mode_config_helper_resume(drm_dev);
  582. return omap_gem_resume(drm_dev);
  583. }
  584. #endif
  585. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  586. static struct platform_driver pdev = {
  587. .driver = {
  588. .name = "omapdrm",
  589. .pm = &omapdrm_pm_ops,
  590. },
  591. .probe = pdev_probe,
  592. .remove = pdev_remove,
  593. };
  594. static struct platform_driver * const drivers[] = {
  595. &omap_dmm_driver,
  596. &pdev,
  597. };
  598. static int __init omap_drm_init(void)
  599. {
  600. DBG("init");
  601. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  602. }
  603. static void __exit omap_drm_fini(void)
  604. {
  605. DBG("fini");
  606. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  607. }
  608. /* need late_initcall() so we load after dss_driver's are loaded */
  609. late_initcall(omap_drm_init);
  610. module_exit(omap_drm_fini);
  611. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  612. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  613. MODULE_ALIAS("platform:" DRIVER_NAME);
  614. MODULE_LICENSE("GPL v2");