omap_crtc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  4. * Author: Rob Clark <rob@ti.com>
  5. */
  6. #include <linux/math64.h>
  7. #include <drm/drm_atomic.h>
  8. #include <drm/drm_atomic_helper.h>
  9. #include <drm/drm_crtc.h>
  10. #include <drm/drm_mode.h>
  11. #include <drm/drm_plane_helper.h>
  12. #include <drm/drm_vblank.h>
  13. #include "omap_drv.h"
  14. #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
  15. struct omap_crtc_state {
  16. /* Must be first. */
  17. struct drm_crtc_state base;
  18. /* Shadow values for legacy userspace support. */
  19. unsigned int rotation;
  20. unsigned int zpos;
  21. bool manually_updated;
  22. };
  23. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  24. struct omap_crtc {
  25. struct drm_crtc base;
  26. const char *name;
  27. struct omap_drm_pipeline *pipe;
  28. enum omap_channel channel;
  29. struct videomode vm;
  30. bool ignore_digit_sync_lost;
  31. bool enabled;
  32. bool pending;
  33. wait_queue_head_t pending_wait;
  34. struct drm_pending_vblank_event *event;
  35. struct delayed_work update_work;
  36. void (*framedone_handler)(void *);
  37. void *framedone_handler_data;
  38. };
  39. /* -----------------------------------------------------------------------------
  40. * Helper Functions
  41. */
  42. struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  43. {
  44. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  45. return &omap_crtc->vm;
  46. }
  47. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  48. {
  49. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  50. return omap_crtc->channel;
  51. }
  52. static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  53. {
  54. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  55. unsigned long flags;
  56. bool pending;
  57. spin_lock_irqsave(&crtc->dev->event_lock, flags);
  58. pending = omap_crtc->pending;
  59. spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  60. return pending;
  61. }
  62. int omap_crtc_wait_pending(struct drm_crtc *crtc)
  63. {
  64. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  65. /*
  66. * Timeout is set to a "sufficiently" high value, which should cover
  67. * a single frame refresh even on slower displays.
  68. */
  69. return wait_event_timeout(omap_crtc->pending_wait,
  70. !omap_crtc_is_pending(crtc),
  71. msecs_to_jiffies(250));
  72. }
  73. /* -----------------------------------------------------------------------------
  74. * DSS Manager Functions
  75. */
  76. /*
  77. * Manager-ops, callbacks from output when they need to configure
  78. * the upstream part of the video pipe.
  79. */
  80. static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
  81. enum omap_channel channel)
  82. {
  83. priv->dispc_ops->mgr_enable(priv->dispc, channel, true);
  84. }
  85. /* Called only from the encoder enable/disable and suspend/resume handlers. */
  86. static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
  87. {
  88. struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
  89. struct drm_device *dev = crtc->dev;
  90. struct omap_drm_private *priv = dev->dev_private;
  91. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  92. enum omap_channel channel = omap_crtc->channel;
  93. struct omap_irq_wait *wait;
  94. u32 framedone_irq, vsync_irq;
  95. int ret;
  96. if (WARN_ON(omap_crtc->enabled == enable))
  97. return;
  98. if (omap_state->manually_updated) {
  99. omap_irq_enable_framedone(crtc, enable);
  100. omap_crtc->enabled = enable;
  101. return;
  102. }
  103. if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {
  104. priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
  105. omap_crtc->enabled = enable;
  106. return;
  107. }
  108. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  109. /*
  110. * Digit output produces some sync lost interrupts during the
  111. * first frame when enabling, so we need to ignore those.
  112. */
  113. omap_crtc->ignore_digit_sync_lost = true;
  114. }
  115. framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
  116. channel);
  117. vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
  118. if (enable) {
  119. wait = omap_irq_wait_init(dev, vsync_irq, 1);
  120. } else {
  121. /*
  122. * When we disable the digit output, we need to wait for
  123. * FRAMEDONE to know that DISPC has finished with the output.
  124. *
  125. * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
  126. * that case we need to use vsync interrupt, and wait for both
  127. * even and odd frames.
  128. */
  129. if (framedone_irq)
  130. wait = omap_irq_wait_init(dev, framedone_irq, 1);
  131. else
  132. wait = omap_irq_wait_init(dev, vsync_irq, 2);
  133. }
  134. priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
  135. omap_crtc->enabled = enable;
  136. ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  137. if (ret) {
  138. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  139. omap_crtc->name, enable ? "enable" : "disable");
  140. }
  141. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  142. omap_crtc->ignore_digit_sync_lost = false;
  143. /* make sure the irq handler sees the value above */
  144. mb();
  145. }
  146. }
  147. static int omap_crtc_dss_enable(struct omap_drm_private *priv,
  148. enum omap_channel channel)
  149. {
  150. struct drm_crtc *crtc = priv->channels[channel]->crtc;
  151. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  152. priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
  153. &omap_crtc->vm);
  154. omap_crtc_set_enabled(&omap_crtc->base, true);
  155. return 0;
  156. }
  157. static void omap_crtc_dss_disable(struct omap_drm_private *priv,
  158. enum omap_channel channel)
  159. {
  160. struct drm_crtc *crtc = priv->channels[channel]->crtc;
  161. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  162. omap_crtc_set_enabled(&omap_crtc->base, false);
  163. }
  164. static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
  165. enum omap_channel channel,
  166. const struct videomode *vm)
  167. {
  168. struct drm_crtc *crtc = priv->channels[channel]->crtc;
  169. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  170. DBG("%s", omap_crtc->name);
  171. omap_crtc->vm = *vm;
  172. }
  173. static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
  174. enum omap_channel channel,
  175. const struct dss_lcd_mgr_config *config)
  176. {
  177. struct drm_crtc *crtc = priv->channels[channel]->crtc;
  178. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  179. DBG("%s", omap_crtc->name);
  180. priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
  181. config);
  182. }
  183. static int omap_crtc_dss_register_framedone(
  184. struct omap_drm_private *priv, enum omap_channel channel,
  185. void (*handler)(void *), void *data)
  186. {
  187. struct drm_crtc *crtc = priv->channels[channel]->crtc;
  188. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  189. struct drm_device *dev = omap_crtc->base.dev;
  190. if (omap_crtc->framedone_handler)
  191. return -EBUSY;
  192. dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);
  193. omap_crtc->framedone_handler = handler;
  194. omap_crtc->framedone_handler_data = data;
  195. return 0;
  196. }
  197. static void omap_crtc_dss_unregister_framedone(
  198. struct omap_drm_private *priv, enum omap_channel channel,
  199. void (*handler)(void *), void *data)
  200. {
  201. struct drm_crtc *crtc = priv->channels[channel]->crtc;
  202. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  203. struct drm_device *dev = omap_crtc->base.dev;
  204. dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);
  205. WARN_ON(omap_crtc->framedone_handler != handler);
  206. WARN_ON(omap_crtc->framedone_handler_data != data);
  207. omap_crtc->framedone_handler = NULL;
  208. omap_crtc->framedone_handler_data = NULL;
  209. }
  210. static const struct dss_mgr_ops mgr_ops = {
  211. .start_update = omap_crtc_dss_start_update,
  212. .enable = omap_crtc_dss_enable,
  213. .disable = omap_crtc_dss_disable,
  214. .set_timings = omap_crtc_dss_set_timings,
  215. .set_lcd_config = omap_crtc_dss_set_lcd_config,
  216. .register_framedone_handler = omap_crtc_dss_register_framedone,
  217. .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
  218. };
  219. /* -----------------------------------------------------------------------------
  220. * Setup, Flush and Page Flip
  221. */
  222. void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
  223. {
  224. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  225. if (omap_crtc->ignore_digit_sync_lost) {
  226. irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
  227. if (!irqstatus)
  228. return;
  229. }
  230. DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  231. }
  232. void omap_crtc_vblank_irq(struct drm_crtc *crtc)
  233. {
  234. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  235. struct drm_device *dev = omap_crtc->base.dev;
  236. struct omap_drm_private *priv = dev->dev_private;
  237. bool pending;
  238. spin_lock(&crtc->dev->event_lock);
  239. /*
  240. * If the dispc is busy we're racing the flush operation. Try again on
  241. * the next vblank interrupt.
  242. */
  243. if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
  244. spin_unlock(&crtc->dev->event_lock);
  245. return;
  246. }
  247. /* Send the vblank event if one has been requested. */
  248. if (omap_crtc->event) {
  249. drm_crtc_send_vblank_event(crtc, omap_crtc->event);
  250. omap_crtc->event = NULL;
  251. }
  252. pending = omap_crtc->pending;
  253. omap_crtc->pending = false;
  254. spin_unlock(&crtc->dev->event_lock);
  255. if (pending)
  256. drm_crtc_vblank_put(crtc);
  257. /* Wake up omap_atomic_complete. */
  258. wake_up(&omap_crtc->pending_wait);
  259. DBG("%s: apply done", omap_crtc->name);
  260. }
  261. void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus)
  262. {
  263. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  264. if (!omap_crtc->framedone_handler)
  265. return;
  266. omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);
  267. spin_lock(&crtc->dev->event_lock);
  268. /* Send the vblank event if one has been requested. */
  269. if (omap_crtc->event) {
  270. drm_crtc_send_vblank_event(crtc, omap_crtc->event);
  271. omap_crtc->event = NULL;
  272. }
  273. omap_crtc->pending = false;
  274. spin_unlock(&crtc->dev->event_lock);
  275. /* Wake up omap_atomic_complete. */
  276. wake_up(&omap_crtc->pending_wait);
  277. }
  278. void omap_crtc_flush(struct drm_crtc *crtc)
  279. {
  280. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  281. struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
  282. if (!omap_state->manually_updated)
  283. return;
  284. if (!delayed_work_pending(&omap_crtc->update_work))
  285. schedule_delayed_work(&omap_crtc->update_work, 0);
  286. }
  287. static void omap_crtc_manual_display_update(struct work_struct *data)
  288. {
  289. struct omap_crtc *omap_crtc =
  290. container_of(data, struct omap_crtc, update_work.work);
  291. struct drm_display_mode *mode = &omap_crtc->pipe->crtc->mode;
  292. struct omap_dss_device *dssdev = omap_crtc->pipe->output->next;
  293. struct drm_device *dev = omap_crtc->base.dev;
  294. const struct omap_dss_driver *dssdrv;
  295. int ret;
  296. if (!dssdev) {
  297. dev_err_once(dev->dev, "missing display dssdev!");
  298. return;
  299. }
  300. dssdrv = dssdev->driver;
  301. if (!dssdrv || !dssdrv->update) {
  302. dev_err_once(dev->dev, "missing or incorrect dssdrv!");
  303. return;
  304. }
  305. if (dssdrv->sync)
  306. dssdrv->sync(dssdev);
  307. ret = dssdrv->update(dssdev, 0, 0, mode->hdisplay, mode->vdisplay);
  308. if (ret < 0) {
  309. spin_lock_irq(&dev->event_lock);
  310. omap_crtc->pending = false;
  311. spin_unlock_irq(&dev->event_lock);
  312. wake_up(&omap_crtc->pending_wait);
  313. }
  314. }
  315. static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
  316. {
  317. struct omap_drm_private *priv = crtc->dev->dev_private;
  318. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  319. struct omap_overlay_manager_info info;
  320. memset(&info, 0, sizeof(info));
  321. info.default_color = 0x000000;
  322. info.trans_enabled = false;
  323. info.partial_alpha_enabled = false;
  324. info.cpr_enable = false;
  325. priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
  326. }
  327. /* -----------------------------------------------------------------------------
  328. * CRTC Functions
  329. */
  330. static void omap_crtc_destroy(struct drm_crtc *crtc)
  331. {
  332. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  333. DBG("%s", omap_crtc->name);
  334. drm_crtc_cleanup(crtc);
  335. kfree(omap_crtc);
  336. }
  337. static void omap_crtc_arm_event(struct drm_crtc *crtc)
  338. {
  339. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  340. WARN_ON(omap_crtc->pending);
  341. omap_crtc->pending = true;
  342. if (crtc->state->event) {
  343. omap_crtc->event = crtc->state->event;
  344. crtc->state->event = NULL;
  345. }
  346. }
  347. static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
  348. struct drm_crtc_state *old_state)
  349. {
  350. struct omap_drm_private *priv = crtc->dev->dev_private;
  351. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  352. struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
  353. int ret;
  354. DBG("%s", omap_crtc->name);
  355. priv->dispc_ops->runtime_get(priv->dispc);
  356. /* manual updated display will not trigger vsync irq */
  357. if (omap_state->manually_updated)
  358. return;
  359. drm_crtc_vblank_on(crtc);
  360. ret = drm_crtc_vblank_get(crtc);
  361. WARN_ON(ret != 0);
  362. spin_lock_irq(&crtc->dev->event_lock);
  363. omap_crtc_arm_event(crtc);
  364. spin_unlock_irq(&crtc->dev->event_lock);
  365. }
  366. static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
  367. struct drm_crtc_state *old_state)
  368. {
  369. struct omap_drm_private *priv = crtc->dev->dev_private;
  370. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  371. struct drm_device *dev = crtc->dev;
  372. DBG("%s", omap_crtc->name);
  373. spin_lock_irq(&crtc->dev->event_lock);
  374. if (crtc->state->event) {
  375. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  376. crtc->state->event = NULL;
  377. }
  378. spin_unlock_irq(&crtc->dev->event_lock);
  379. cancel_delayed_work(&omap_crtc->update_work);
  380. if (!omap_crtc_wait_pending(crtc))
  381. dev_warn(dev->dev, "manual display update did not finish!");
  382. drm_crtc_vblank_off(crtc);
  383. priv->dispc_ops->runtime_put(priv->dispc);
  384. }
  385. static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
  386. const struct drm_display_mode *mode)
  387. {
  388. struct omap_drm_private *priv = crtc->dev->dev_private;
  389. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  390. struct videomode vm = {0};
  391. int r;
  392. drm_display_mode_to_videomode(mode, &vm);
  393. /*
  394. * DSI might not call this, since the supplied mode is not a
  395. * valid DISPC mode. DSI will calculate and configure the
  396. * proper DISPC mode later.
  397. */
  398. if (omap_crtc->pipe->output->next == NULL ||
  399. omap_crtc->pipe->output->next->type != OMAP_DISPLAY_TYPE_DSI) {
  400. r = priv->dispc_ops->mgr_check_timings(priv->dispc,
  401. omap_crtc->channel,
  402. &vm);
  403. if (r)
  404. return r;
  405. }
  406. /* Check for bandwidth limit */
  407. if (priv->max_bandwidth) {
  408. /*
  409. * Estimation for the bandwidth need of a given mode with one
  410. * full screen plane:
  411. * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
  412. * ^^ Refresh rate ^^
  413. *
  414. * The interlaced mode is taken into account by using the
  415. * pixelclock in the calculation.
  416. *
  417. * The equation is rearranged for 64bit arithmetic.
  418. */
  419. uint64_t bandwidth = mode->clock * 1000;
  420. unsigned int bpp = 4;
  421. bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
  422. bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
  423. /*
  424. * Reject modes which would need more bandwidth if used with one
  425. * full resolution plane (most common use case).
  426. */
  427. if (priv->max_bandwidth < bandwidth)
  428. return MODE_BAD;
  429. }
  430. return MODE_OK;
  431. }
  432. static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
  433. {
  434. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  435. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  436. DBG("%s: set mode: " DRM_MODE_FMT,
  437. omap_crtc->name, DRM_MODE_ARG(mode));
  438. drm_display_mode_to_videomode(mode, &omap_crtc->vm);
  439. }
  440. static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc)
  441. {
  442. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  443. struct omap_dss_device *display = omap_crtc->pipe->output->next;
  444. if (!display)
  445. return false;
  446. if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
  447. DBG("detected manually updated display!");
  448. return true;
  449. }
  450. return false;
  451. }
  452. static int omap_crtc_atomic_check(struct drm_crtc *crtc,
  453. struct drm_crtc_state *state)
  454. {
  455. struct drm_plane_state *pri_state;
  456. if (state->color_mgmt_changed && state->gamma_lut) {
  457. unsigned int length = state->gamma_lut->length /
  458. sizeof(struct drm_color_lut);
  459. if (length < 2)
  460. return -EINVAL;
  461. }
  462. pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
  463. if (pri_state) {
  464. struct omap_crtc_state *omap_crtc_state =
  465. to_omap_crtc_state(state);
  466. /* Mirror new values for zpos and rotation in omap_crtc_state */
  467. omap_crtc_state->zpos = pri_state->zpos;
  468. omap_crtc_state->rotation = pri_state->rotation;
  469. /* Check if this CRTC is for a manually updated display */
  470. omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);
  471. }
  472. return 0;
  473. }
  474. static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
  475. struct drm_crtc_state *old_crtc_state)
  476. {
  477. }
  478. static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
  479. struct drm_crtc_state *old_crtc_state)
  480. {
  481. struct omap_drm_private *priv = crtc->dev->dev_private;
  482. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  483. struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);
  484. int ret;
  485. if (crtc->state->color_mgmt_changed) {
  486. struct drm_color_lut *lut = NULL;
  487. unsigned int length = 0;
  488. if (crtc->state->gamma_lut) {
  489. lut = (struct drm_color_lut *)
  490. crtc->state->gamma_lut->data;
  491. length = crtc->state->gamma_lut->length /
  492. sizeof(*lut);
  493. }
  494. priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
  495. lut, length);
  496. }
  497. omap_crtc_write_crtc_properties(crtc);
  498. /* Only flush the CRTC if it is currently enabled. */
  499. if (!omap_crtc->enabled)
  500. return;
  501. DBG("%s: GO", omap_crtc->name);
  502. if (omap_crtc_state->manually_updated) {
  503. /* send new image for page flips and modeset changes */
  504. spin_lock_irq(&crtc->dev->event_lock);
  505. omap_crtc_flush(crtc);
  506. omap_crtc_arm_event(crtc);
  507. spin_unlock_irq(&crtc->dev->event_lock);
  508. return;
  509. }
  510. ret = drm_crtc_vblank_get(crtc);
  511. WARN_ON(ret != 0);
  512. spin_lock_irq(&crtc->dev->event_lock);
  513. priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
  514. omap_crtc_arm_event(crtc);
  515. spin_unlock_irq(&crtc->dev->event_lock);
  516. }
  517. static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
  518. struct drm_crtc_state *state,
  519. struct drm_property *property,
  520. u64 val)
  521. {
  522. struct omap_drm_private *priv = crtc->dev->dev_private;
  523. struct drm_plane_state *plane_state;
  524. /*
  525. * Delegate property set to the primary plane. Get the plane state and
  526. * set the property directly, the shadow copy will be assigned in the
  527. * omap_crtc_atomic_check callback. This way updates to plane state will
  528. * always be mirrored in the crtc state correctly.
  529. */
  530. plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
  531. if (IS_ERR(plane_state))
  532. return PTR_ERR(plane_state);
  533. if (property == crtc->primary->rotation_property)
  534. plane_state->rotation = val;
  535. else if (property == priv->zorder_prop)
  536. plane_state->zpos = val;
  537. else
  538. return -EINVAL;
  539. return 0;
  540. }
  541. static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
  542. const struct drm_crtc_state *state,
  543. struct drm_property *property,
  544. u64 *val)
  545. {
  546. struct omap_drm_private *priv = crtc->dev->dev_private;
  547. struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
  548. if (property == crtc->primary->rotation_property)
  549. *val = omap_state->rotation;
  550. else if (property == priv->zorder_prop)
  551. *val = omap_state->zpos;
  552. else
  553. return -EINVAL;
  554. return 0;
  555. }
  556. static void omap_crtc_reset(struct drm_crtc *crtc)
  557. {
  558. struct omap_crtc_state *state;
  559. if (crtc->state)
  560. __drm_atomic_helper_crtc_destroy_state(crtc->state);
  561. kfree(crtc->state);
  562. state = kzalloc(sizeof(*state), GFP_KERNEL);
  563. if (state)
  564. __drm_atomic_helper_crtc_reset(crtc, &state->base);
  565. }
  566. static struct drm_crtc_state *
  567. omap_crtc_duplicate_state(struct drm_crtc *crtc)
  568. {
  569. struct omap_crtc_state *state, *current_state;
  570. if (WARN_ON(!crtc->state))
  571. return NULL;
  572. current_state = to_omap_crtc_state(crtc->state);
  573. state = kmalloc(sizeof(*state), GFP_KERNEL);
  574. if (!state)
  575. return NULL;
  576. __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
  577. state->zpos = current_state->zpos;
  578. state->rotation = current_state->rotation;
  579. state->manually_updated = current_state->manually_updated;
  580. return &state->base;
  581. }
  582. static const struct drm_crtc_funcs omap_crtc_funcs = {
  583. .reset = omap_crtc_reset,
  584. .set_config = drm_atomic_helper_set_config,
  585. .destroy = omap_crtc_destroy,
  586. .page_flip = drm_atomic_helper_page_flip,
  587. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  588. .atomic_duplicate_state = omap_crtc_duplicate_state,
  589. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  590. .atomic_set_property = omap_crtc_atomic_set_property,
  591. .atomic_get_property = omap_crtc_atomic_get_property,
  592. .enable_vblank = omap_irq_enable_vblank,
  593. .disable_vblank = omap_irq_disable_vblank,
  594. };
  595. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  596. .mode_set_nofb = omap_crtc_mode_set_nofb,
  597. .atomic_check = omap_crtc_atomic_check,
  598. .atomic_begin = omap_crtc_atomic_begin,
  599. .atomic_flush = omap_crtc_atomic_flush,
  600. .atomic_enable = omap_crtc_atomic_enable,
  601. .atomic_disable = omap_crtc_atomic_disable,
  602. .mode_valid = omap_crtc_mode_valid,
  603. };
  604. /* -----------------------------------------------------------------------------
  605. * Init and Cleanup
  606. */
  607. static const char *channel_names[] = {
  608. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  609. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  610. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  611. [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
  612. };
  613. void omap_crtc_pre_init(struct omap_drm_private *priv)
  614. {
  615. dss_install_mgr_ops(priv->dss, &mgr_ops, priv);
  616. }
  617. void omap_crtc_pre_uninit(struct omap_drm_private *priv)
  618. {
  619. dss_uninstall_mgr_ops(priv->dss);
  620. }
  621. /* initialize crtc */
  622. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  623. struct omap_drm_pipeline *pipe,
  624. struct drm_plane *plane)
  625. {
  626. struct omap_drm_private *priv = dev->dev_private;
  627. struct drm_crtc *crtc = NULL;
  628. struct omap_crtc *omap_crtc;
  629. enum omap_channel channel;
  630. int ret;
  631. channel = pipe->output->dispc_channel;
  632. DBG("%s", channel_names[channel]);
  633. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  634. if (!omap_crtc)
  635. return ERR_PTR(-ENOMEM);
  636. crtc = &omap_crtc->base;
  637. init_waitqueue_head(&omap_crtc->pending_wait);
  638. omap_crtc->pipe = pipe;
  639. omap_crtc->channel = channel;
  640. omap_crtc->name = channel_names[channel];
  641. /*
  642. * We want to refresh manually updated displays from dirty callback,
  643. * which is called quite often (e.g. for each drawn line). This will
  644. * be used to do the display update asynchronously to avoid blocking
  645. * the rendering process and merges multiple dirty calls into one
  646. * update if they arrive very fast. We also call this function for
  647. * atomic display updates (e.g. for page flips), which means we do
  648. * not need extra locking. Atomic updates should be synchronous, but
  649. * need to wait for the framedone interrupt anyways.
  650. */
  651. INIT_DELAYED_WORK(&omap_crtc->update_work,
  652. omap_crtc_manual_display_update);
  653. ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
  654. &omap_crtc_funcs, NULL);
  655. if (ret < 0) {
  656. dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
  657. __func__, pipe->output->name);
  658. kfree(omap_crtc);
  659. return ERR_PTR(ret);
  660. }
  661. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  662. /* The dispc API adapts to what ever size, but the HW supports
  663. * 256 element gamma table for LCDs and 1024 element table for
  664. * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
  665. * tables so lets use that. Size of HW gamma table can be
  666. * extracted with dispc_mgr_gamma_size(). If it returns 0
  667. * gamma table is not supported.
  668. */
  669. if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
  670. unsigned int gamma_lut_size = 256;
  671. drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
  672. drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
  673. }
  674. omap_plane_install_properties(crtc->primary, &crtc->base);
  675. return crtc;
  676. }