nv50_fence.c 3.0 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs <bskeggs@redhat.com>
  23. */
  24. #include <nvif/os.h>
  25. #include <nvif/class.h>
  26. #include <nvif/cl0002.h>
  27. #include "nouveau_drv.h"
  28. #include "nouveau_dma.h"
  29. #include "nv10_fence.h"
  30. #include "nv50_display.h"
  31. static int
  32. nv50_fence_context_new(struct nouveau_channel *chan)
  33. {
  34. struct nv10_fence_priv *priv = chan->drm->fence;
  35. struct nv10_fence_chan *fctx;
  36. struct ttm_resource *reg = &priv->bo->bo.mem;
  37. u32 start = reg->start * PAGE_SIZE;
  38. u32 limit = start + reg->size - 1;
  39. int ret;
  40. fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
  41. if (!fctx)
  42. return -ENOMEM;
  43. nouveau_fence_context_new(chan, &fctx->base);
  44. fctx->base.emit = nv10_fence_emit;
  45. fctx->base.read = nv10_fence_read;
  46. fctx->base.sync = nv17_fence_sync;
  47. ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema,
  48. NV_DMA_IN_MEMORY,
  49. &(struct nv_dma_v0) {
  50. .target = NV_DMA_V0_TARGET_VRAM,
  51. .access = NV_DMA_V0_ACCESS_RDWR,
  52. .start = start,
  53. .limit = limit,
  54. }, sizeof(struct nv_dma_v0),
  55. &fctx->sema);
  56. if (ret)
  57. nv10_fence_context_del(chan);
  58. return ret;
  59. }
  60. int
  61. nv50_fence_create(struct nouveau_drm *drm)
  62. {
  63. struct nv10_fence_priv *priv;
  64. int ret = 0;
  65. priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
  66. if (!priv)
  67. return -ENOMEM;
  68. priv->base.dtor = nv10_fence_destroy;
  69. priv->base.resume = nv17_fence_resume;
  70. priv->base.context_new = nv50_fence_context_new;
  71. priv->base.context_del = nv10_fence_context_del;
  72. spin_lock_init(&priv->lock);
  73. ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
  74. NOUVEAU_GEM_DOMAIN_VRAM,
  75. 0, 0x0000, NULL, NULL, &priv->bo);
  76. if (!ret) {
  77. ret = nouveau_bo_pin(priv->bo, NOUVEAU_GEM_DOMAIN_VRAM, false);
  78. if (!ret) {
  79. ret = nouveau_bo_map(priv->bo);
  80. if (ret)
  81. nouveau_bo_unpin(priv->bo);
  82. }
  83. if (ret)
  84. nouveau_bo_ref(NULL, &priv->bo);
  85. }
  86. if (ret) {
  87. nv10_fence_destroy(drm);
  88. return ret;
  89. }
  90. nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
  91. return ret;
  92. }