nouveau_drm.c 36 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <linux/console.h>
  25. #include <linux/delay.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/vga_switcheroo.h>
  30. #include <linux/mmu_notifier.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_ioctl.h>
  33. #include <drm/drm_vblank.h>
  34. #include <core/gpuobj.h>
  35. #include <core/option.h>
  36. #include <core/pci.h>
  37. #include <core/tegra.h>
  38. #include <nvif/driver.h>
  39. #include <nvif/fifo.h>
  40. #include <nvif/push006c.h>
  41. #include <nvif/user.h>
  42. #include <nvif/class.h>
  43. #include <nvif/cl0002.h>
  44. #include <nvif/cla06f.h>
  45. #include "nouveau_drv.h"
  46. #include "nouveau_dma.h"
  47. #include "nouveau_ttm.h"
  48. #include "nouveau_gem.h"
  49. #include "nouveau_vga.h"
  50. #include "nouveau_led.h"
  51. #include "nouveau_hwmon.h"
  52. #include "nouveau_acpi.h"
  53. #include "nouveau_bios.h"
  54. #include "nouveau_ioctl.h"
  55. #include "nouveau_abi16.h"
  56. #include "nouveau_fbcon.h"
  57. #include "nouveau_fence.h"
  58. #include "nouveau_debugfs.h"
  59. #include "nouveau_usif.h"
  60. #include "nouveau_connector.h"
  61. #include "nouveau_platform.h"
  62. #include "nouveau_svm.h"
  63. #include "nouveau_dmem.h"
  64. MODULE_PARM_DESC(config, "option string to pass to driver core");
  65. static char *nouveau_config;
  66. module_param_named(config, nouveau_config, charp, 0400);
  67. MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  68. static char *nouveau_debug;
  69. module_param_named(debug, nouveau_debug, charp, 0400);
  70. MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  71. static int nouveau_noaccel = 0;
  72. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  73. MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
  74. "0 = disabled, 1 = enabled, 2 = headless)");
  75. int nouveau_modeset = -1;
  76. module_param_named(modeset, nouveau_modeset, int, 0400);
  77. MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
  78. static int nouveau_atomic = 0;
  79. module_param_named(atomic, nouveau_atomic, int, 0400);
  80. MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
  81. static int nouveau_runtime_pm = -1;
  82. module_param_named(runpm, nouveau_runtime_pm, int, 0400);
  83. static struct drm_driver driver_stub;
  84. static struct drm_driver driver_pci;
  85. static struct drm_driver driver_platform;
  86. static u64
  87. nouveau_pci_name(struct pci_dev *pdev)
  88. {
  89. u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
  90. name |= pdev->bus->number << 16;
  91. name |= PCI_SLOT(pdev->devfn) << 8;
  92. return name | PCI_FUNC(pdev->devfn);
  93. }
  94. static u64
  95. nouveau_platform_name(struct platform_device *platformdev)
  96. {
  97. return platformdev->id;
  98. }
  99. static u64
  100. nouveau_name(struct drm_device *dev)
  101. {
  102. if (dev->pdev)
  103. return nouveau_pci_name(dev->pdev);
  104. else
  105. return nouveau_platform_name(to_platform_device(dev->dev));
  106. }
  107. static inline bool
  108. nouveau_cli_work_ready(struct dma_fence *fence)
  109. {
  110. if (!dma_fence_is_signaled(fence))
  111. return false;
  112. dma_fence_put(fence);
  113. return true;
  114. }
  115. static void
  116. nouveau_cli_work(struct work_struct *w)
  117. {
  118. struct nouveau_cli *cli = container_of(w, typeof(*cli), work);
  119. struct nouveau_cli_work *work, *wtmp;
  120. mutex_lock(&cli->lock);
  121. list_for_each_entry_safe(work, wtmp, &cli->worker, head) {
  122. if (!work->fence || nouveau_cli_work_ready(work->fence)) {
  123. list_del(&work->head);
  124. work->func(work);
  125. }
  126. }
  127. mutex_unlock(&cli->lock);
  128. }
  129. static void
  130. nouveau_cli_work_fence(struct dma_fence *fence, struct dma_fence_cb *cb)
  131. {
  132. struct nouveau_cli_work *work = container_of(cb, typeof(*work), cb);
  133. schedule_work(&work->cli->work);
  134. }
  135. void
  136. nouveau_cli_work_queue(struct nouveau_cli *cli, struct dma_fence *fence,
  137. struct nouveau_cli_work *work)
  138. {
  139. work->fence = dma_fence_get(fence);
  140. work->cli = cli;
  141. mutex_lock(&cli->lock);
  142. list_add_tail(&work->head, &cli->worker);
  143. if (dma_fence_add_callback(fence, &work->cb, nouveau_cli_work_fence))
  144. nouveau_cli_work_fence(fence, &work->cb);
  145. mutex_unlock(&cli->lock);
  146. }
  147. static void
  148. nouveau_cli_fini(struct nouveau_cli *cli)
  149. {
  150. /* All our channels are dead now, which means all the fences they
  151. * own are signalled, and all callback functions have been called.
  152. *
  153. * So, after flushing the workqueue, there should be nothing left.
  154. */
  155. flush_work(&cli->work);
  156. WARN_ON(!list_empty(&cli->worker));
  157. usif_client_fini(cli);
  158. nouveau_vmm_fini(&cli->svm);
  159. nouveau_vmm_fini(&cli->vmm);
  160. nvif_mmu_dtor(&cli->mmu);
  161. nvif_device_dtor(&cli->device);
  162. mutex_lock(&cli->drm->master.lock);
  163. nvif_client_dtor(&cli->base);
  164. mutex_unlock(&cli->drm->master.lock);
  165. }
  166. static int
  167. nouveau_cli_init(struct nouveau_drm *drm, const char *sname,
  168. struct nouveau_cli *cli)
  169. {
  170. static const struct nvif_mclass
  171. mems[] = {
  172. { NVIF_CLASS_MEM_GF100, -1 },
  173. { NVIF_CLASS_MEM_NV50 , -1 },
  174. { NVIF_CLASS_MEM_NV04 , -1 },
  175. {}
  176. };
  177. static const struct nvif_mclass
  178. mmus[] = {
  179. { NVIF_CLASS_MMU_GF100, -1 },
  180. { NVIF_CLASS_MMU_NV50 , -1 },
  181. { NVIF_CLASS_MMU_NV04 , -1 },
  182. {}
  183. };
  184. static const struct nvif_mclass
  185. vmms[] = {
  186. { NVIF_CLASS_VMM_GP100, -1 },
  187. { NVIF_CLASS_VMM_GM200, -1 },
  188. { NVIF_CLASS_VMM_GF100, -1 },
  189. { NVIF_CLASS_VMM_NV50 , -1 },
  190. { NVIF_CLASS_VMM_NV04 , -1 },
  191. {}
  192. };
  193. u64 device = nouveau_name(drm->dev);
  194. int ret;
  195. snprintf(cli->name, sizeof(cli->name), "%s", sname);
  196. cli->drm = drm;
  197. mutex_init(&cli->mutex);
  198. usif_client_init(cli);
  199. INIT_WORK(&cli->work, nouveau_cli_work);
  200. INIT_LIST_HEAD(&cli->worker);
  201. mutex_init(&cli->lock);
  202. if (cli == &drm->master) {
  203. ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug,
  204. cli->name, device, &cli->base);
  205. } else {
  206. mutex_lock(&drm->master.lock);
  207. ret = nvif_client_ctor(&drm->master.base, cli->name, device,
  208. &cli->base);
  209. mutex_unlock(&drm->master.lock);
  210. }
  211. if (ret) {
  212. NV_PRINTK(err, cli, "Client allocation failed: %d\n", ret);
  213. goto done;
  214. }
  215. ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE,
  216. &(struct nv_device_v0) {
  217. .device = ~0,
  218. }, sizeof(struct nv_device_v0),
  219. &cli->device);
  220. if (ret) {
  221. NV_PRINTK(err, cli, "Device allocation failed: %d\n", ret);
  222. goto done;
  223. }
  224. ret = nvif_mclass(&cli->device.object, mmus);
  225. if (ret < 0) {
  226. NV_PRINTK(err, cli, "No supported MMU class\n");
  227. goto done;
  228. }
  229. ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass,
  230. &cli->mmu);
  231. if (ret) {
  232. NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret);
  233. goto done;
  234. }
  235. ret = nvif_mclass(&cli->mmu.object, vmms);
  236. if (ret < 0) {
  237. NV_PRINTK(err, cli, "No supported VMM class\n");
  238. goto done;
  239. }
  240. ret = nouveau_vmm_init(cli, vmms[ret].oclass, &cli->vmm);
  241. if (ret) {
  242. NV_PRINTK(err, cli, "VMM allocation failed: %d\n", ret);
  243. goto done;
  244. }
  245. ret = nvif_mclass(&cli->mmu.object, mems);
  246. if (ret < 0) {
  247. NV_PRINTK(err, cli, "No supported MEM class\n");
  248. goto done;
  249. }
  250. cli->mem = &mems[ret];
  251. return 0;
  252. done:
  253. if (ret)
  254. nouveau_cli_fini(cli);
  255. return ret;
  256. }
  257. static void
  258. nouveau_accel_ce_fini(struct nouveau_drm *drm)
  259. {
  260. nouveau_channel_idle(drm->cechan);
  261. nvif_object_dtor(&drm->ttm.copy);
  262. nouveau_channel_del(&drm->cechan);
  263. }
  264. static void
  265. nouveau_accel_ce_init(struct nouveau_drm *drm)
  266. {
  267. struct nvif_device *device = &drm->client.device;
  268. int ret = 0;
  269. /* Allocate channel that has access to a (preferably async) copy
  270. * engine, to use for TTM buffer moves.
  271. */
  272. if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
  273. ret = nouveau_channel_new(drm, device,
  274. nvif_fifo_runlist_ce(device), 0,
  275. true, &drm->cechan);
  276. } else
  277. if (device->info.chipset >= 0xa3 &&
  278. device->info.chipset != 0xaa &&
  279. device->info.chipset != 0xac) {
  280. /* Prior to Kepler, there's only a single runlist, so all
  281. * engines can be accessed from any channel.
  282. *
  283. * We still want to use a separate channel though.
  284. */
  285. ret = nouveau_channel_new(drm, device, NvDmaFB, NvDmaTT, false,
  286. &drm->cechan);
  287. }
  288. if (ret)
  289. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  290. }
  291. static void
  292. nouveau_accel_gr_fini(struct nouveau_drm *drm)
  293. {
  294. nouveau_channel_idle(drm->channel);
  295. nvif_object_dtor(&drm->ntfy);
  296. nvkm_gpuobj_del(&drm->notify);
  297. nouveau_channel_del(&drm->channel);
  298. }
  299. static void
  300. nouveau_accel_gr_init(struct nouveau_drm *drm)
  301. {
  302. struct nvif_device *device = &drm->client.device;
  303. u32 arg0, arg1;
  304. int ret;
  305. /* Allocate channel that has access to the graphics engine. */
  306. if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
  307. arg0 = nvif_fifo_runlist(device, NV_DEVICE_INFO_ENGINE_GR);
  308. arg1 = 1;
  309. } else {
  310. arg0 = NvDmaFB;
  311. arg1 = NvDmaTT;
  312. }
  313. ret = nouveau_channel_new(drm, device, arg0, arg1, false,
  314. &drm->channel);
  315. if (ret) {
  316. NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
  317. nouveau_accel_gr_fini(drm);
  318. return;
  319. }
  320. /* A SW class is used on pre-NV50 HW to assist with handling the
  321. * synchronisation of page flips, as well as to implement fences
  322. * on TNT/TNT2 HW that lacks any kind of support in host.
  323. */
  324. if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) {
  325. ret = nvif_object_ctor(&drm->channel->user, "drmNvsw",
  326. NVDRM_NVSW, nouveau_abi16_swclass(drm),
  327. NULL, 0, &drm->channel->nvsw);
  328. if (ret == 0) {
  329. struct nvif_push *push = drm->channel->chan.push;
  330. ret = PUSH_WAIT(push, 2);
  331. if (ret == 0)
  332. PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle);
  333. }
  334. if (ret) {
  335. NV_ERROR(drm, "failed to allocate sw class, %d\n", ret);
  336. nouveau_accel_gr_fini(drm);
  337. return;
  338. }
  339. }
  340. /* NvMemoryToMemoryFormat requires a notifier ctxdma for some reason,
  341. * even if notification is never requested, so, allocate a ctxdma on
  342. * any GPU where it's possible we'll end up using M2MF for BO moves.
  343. */
  344. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  345. ret = nvkm_gpuobj_new(nvxx_device(device), 32, 0, false, NULL,
  346. &drm->notify);
  347. if (ret) {
  348. NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
  349. nouveau_accel_gr_fini(drm);
  350. return;
  351. }
  352. ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy",
  353. NvNotify0, NV_DMA_IN_MEMORY,
  354. &(struct nv_dma_v0) {
  355. .target = NV_DMA_V0_TARGET_VRAM,
  356. .access = NV_DMA_V0_ACCESS_RDWR,
  357. .start = drm->notify->addr,
  358. .limit = drm->notify->addr + 31
  359. }, sizeof(struct nv_dma_v0),
  360. &drm->ntfy);
  361. if (ret) {
  362. nouveau_accel_gr_fini(drm);
  363. return;
  364. }
  365. }
  366. }
  367. static void
  368. nouveau_accel_fini(struct nouveau_drm *drm)
  369. {
  370. nouveau_accel_ce_fini(drm);
  371. nouveau_accel_gr_fini(drm);
  372. if (drm->fence)
  373. nouveau_fence(drm)->dtor(drm);
  374. }
  375. static void
  376. nouveau_accel_init(struct nouveau_drm *drm)
  377. {
  378. struct nvif_device *device = &drm->client.device;
  379. struct nvif_sclass *sclass;
  380. int ret, i, n;
  381. if (nouveau_noaccel)
  382. return;
  383. /* Initialise global support for channels, and synchronisation. */
  384. ret = nouveau_channels_init(drm);
  385. if (ret)
  386. return;
  387. /*XXX: this is crap, but the fence/channel stuff is a little
  388. * backwards in some places. this will be fixed.
  389. */
  390. ret = n = nvif_object_sclass_get(&device->object, &sclass);
  391. if (ret < 0)
  392. return;
  393. for (ret = -ENOSYS, i = 0; i < n; i++) {
  394. switch (sclass[i].oclass) {
  395. case NV03_CHANNEL_DMA:
  396. ret = nv04_fence_create(drm);
  397. break;
  398. case NV10_CHANNEL_DMA:
  399. ret = nv10_fence_create(drm);
  400. break;
  401. case NV17_CHANNEL_DMA:
  402. case NV40_CHANNEL_DMA:
  403. ret = nv17_fence_create(drm);
  404. break;
  405. case NV50_CHANNEL_GPFIFO:
  406. ret = nv50_fence_create(drm);
  407. break;
  408. case G82_CHANNEL_GPFIFO:
  409. ret = nv84_fence_create(drm);
  410. break;
  411. case FERMI_CHANNEL_GPFIFO:
  412. case KEPLER_CHANNEL_GPFIFO_A:
  413. case KEPLER_CHANNEL_GPFIFO_B:
  414. case MAXWELL_CHANNEL_GPFIFO_A:
  415. case PASCAL_CHANNEL_GPFIFO_A:
  416. case VOLTA_CHANNEL_GPFIFO_A:
  417. case TURING_CHANNEL_GPFIFO_A:
  418. ret = nvc0_fence_create(drm);
  419. break;
  420. default:
  421. break;
  422. }
  423. }
  424. nvif_object_sclass_put(&sclass);
  425. if (ret) {
  426. NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
  427. nouveau_accel_fini(drm);
  428. return;
  429. }
  430. /* Volta requires access to a doorbell register for kickoff. */
  431. if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) {
  432. ret = nvif_user_ctor(device, "drmUsermode");
  433. if (ret)
  434. return;
  435. }
  436. /* Allocate channels we need to support various functions. */
  437. nouveau_accel_gr_init(drm);
  438. nouveau_accel_ce_init(drm);
  439. /* Initialise accelerated TTM buffer moves. */
  440. nouveau_bo_move_init(drm);
  441. }
  442. static void __printf(2, 3)
  443. nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...)
  444. {
  445. struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
  446. struct va_format vaf;
  447. va_list va;
  448. va_start(va, fmt);
  449. vaf.fmt = fmt;
  450. vaf.va = &va;
  451. NV_ERROR(drm, "%pV", &vaf);
  452. va_end(va);
  453. }
  454. static void __printf(2, 3)
  455. nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...)
  456. {
  457. struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent);
  458. struct va_format vaf;
  459. va_list va;
  460. va_start(va, fmt);
  461. vaf.fmt = fmt;
  462. vaf.va = &va;
  463. NV_DEBUG(drm, "%pV", &vaf);
  464. va_end(va);
  465. }
  466. static const struct nvif_parent_func
  467. nouveau_parent = {
  468. .debugf = nouveau_drm_debugf,
  469. .errorf = nouveau_drm_errorf,
  470. };
  471. static int
  472. nouveau_drm_device_init(struct drm_device *dev)
  473. {
  474. struct nouveau_drm *drm;
  475. int ret;
  476. if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL)))
  477. return -ENOMEM;
  478. dev->dev_private = drm;
  479. drm->dev = dev;
  480. nvif_parent_ctor(&nouveau_parent, &drm->parent);
  481. drm->master.base.object.parent = &drm->parent;
  482. ret = nouveau_cli_init(drm, "DRM-master", &drm->master);
  483. if (ret)
  484. goto fail_alloc;
  485. ret = nouveau_cli_init(drm, "DRM", &drm->client);
  486. if (ret)
  487. goto fail_master;
  488. dev->irq_enabled = true;
  489. nvxx_client(&drm->client.base)->debug =
  490. nvkm_dbgopt(nouveau_debug, "DRM");
  491. INIT_LIST_HEAD(&drm->clients);
  492. mutex_init(&drm->clients_lock);
  493. spin_lock_init(&drm->tile.lock);
  494. /* workaround an odd issue on nvc1 by disabling the device's
  495. * nosnoop capability. hopefully won't cause issues until a
  496. * better fix is found - assuming there is one...
  497. */
  498. if (drm->client.device.info.chipset == 0xc1)
  499. nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000);
  500. nouveau_vga_init(drm);
  501. ret = nouveau_ttm_init(drm);
  502. if (ret)
  503. goto fail_ttm;
  504. ret = nouveau_bios_init(dev);
  505. if (ret)
  506. goto fail_bios;
  507. nouveau_accel_init(drm);
  508. ret = nouveau_display_create(dev);
  509. if (ret)
  510. goto fail_dispctor;
  511. if (dev->mode_config.num_crtc) {
  512. ret = nouveau_display_init(dev, false, false);
  513. if (ret)
  514. goto fail_dispinit;
  515. }
  516. nouveau_debugfs_init(drm);
  517. nouveau_hwmon_init(dev);
  518. nouveau_svm_init(drm);
  519. nouveau_dmem_init(drm);
  520. nouveau_fbcon_init(dev);
  521. nouveau_led_init(dev);
  522. if (nouveau_pmops_runtime()) {
  523. pm_runtime_use_autosuspend(dev->dev);
  524. pm_runtime_set_autosuspend_delay(dev->dev, 5000);
  525. pm_runtime_set_active(dev->dev);
  526. pm_runtime_allow(dev->dev);
  527. pm_runtime_mark_last_busy(dev->dev);
  528. pm_runtime_put(dev->dev);
  529. }
  530. return 0;
  531. fail_dispinit:
  532. nouveau_display_destroy(dev);
  533. fail_dispctor:
  534. nouveau_accel_fini(drm);
  535. nouveau_bios_takedown(dev);
  536. fail_bios:
  537. nouveau_ttm_fini(drm);
  538. fail_ttm:
  539. nouveau_vga_fini(drm);
  540. nouveau_cli_fini(&drm->client);
  541. fail_master:
  542. nouveau_cli_fini(&drm->master);
  543. fail_alloc:
  544. nvif_parent_dtor(&drm->parent);
  545. kfree(drm);
  546. return ret;
  547. }
  548. static void
  549. nouveau_drm_device_fini(struct drm_device *dev)
  550. {
  551. struct nouveau_cli *cli, *temp_cli;
  552. struct nouveau_drm *drm = nouveau_drm(dev);
  553. if (nouveau_pmops_runtime()) {
  554. pm_runtime_get_sync(dev->dev);
  555. pm_runtime_forbid(dev->dev);
  556. }
  557. nouveau_led_fini(dev);
  558. nouveau_fbcon_fini(dev);
  559. nouveau_dmem_fini(drm);
  560. nouveau_svm_fini(drm);
  561. nouveau_hwmon_fini(dev);
  562. nouveau_debugfs_fini(drm);
  563. if (dev->mode_config.num_crtc)
  564. nouveau_display_fini(dev, false, false);
  565. nouveau_display_destroy(dev);
  566. nouveau_accel_fini(drm);
  567. nouveau_bios_takedown(dev);
  568. nouveau_ttm_fini(drm);
  569. nouveau_vga_fini(drm);
  570. /*
  571. * There may be existing clients from as-yet unclosed files. For now,
  572. * clean them up here rather than deferring until the file is closed,
  573. * but this likely not correct if we want to support hot-unplugging
  574. * properly.
  575. */
  576. mutex_lock(&drm->clients_lock);
  577. list_for_each_entry_safe(cli, temp_cli, &drm->clients, head) {
  578. list_del(&cli->head);
  579. mutex_lock(&cli->mutex);
  580. if (cli->abi16)
  581. nouveau_abi16_fini(cli->abi16);
  582. mutex_unlock(&cli->mutex);
  583. nouveau_cli_fini(cli);
  584. kfree(cli);
  585. }
  586. mutex_unlock(&drm->clients_lock);
  587. nouveau_cli_fini(&drm->client);
  588. nouveau_cli_fini(&drm->master);
  589. nvif_parent_dtor(&drm->parent);
  590. mutex_destroy(&drm->clients_lock);
  591. kfree(drm);
  592. }
  593. /*
  594. * On some Intel PCIe bridge controllers doing a
  595. * D0 -> D3hot -> D3cold -> D0 sequence causes Nvidia GPUs to not reappear.
  596. * Skipping the intermediate D3hot step seems to make it work again. This is
  597. * probably caused by not meeting the expectation the involved AML code has
  598. * when the GPU is put into D3hot state before invoking it.
  599. *
  600. * This leads to various manifestations of this issue:
  601. * - AML code execution to power on the GPU hits an infinite loop (as the
  602. * code waits on device memory to change).
  603. * - kernel crashes, as all PCI reads return -1, which most code isn't able
  604. * to handle well enough.
  605. *
  606. * In all cases dmesg will contain at least one line like this:
  607. * 'nouveau 0000:01:00.0: Refused to change power state, currently in D3'
  608. * followed by a lot of nouveau timeouts.
  609. *
  610. * In the \_SB.PCI0.PEG0.PG00._OFF code deeper down writes bit 0x80 to the not
  611. * documented PCI config space register 0x248 of the Intel PCIe bridge
  612. * controller (0x1901) in order to change the state of the PCIe link between
  613. * the PCIe port and the GPU. There are alternative code paths using other
  614. * registers, which seem to work fine (executed pre Windows 8):
  615. * - 0xbc bit 0x20 (publicly available documentation claims 'reserved')
  616. * - 0xb0 bit 0x10 (link disable)
  617. * Changing the conditions inside the firmware by poking into the relevant
  618. * addresses does resolve the issue, but it seemed to be ACPI private memory
  619. * and not any device accessible memory at all, so there is no portable way of
  620. * changing the conditions.
  621. * On a XPS 9560 that means bits [0,3] on \CPEX need to be cleared.
  622. *
  623. * The only systems where this behavior can be seen are hybrid graphics laptops
  624. * with a secondary Nvidia Maxwell, Pascal or Turing GPU. It's unclear whether
  625. * this issue only occurs in combination with listed Intel PCIe bridge
  626. * controllers and the mentioned GPUs or other devices as well.
  627. *
  628. * documentation on the PCIe bridge controller can be found in the
  629. * "7th Generation Intel® Processor Families for H Platforms Datasheet Volume 2"
  630. * Section "12 PCI Express* Controller (x16) Registers"
  631. */
  632. static void quirk_broken_nv_runpm(struct pci_dev *pdev)
  633. {
  634. struct drm_device *dev = pci_get_drvdata(pdev);
  635. struct nouveau_drm *drm = nouveau_drm(dev);
  636. struct pci_dev *bridge = pci_upstream_bridge(pdev);
  637. if (!bridge || bridge->vendor != PCI_VENDOR_ID_INTEL)
  638. return;
  639. switch (bridge->device) {
  640. case 0x1901:
  641. drm->old_pm_cap = pdev->pm_cap;
  642. pdev->pm_cap = 0;
  643. NV_INFO(drm, "Disabling PCI power management to avoid bug\n");
  644. break;
  645. }
  646. }
  647. static int nouveau_drm_probe(struct pci_dev *pdev,
  648. const struct pci_device_id *pent)
  649. {
  650. struct nvkm_device *device;
  651. struct drm_device *drm_dev;
  652. int ret;
  653. if (vga_switcheroo_client_probe_defer(pdev))
  654. return -EPROBE_DEFER;
  655. /* We need to check that the chipset is supported before booting
  656. * fbdev off the hardware, as there's no way to put it back.
  657. */
  658. ret = nvkm_device_pci_new(pdev, nouveau_config, "error",
  659. true, false, 0, &device);
  660. if (ret)
  661. return ret;
  662. nvkm_device_del(&device);
  663. /* Remove conflicting drivers (vesafb, efifb etc). */
  664. ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "nouveaufb");
  665. if (ret)
  666. return ret;
  667. ret = nvkm_device_pci_new(pdev, nouveau_config, nouveau_debug,
  668. true, true, ~0ULL, &device);
  669. if (ret)
  670. return ret;
  671. pci_set_master(pdev);
  672. if (nouveau_atomic)
  673. driver_pci.driver_features |= DRIVER_ATOMIC;
  674. drm_dev = drm_dev_alloc(&driver_pci, &pdev->dev);
  675. if (IS_ERR(drm_dev)) {
  676. ret = PTR_ERR(drm_dev);
  677. goto fail_nvkm;
  678. }
  679. ret = pci_enable_device(pdev);
  680. if (ret)
  681. goto fail_drm;
  682. drm_dev->pdev = pdev;
  683. pci_set_drvdata(pdev, drm_dev);
  684. ret = nouveau_drm_device_init(drm_dev);
  685. if (ret)
  686. goto fail_pci;
  687. ret = drm_dev_register(drm_dev, pent->driver_data);
  688. if (ret)
  689. goto fail_drm_dev_init;
  690. quirk_broken_nv_runpm(pdev);
  691. return 0;
  692. fail_drm_dev_init:
  693. nouveau_drm_device_fini(drm_dev);
  694. fail_pci:
  695. pci_disable_device(pdev);
  696. fail_drm:
  697. drm_dev_put(drm_dev);
  698. fail_nvkm:
  699. nvkm_device_del(&device);
  700. return ret;
  701. }
  702. void
  703. nouveau_drm_device_remove(struct drm_device *dev)
  704. {
  705. struct nouveau_drm *drm = nouveau_drm(dev);
  706. struct nvkm_client *client;
  707. struct nvkm_device *device;
  708. drm_dev_unplug(dev);
  709. dev->irq_enabled = false;
  710. client = nvxx_client(&drm->client.base);
  711. device = nvkm_device_find(client->device);
  712. nouveau_drm_device_fini(dev);
  713. drm_dev_put(dev);
  714. nvkm_device_del(&device);
  715. }
  716. static void
  717. nouveau_drm_remove(struct pci_dev *pdev)
  718. {
  719. struct drm_device *dev = pci_get_drvdata(pdev);
  720. struct nouveau_drm *drm = nouveau_drm(dev);
  721. /* revert our workaround */
  722. if (drm->old_pm_cap)
  723. pdev->pm_cap = drm->old_pm_cap;
  724. nouveau_drm_device_remove(dev);
  725. pci_disable_device(pdev);
  726. }
  727. static int
  728. nouveau_do_suspend(struct drm_device *dev, bool runtime)
  729. {
  730. struct nouveau_drm *drm = nouveau_drm(dev);
  731. int ret;
  732. nouveau_svm_suspend(drm);
  733. nouveau_dmem_suspend(drm);
  734. nouveau_led_suspend(dev);
  735. if (dev->mode_config.num_crtc) {
  736. NV_DEBUG(drm, "suspending console...\n");
  737. nouveau_fbcon_set_suspend(dev, 1);
  738. NV_DEBUG(drm, "suspending display...\n");
  739. ret = nouveau_display_suspend(dev, runtime);
  740. if (ret)
  741. return ret;
  742. }
  743. NV_DEBUG(drm, "evicting buffers...\n");
  744. ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
  745. NV_DEBUG(drm, "waiting for kernel channels to go idle...\n");
  746. if (drm->cechan) {
  747. ret = nouveau_channel_idle(drm->cechan);
  748. if (ret)
  749. goto fail_display;
  750. }
  751. if (drm->channel) {
  752. ret = nouveau_channel_idle(drm->channel);
  753. if (ret)
  754. goto fail_display;
  755. }
  756. NV_DEBUG(drm, "suspending fence...\n");
  757. if (drm->fence && nouveau_fence(drm)->suspend) {
  758. if (!nouveau_fence(drm)->suspend(drm)) {
  759. ret = -ENOMEM;
  760. goto fail_display;
  761. }
  762. }
  763. NV_DEBUG(drm, "suspending object tree...\n");
  764. ret = nvif_client_suspend(&drm->master.base);
  765. if (ret)
  766. goto fail_client;
  767. return 0;
  768. fail_client:
  769. if (drm->fence && nouveau_fence(drm)->resume)
  770. nouveau_fence(drm)->resume(drm);
  771. fail_display:
  772. if (dev->mode_config.num_crtc) {
  773. NV_DEBUG(drm, "resuming display...\n");
  774. nouveau_display_resume(dev, runtime);
  775. }
  776. return ret;
  777. }
  778. static int
  779. nouveau_do_resume(struct drm_device *dev, bool runtime)
  780. {
  781. int ret = 0;
  782. struct nouveau_drm *drm = nouveau_drm(dev);
  783. NV_DEBUG(drm, "resuming object tree...\n");
  784. ret = nvif_client_resume(&drm->master.base);
  785. if (ret) {
  786. NV_ERROR(drm, "Client resume failed with error: %d\n", ret);
  787. return ret;
  788. }
  789. NV_DEBUG(drm, "resuming fence...\n");
  790. if (drm->fence && nouveau_fence(drm)->resume)
  791. nouveau_fence(drm)->resume(drm);
  792. nouveau_run_vbios_init(dev);
  793. if (dev->mode_config.num_crtc) {
  794. NV_DEBUG(drm, "resuming display...\n");
  795. nouveau_display_resume(dev, runtime);
  796. NV_DEBUG(drm, "resuming console...\n");
  797. nouveau_fbcon_set_suspend(dev, 0);
  798. }
  799. nouveau_led_resume(dev);
  800. nouveau_dmem_resume(drm);
  801. nouveau_svm_resume(drm);
  802. return 0;
  803. }
  804. int
  805. nouveau_pmops_suspend(struct device *dev)
  806. {
  807. struct pci_dev *pdev = to_pci_dev(dev);
  808. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  809. int ret;
  810. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  811. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  812. return 0;
  813. ret = nouveau_do_suspend(drm_dev, false);
  814. if (ret)
  815. return ret;
  816. pci_save_state(pdev);
  817. pci_disable_device(pdev);
  818. pci_set_power_state(pdev, PCI_D3hot);
  819. udelay(200);
  820. return 0;
  821. }
  822. int
  823. nouveau_pmops_resume(struct device *dev)
  824. {
  825. struct pci_dev *pdev = to_pci_dev(dev);
  826. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  827. int ret;
  828. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  829. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  830. return 0;
  831. pci_set_power_state(pdev, PCI_D0);
  832. pci_restore_state(pdev);
  833. ret = pci_enable_device(pdev);
  834. if (ret)
  835. return ret;
  836. pci_set_master(pdev);
  837. ret = nouveau_do_resume(drm_dev, false);
  838. /* Monitors may have been connected / disconnected during suspend */
  839. nouveau_display_hpd_resume(drm_dev);
  840. return ret;
  841. }
  842. static int
  843. nouveau_pmops_freeze(struct device *dev)
  844. {
  845. struct pci_dev *pdev = to_pci_dev(dev);
  846. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  847. return nouveau_do_suspend(drm_dev, false);
  848. }
  849. static int
  850. nouveau_pmops_thaw(struct device *dev)
  851. {
  852. struct pci_dev *pdev = to_pci_dev(dev);
  853. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  854. return nouveau_do_resume(drm_dev, false);
  855. }
  856. bool
  857. nouveau_pmops_runtime(void)
  858. {
  859. if (nouveau_runtime_pm == -1)
  860. return nouveau_is_optimus() || nouveau_is_v1_dsm();
  861. return nouveau_runtime_pm == 1;
  862. }
  863. static int
  864. nouveau_pmops_runtime_suspend(struct device *dev)
  865. {
  866. struct pci_dev *pdev = to_pci_dev(dev);
  867. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  868. int ret;
  869. if (!nouveau_pmops_runtime()) {
  870. pm_runtime_forbid(dev);
  871. return -EBUSY;
  872. }
  873. nouveau_switcheroo_optimus_dsm();
  874. ret = nouveau_do_suspend(drm_dev, true);
  875. pci_save_state(pdev);
  876. pci_disable_device(pdev);
  877. pci_ignore_hotplug(pdev);
  878. pci_set_power_state(pdev, PCI_D3cold);
  879. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  880. return ret;
  881. }
  882. static int
  883. nouveau_pmops_runtime_resume(struct device *dev)
  884. {
  885. struct pci_dev *pdev = to_pci_dev(dev);
  886. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  887. struct nouveau_drm *drm = nouveau_drm(drm_dev);
  888. struct nvif_device *device = &nouveau_drm(drm_dev)->client.device;
  889. int ret;
  890. if (!nouveau_pmops_runtime()) {
  891. pm_runtime_forbid(dev);
  892. return -EBUSY;
  893. }
  894. pci_set_power_state(pdev, PCI_D0);
  895. pci_restore_state(pdev);
  896. ret = pci_enable_device(pdev);
  897. if (ret)
  898. return ret;
  899. pci_set_master(pdev);
  900. ret = nouveau_do_resume(drm_dev, true);
  901. if (ret) {
  902. NV_ERROR(drm, "resume failed with: %d\n", ret);
  903. return ret;
  904. }
  905. /* do magic */
  906. nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
  907. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  908. /* Monitors may have been connected / disconnected during suspend */
  909. nouveau_display_hpd_resume(drm_dev);
  910. return ret;
  911. }
  912. static int
  913. nouveau_pmops_runtime_idle(struct device *dev)
  914. {
  915. if (!nouveau_pmops_runtime()) {
  916. pm_runtime_forbid(dev);
  917. return -EBUSY;
  918. }
  919. pm_runtime_mark_last_busy(dev);
  920. pm_runtime_autosuspend(dev);
  921. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  922. return 1;
  923. }
  924. static int
  925. nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
  926. {
  927. struct nouveau_drm *drm = nouveau_drm(dev);
  928. struct nouveau_cli *cli;
  929. char name[32], tmpname[TASK_COMM_LEN];
  930. int ret;
  931. /* need to bring up power immediately if opening device */
  932. ret = pm_runtime_get_sync(dev->dev);
  933. if (ret < 0 && ret != -EACCES) {
  934. pm_runtime_put_autosuspend(dev->dev);
  935. return ret;
  936. }
  937. get_task_comm(tmpname, current);
  938. snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
  939. if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) {
  940. ret = -ENOMEM;
  941. goto done;
  942. }
  943. ret = nouveau_cli_init(drm, name, cli);
  944. if (ret)
  945. goto done;
  946. cli->base.super = false;
  947. fpriv->driver_priv = cli;
  948. mutex_lock(&drm->clients_lock);
  949. list_add(&cli->head, &drm->clients);
  950. mutex_unlock(&drm->clients_lock);
  951. done:
  952. if (ret && cli) {
  953. nouveau_cli_fini(cli);
  954. kfree(cli);
  955. }
  956. pm_runtime_mark_last_busy(dev->dev);
  957. pm_runtime_put_autosuspend(dev->dev);
  958. return ret;
  959. }
  960. static void
  961. nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
  962. {
  963. struct nouveau_cli *cli = nouveau_cli(fpriv);
  964. struct nouveau_drm *drm = nouveau_drm(dev);
  965. int dev_index;
  966. /*
  967. * The device is gone, and as it currently stands all clients are
  968. * cleaned up in the removal codepath. In the future this may change
  969. * so that we can support hot-unplugging, but for now we immediately
  970. * return to avoid a double-free situation.
  971. */
  972. if (!drm_dev_enter(dev, &dev_index))
  973. return;
  974. pm_runtime_get_sync(dev->dev);
  975. mutex_lock(&cli->mutex);
  976. if (cli->abi16)
  977. nouveau_abi16_fini(cli->abi16);
  978. mutex_unlock(&cli->mutex);
  979. mutex_lock(&drm->clients_lock);
  980. list_del(&cli->head);
  981. mutex_unlock(&drm->clients_lock);
  982. nouveau_cli_fini(cli);
  983. kfree(cli);
  984. pm_runtime_mark_last_busy(dev->dev);
  985. pm_runtime_put_autosuspend(dev->dev);
  986. drm_dev_exit(dev_index);
  987. }
  988. static const struct drm_ioctl_desc
  989. nouveau_ioctls[] = {
  990. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
  991. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  992. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
  993. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
  994. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
  995. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
  996. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
  997. DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
  998. DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
  999. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
  1000. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
  1001. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
  1002. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
  1003. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
  1004. };
  1005. long
  1006. nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1007. {
  1008. struct drm_file *filp = file->private_data;
  1009. struct drm_device *dev = filp->minor->dev;
  1010. long ret;
  1011. ret = pm_runtime_get_sync(dev->dev);
  1012. if (ret < 0 && ret != -EACCES) {
  1013. pm_runtime_put_autosuspend(dev->dev);
  1014. return ret;
  1015. }
  1016. switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
  1017. case DRM_NOUVEAU_NVIF:
  1018. ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
  1019. break;
  1020. default:
  1021. ret = drm_ioctl(file, cmd, arg);
  1022. break;
  1023. }
  1024. pm_runtime_mark_last_busy(dev->dev);
  1025. pm_runtime_put_autosuspend(dev->dev);
  1026. return ret;
  1027. }
  1028. static const struct file_operations
  1029. nouveau_driver_fops = {
  1030. .owner = THIS_MODULE,
  1031. .open = drm_open,
  1032. .release = drm_release,
  1033. .unlocked_ioctl = nouveau_drm_ioctl,
  1034. .mmap = nouveau_ttm_mmap,
  1035. .poll = drm_poll,
  1036. .read = drm_read,
  1037. #if defined(CONFIG_COMPAT)
  1038. .compat_ioctl = nouveau_compat_ioctl,
  1039. #endif
  1040. .llseek = noop_llseek,
  1041. };
  1042. static struct drm_driver
  1043. driver_stub = {
  1044. .driver_features =
  1045. DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
  1046. #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
  1047. | DRIVER_KMS_LEGACY_CONTEXT
  1048. #endif
  1049. ,
  1050. .open = nouveau_drm_open,
  1051. .postclose = nouveau_drm_postclose,
  1052. .lastclose = nouveau_vga_lastclose,
  1053. #if defined(CONFIG_DEBUG_FS)
  1054. .debugfs_init = nouveau_drm_debugfs_init,
  1055. #endif
  1056. .ioctls = nouveau_ioctls,
  1057. .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
  1058. .fops = &nouveau_driver_fops,
  1059. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  1060. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  1061. .gem_prime_pin = nouveau_gem_prime_pin,
  1062. .gem_prime_unpin = nouveau_gem_prime_unpin,
  1063. .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
  1064. .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
  1065. .gem_prime_vmap = nouveau_gem_prime_vmap,
  1066. .gem_prime_vunmap = nouveau_gem_prime_vunmap,
  1067. .gem_free_object_unlocked = nouveau_gem_object_del,
  1068. .gem_open_object = nouveau_gem_object_open,
  1069. .gem_close_object = nouveau_gem_object_close,
  1070. .dumb_create = nouveau_display_dumb_create,
  1071. .dumb_map_offset = nouveau_display_dumb_map_offset,
  1072. .name = DRIVER_NAME,
  1073. .desc = DRIVER_DESC,
  1074. #ifdef GIT_REVISION
  1075. .date = GIT_REVISION,
  1076. #else
  1077. .date = DRIVER_DATE,
  1078. #endif
  1079. .major = DRIVER_MAJOR,
  1080. .minor = DRIVER_MINOR,
  1081. .patchlevel = DRIVER_PATCHLEVEL,
  1082. };
  1083. static struct pci_device_id
  1084. nouveau_drm_pci_table[] = {
  1085. {
  1086. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  1087. .class = PCI_BASE_CLASS_DISPLAY << 16,
  1088. .class_mask = 0xff << 16,
  1089. },
  1090. {
  1091. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  1092. .class = PCI_BASE_CLASS_DISPLAY << 16,
  1093. .class_mask = 0xff << 16,
  1094. },
  1095. {}
  1096. };
  1097. static void nouveau_display_options(void)
  1098. {
  1099. DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
  1100. DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
  1101. DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
  1102. DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
  1103. DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
  1104. DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
  1105. DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
  1106. DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
  1107. DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
  1108. DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
  1109. DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
  1110. DRM_DEBUG_DRIVER("... hdmimhz : %d\n", nouveau_hdmimhz);
  1111. }
  1112. static const struct dev_pm_ops nouveau_pm_ops = {
  1113. .suspend = nouveau_pmops_suspend,
  1114. .resume = nouveau_pmops_resume,
  1115. .freeze = nouveau_pmops_freeze,
  1116. .thaw = nouveau_pmops_thaw,
  1117. .poweroff = nouveau_pmops_freeze,
  1118. .restore = nouveau_pmops_resume,
  1119. .runtime_suspend = nouveau_pmops_runtime_suspend,
  1120. .runtime_resume = nouveau_pmops_runtime_resume,
  1121. .runtime_idle = nouveau_pmops_runtime_idle,
  1122. };
  1123. static struct pci_driver
  1124. nouveau_drm_pci_driver = {
  1125. .name = "nouveau",
  1126. .id_table = nouveau_drm_pci_table,
  1127. .probe = nouveau_drm_probe,
  1128. .remove = nouveau_drm_remove,
  1129. .driver.pm = &nouveau_pm_ops,
  1130. };
  1131. struct drm_device *
  1132. nouveau_platform_device_create(const struct nvkm_device_tegra_func *func,
  1133. struct platform_device *pdev,
  1134. struct nvkm_device **pdevice)
  1135. {
  1136. struct drm_device *drm;
  1137. int err;
  1138. err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug,
  1139. true, true, ~0ULL, pdevice);
  1140. if (err)
  1141. goto err_free;
  1142. drm = drm_dev_alloc(&driver_platform, &pdev->dev);
  1143. if (IS_ERR(drm)) {
  1144. err = PTR_ERR(drm);
  1145. goto err_free;
  1146. }
  1147. err = nouveau_drm_device_init(drm);
  1148. if (err)
  1149. goto err_put;
  1150. platform_set_drvdata(pdev, drm);
  1151. return drm;
  1152. err_put:
  1153. drm_dev_put(drm);
  1154. err_free:
  1155. nvkm_device_del(pdevice);
  1156. return ERR_PTR(err);
  1157. }
  1158. static int __init
  1159. nouveau_drm_init(void)
  1160. {
  1161. driver_pci = driver_stub;
  1162. driver_platform = driver_stub;
  1163. nouveau_display_options();
  1164. if (nouveau_modeset == -1) {
  1165. if (vgacon_text_force())
  1166. nouveau_modeset = 0;
  1167. }
  1168. if (!nouveau_modeset)
  1169. return 0;
  1170. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  1171. platform_driver_register(&nouveau_platform_driver);
  1172. #endif
  1173. nouveau_register_dsm_handler();
  1174. nouveau_backlight_ctor();
  1175. #ifdef CONFIG_PCI
  1176. return pci_register_driver(&nouveau_drm_pci_driver);
  1177. #else
  1178. return 0;
  1179. #endif
  1180. }
  1181. static void __exit
  1182. nouveau_drm_exit(void)
  1183. {
  1184. if (!nouveau_modeset)
  1185. return;
  1186. #ifdef CONFIG_PCI
  1187. pci_unregister_driver(&nouveau_drm_pci_driver);
  1188. #endif
  1189. nouveau_backlight_dtor();
  1190. nouveau_unregister_dsm_handler();
  1191. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  1192. platform_driver_unregister(&nouveau_platform_driver);
  1193. #endif
  1194. if (IS_ENABLED(CONFIG_DRM_NOUVEAU_SVM))
  1195. mmu_notifier_synchronize();
  1196. }
  1197. module_init(nouveau_drm_init);
  1198. module_exit(nouveau_drm_exit);
  1199. MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
  1200. MODULE_AUTHOR(DRIVER_AUTHOR);
  1201. MODULE_DESCRIPTION(DRIVER_DESC);
  1202. MODULE_LICENSE("GPL and additional rights");