nouveau_dma.h 3.5 KB

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  1. /*
  2. * Copyright (C) 2007 Ben Skeggs.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #ifndef __NOUVEAU_DMA_H__
  27. #define __NOUVEAU_DMA_H__
  28. #include "nouveau_bo.h"
  29. #include "nouveau_chan.h"
  30. int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
  31. void nv50_dma_push(struct nouveau_channel *, u64 addr, int length);
  32. /*
  33. * There's a hw race condition where you can't jump to your PUT offset,
  34. * to avoid this we jump to offset + SKIPS and fill the difference with
  35. * NOPs.
  36. *
  37. * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
  38. * a SKIPS value of 8. Lets assume that the race condition is to do
  39. * with writing into the fetch area, we configure a fetch size of 128
  40. * bytes so we need a larger SKIPS value.
  41. */
  42. #define NOUVEAU_DMA_SKIPS (128 / 4)
  43. /* Object handles - for stuff that's doesn't use handle == oclass. */
  44. enum {
  45. NvDmaFB = 0x80000002,
  46. NvDmaTT = 0x80000003,
  47. NvNotify0 = 0x80000006,
  48. NvSema = 0x8000000f,
  49. NvEvoSema0 = 0x80000010,
  50. NvEvoSema1 = 0x80000011,
  51. };
  52. static __must_check inline int
  53. RING_SPACE(struct nouveau_channel *chan, int size)
  54. {
  55. int ret;
  56. ret = nouveau_dma_wait(chan, 1, size);
  57. if (ret)
  58. return ret;
  59. chan->dma.free -= size;
  60. return 0;
  61. }
  62. static inline void
  63. OUT_RING(struct nouveau_channel *chan, int data)
  64. {
  65. nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
  66. }
  67. #define WRITE_PUT(val) do { \
  68. mb(); \
  69. nouveau_bo_rd32(chan->push.buffer, 0); \
  70. nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\
  71. } while (0)
  72. static inline void
  73. FIRE_RING(struct nouveau_channel *chan)
  74. {
  75. if (chan->dma.cur == chan->dma.put)
  76. return;
  77. chan->accel_done = true;
  78. if (chan->dma.ib_max) {
  79. nv50_dma_push(chan, chan->push.addr + (chan->dma.put << 2),
  80. (chan->dma.cur - chan->dma.put) << 2);
  81. } else {
  82. WRITE_PUT(chan->dma.cur);
  83. }
  84. chan->dma.put = chan->dma.cur;
  85. }
  86. static inline void
  87. WIND_RING(struct nouveau_channel *chan)
  88. {
  89. chan->dma.cur = chan->dma.put;
  90. }
  91. /* NV_SW object class */
  92. #define NV_SW_DMA_VBLSEM 0x0000018c
  93. #define NV_SW_VBLSEM_OFFSET 0x00000400
  94. #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
  95. #define NV_SW_VBLSEM_RELEASE 0x00000408
  96. #define NV_SW_PAGE_FLIP 0x00000500
  97. #endif