nouveau_chan.c 16 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <nvif/push006c.h>
  25. #include <nvif/class.h>
  26. #include <nvif/cl0002.h>
  27. #include <nvif/cl006b.h>
  28. #include <nvif/cl506f.h>
  29. #include <nvif/cl906f.h>
  30. #include <nvif/cla06f.h>
  31. #include <nvif/clc36f.h>
  32. #include <nvif/ioctl.h>
  33. #include "nouveau_drv.h"
  34. #include "nouveau_dma.h"
  35. #include "nouveau_bo.h"
  36. #include "nouveau_chan.h"
  37. #include "nouveau_fence.h"
  38. #include "nouveau_abi16.h"
  39. #include "nouveau_vmm.h"
  40. #include "nouveau_svm.h"
  41. MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
  42. int nouveau_vram_pushbuf;
  43. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  44. static int
  45. nouveau_channel_killed(struct nvif_notify *ntfy)
  46. {
  47. struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill);
  48. struct nouveau_cli *cli = (void *)chan->user.client;
  49. NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
  50. atomic_set(&chan->killed, 1);
  51. if (chan->fence)
  52. nouveau_fence_context_kill(chan->fence, -ENODEV);
  53. return NVIF_NOTIFY_DROP;
  54. }
  55. int
  56. nouveau_channel_idle(struct nouveau_channel *chan)
  57. {
  58. if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
  59. struct nouveau_cli *cli = (void *)chan->user.client;
  60. struct nouveau_fence *fence = NULL;
  61. int ret;
  62. ret = nouveau_fence_new(chan, false, &fence);
  63. if (!ret) {
  64. ret = nouveau_fence_wait(fence, false, false);
  65. nouveau_fence_unref(&fence);
  66. }
  67. if (ret) {
  68. NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
  69. chan->chid, nvxx_client(&cli->base)->name);
  70. return ret;
  71. }
  72. }
  73. return 0;
  74. }
  75. void
  76. nouveau_channel_del(struct nouveau_channel **pchan)
  77. {
  78. struct nouveau_channel *chan = *pchan;
  79. if (chan) {
  80. struct nouveau_cli *cli = (void *)chan->user.client;
  81. bool super;
  82. if (cli) {
  83. super = cli->base.super;
  84. cli->base.super = true;
  85. }
  86. if (chan->fence)
  87. nouveau_fence(chan->drm)->context_del(chan);
  88. if (cli)
  89. nouveau_svmm_part(chan->vmm->svmm, chan->inst);
  90. nvif_object_dtor(&chan->nvsw);
  91. nvif_object_dtor(&chan->gart);
  92. nvif_object_dtor(&chan->vram);
  93. nvif_notify_dtor(&chan->kill);
  94. nvif_object_dtor(&chan->user);
  95. nvif_object_dtor(&chan->push.ctxdma);
  96. nouveau_vma_del(&chan->push.vma);
  97. nouveau_bo_unmap(chan->push.buffer);
  98. if (chan->push.buffer && chan->push.buffer->pin_refcnt)
  99. nouveau_bo_unpin(chan->push.buffer);
  100. nouveau_bo_ref(NULL, &chan->push.buffer);
  101. kfree(chan);
  102. if (cli)
  103. cli->base.super = super;
  104. }
  105. *pchan = NULL;
  106. }
  107. static void
  108. nouveau_channel_kick(struct nvif_push *push)
  109. {
  110. struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
  111. chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
  112. FIRE_RING(chan);
  113. chan->chan._push.bgn = chan->chan._push.cur;
  114. }
  115. static int
  116. nouveau_channel_wait(struct nvif_push *push, u32 size)
  117. {
  118. struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push);
  119. int ret;
  120. chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn);
  121. ret = RING_SPACE(chan, size);
  122. if (ret == 0) {
  123. chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr;
  124. chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur;
  125. chan->chan._push.cur = chan->chan._push.bgn;
  126. chan->chan._push.end = chan->chan._push.bgn + size;
  127. }
  128. return ret;
  129. }
  130. static int
  131. nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
  132. u32 size, struct nouveau_channel **pchan)
  133. {
  134. struct nouveau_cli *cli = (void *)device->object.client;
  135. struct nv_dma_v0 args = {};
  136. struct nouveau_channel *chan;
  137. u32 target;
  138. int ret;
  139. chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
  140. if (!chan)
  141. return -ENOMEM;
  142. chan->device = device;
  143. chan->drm = drm;
  144. chan->vmm = cli->svm.cli ? &cli->svm : &cli->vmm;
  145. atomic_set(&chan->killed, 0);
  146. /* allocate memory for dma push buffer */
  147. target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
  148. if (nouveau_vram_pushbuf)
  149. target = NOUVEAU_GEM_DOMAIN_VRAM;
  150. ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
  151. &chan->push.buffer);
  152. if (ret == 0) {
  153. ret = nouveau_bo_pin(chan->push.buffer, target, false);
  154. if (ret == 0)
  155. ret = nouveau_bo_map(chan->push.buffer);
  156. }
  157. if (ret) {
  158. nouveau_channel_del(pchan);
  159. return ret;
  160. }
  161. chan->chan._push.mem.object.parent = cli->base.object.parent;
  162. chan->chan._push.mem.object.client = &cli->base;
  163. chan->chan._push.mem.object.name = "chanPush";
  164. chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual;
  165. chan->chan._push.wait = nouveau_channel_wait;
  166. chan->chan._push.kick = nouveau_channel_kick;
  167. chan->chan.push = &chan->chan._push;
  168. /* create dma object covering the *entire* memory space that the
  169. * pushbuf lives in, this is because the GEM code requires that
  170. * we be able to call out to other (indirect) push buffers
  171. */
  172. chan->push.addr = chan->push.buffer->offset;
  173. if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
  174. ret = nouveau_vma_new(chan->push.buffer, chan->vmm,
  175. &chan->push.vma);
  176. if (ret) {
  177. nouveau_channel_del(pchan);
  178. return ret;
  179. }
  180. chan->push.addr = chan->push.vma->addr;
  181. if (device->info.family >= NV_DEVICE_INFO_V0_FERMI)
  182. return 0;
  183. args.target = NV_DMA_V0_TARGET_VM;
  184. args.access = NV_DMA_V0_ACCESS_VM;
  185. args.start = 0;
  186. args.limit = chan->vmm->vmm.limit - 1;
  187. } else
  188. if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
  189. if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
  190. /* nv04 vram pushbuf hack, retarget to its location in
  191. * the framebuffer bar rather than direct vram access..
  192. * nfi why this exists, it came from the -nv ddx.
  193. */
  194. args.target = NV_DMA_V0_TARGET_PCI;
  195. args.access = NV_DMA_V0_ACCESS_RDWR;
  196. args.start = nvxx_device(device)->func->
  197. resource_addr(nvxx_device(device), 1);
  198. args.limit = args.start + device->info.ram_user - 1;
  199. } else {
  200. args.target = NV_DMA_V0_TARGET_VRAM;
  201. args.access = NV_DMA_V0_ACCESS_RDWR;
  202. args.start = 0;
  203. args.limit = device->info.ram_user - 1;
  204. }
  205. } else {
  206. if (chan->drm->agp.bridge) {
  207. args.target = NV_DMA_V0_TARGET_AGP;
  208. args.access = NV_DMA_V0_ACCESS_RDWR;
  209. args.start = chan->drm->agp.base;
  210. args.limit = chan->drm->agp.base +
  211. chan->drm->agp.size - 1;
  212. } else {
  213. args.target = NV_DMA_V0_TARGET_VM;
  214. args.access = NV_DMA_V0_ACCESS_RDWR;
  215. args.start = 0;
  216. args.limit = chan->vmm->vmm.limit - 1;
  217. }
  218. }
  219. ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0,
  220. NV_DMA_FROM_MEMORY, &args, sizeof(args),
  221. &chan->push.ctxdma);
  222. if (ret) {
  223. nouveau_channel_del(pchan);
  224. return ret;
  225. }
  226. return 0;
  227. }
  228. static int
  229. nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
  230. u64 runlist, bool priv, struct nouveau_channel **pchan)
  231. {
  232. static const u16 oclasses[] = { TURING_CHANNEL_GPFIFO_A,
  233. VOLTA_CHANNEL_GPFIFO_A,
  234. PASCAL_CHANNEL_GPFIFO_A,
  235. MAXWELL_CHANNEL_GPFIFO_A,
  236. KEPLER_CHANNEL_GPFIFO_B,
  237. KEPLER_CHANNEL_GPFIFO_A,
  238. FERMI_CHANNEL_GPFIFO,
  239. G82_CHANNEL_GPFIFO,
  240. NV50_CHANNEL_GPFIFO,
  241. 0 };
  242. const u16 *oclass = oclasses;
  243. union {
  244. struct nv50_channel_gpfifo_v0 nv50;
  245. struct fermi_channel_gpfifo_v0 fermi;
  246. struct kepler_channel_gpfifo_a_v0 kepler;
  247. struct volta_channel_gpfifo_a_v0 volta;
  248. } args;
  249. struct nouveau_channel *chan;
  250. u32 size;
  251. int ret;
  252. /* allocate dma push buffer */
  253. ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
  254. *pchan = chan;
  255. if (ret)
  256. return ret;
  257. /* create channel object */
  258. do {
  259. if (oclass[0] >= VOLTA_CHANNEL_GPFIFO_A) {
  260. args.volta.version = 0;
  261. args.volta.ilength = 0x02000;
  262. args.volta.ioffset = 0x10000 + chan->push.addr;
  263. args.volta.runlist = runlist;
  264. args.volta.vmm = nvif_handle(&chan->vmm->vmm.object);
  265. args.volta.priv = priv;
  266. size = sizeof(args.volta);
  267. } else
  268. if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
  269. args.kepler.version = 0;
  270. args.kepler.ilength = 0x02000;
  271. args.kepler.ioffset = 0x10000 + chan->push.addr;
  272. args.kepler.runlist = runlist;
  273. args.kepler.vmm = nvif_handle(&chan->vmm->vmm.object);
  274. args.kepler.priv = priv;
  275. size = sizeof(args.kepler);
  276. } else
  277. if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
  278. args.fermi.version = 0;
  279. args.fermi.ilength = 0x02000;
  280. args.fermi.ioffset = 0x10000 + chan->push.addr;
  281. args.fermi.vmm = nvif_handle(&chan->vmm->vmm.object);
  282. size = sizeof(args.fermi);
  283. } else {
  284. args.nv50.version = 0;
  285. args.nv50.ilength = 0x02000;
  286. args.nv50.ioffset = 0x10000 + chan->push.addr;
  287. args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
  288. args.nv50.vmm = nvif_handle(&chan->vmm->vmm.object);
  289. size = sizeof(args.nv50);
  290. }
  291. ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0,
  292. *oclass++, &args, size, &chan->user);
  293. if (ret == 0) {
  294. if (chan->user.oclass >= VOLTA_CHANNEL_GPFIFO_A) {
  295. chan->chid = args.volta.chid;
  296. chan->inst = args.volta.inst;
  297. chan->token = args.volta.token;
  298. } else
  299. if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) {
  300. chan->chid = args.kepler.chid;
  301. chan->inst = args.kepler.inst;
  302. } else
  303. if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
  304. chan->chid = args.fermi.chid;
  305. } else {
  306. chan->chid = args.nv50.chid;
  307. }
  308. return ret;
  309. }
  310. } while (*oclass);
  311. nouveau_channel_del(pchan);
  312. return ret;
  313. }
  314. static int
  315. nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
  316. struct nouveau_channel **pchan)
  317. {
  318. static const u16 oclasses[] = { NV40_CHANNEL_DMA,
  319. NV17_CHANNEL_DMA,
  320. NV10_CHANNEL_DMA,
  321. NV03_CHANNEL_DMA,
  322. 0 };
  323. const u16 *oclass = oclasses;
  324. struct nv03_channel_dma_v0 args;
  325. struct nouveau_channel *chan;
  326. int ret;
  327. /* allocate dma push buffer */
  328. ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
  329. *pchan = chan;
  330. if (ret)
  331. return ret;
  332. /* create channel object */
  333. args.version = 0;
  334. args.pushbuf = nvif_handle(&chan->push.ctxdma);
  335. args.offset = chan->push.addr;
  336. do {
  337. ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0,
  338. *oclass++, &args, sizeof(args),
  339. &chan->user);
  340. if (ret == 0) {
  341. chan->chid = args.chid;
  342. return ret;
  343. }
  344. } while (ret && *oclass);
  345. nouveau_channel_del(pchan);
  346. return ret;
  347. }
  348. static int
  349. nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
  350. {
  351. struct nvif_device *device = chan->device;
  352. struct nouveau_drm *drm = chan->drm;
  353. struct nv_dma_v0 args = {};
  354. int ret, i;
  355. nvif_object_map(&chan->user, NULL, 0);
  356. if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
  357. ret = nvif_notify_ctor(&chan->user, "abi16ChanKilled",
  358. nouveau_channel_killed,
  359. true, NV906F_V0_NTFY_KILLED,
  360. NULL, 0, 0, &chan->kill);
  361. if (ret == 0)
  362. ret = nvif_notify_get(&chan->kill);
  363. if (ret) {
  364. NV_ERROR(drm, "Failed to request channel kill "
  365. "notification: %d\n", ret);
  366. return ret;
  367. }
  368. }
  369. /* allocate dma objects to cover all allowed vram, and gart */
  370. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  371. if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
  372. args.target = NV_DMA_V0_TARGET_VM;
  373. args.access = NV_DMA_V0_ACCESS_VM;
  374. args.start = 0;
  375. args.limit = chan->vmm->vmm.limit - 1;
  376. } else {
  377. args.target = NV_DMA_V0_TARGET_VRAM;
  378. args.access = NV_DMA_V0_ACCESS_RDWR;
  379. args.start = 0;
  380. args.limit = device->info.ram_user - 1;
  381. }
  382. ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram,
  383. NV_DMA_IN_MEMORY, &args, sizeof(args),
  384. &chan->vram);
  385. if (ret)
  386. return ret;
  387. if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
  388. args.target = NV_DMA_V0_TARGET_VM;
  389. args.access = NV_DMA_V0_ACCESS_VM;
  390. args.start = 0;
  391. args.limit = chan->vmm->vmm.limit - 1;
  392. } else
  393. if (chan->drm->agp.bridge) {
  394. args.target = NV_DMA_V0_TARGET_AGP;
  395. args.access = NV_DMA_V0_ACCESS_RDWR;
  396. args.start = chan->drm->agp.base;
  397. args.limit = chan->drm->agp.base +
  398. chan->drm->agp.size - 1;
  399. } else {
  400. args.target = NV_DMA_V0_TARGET_VM;
  401. args.access = NV_DMA_V0_ACCESS_RDWR;
  402. args.start = 0;
  403. args.limit = chan->vmm->vmm.limit - 1;
  404. }
  405. ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart,
  406. NV_DMA_IN_MEMORY, &args, sizeof(args),
  407. &chan->gart);
  408. if (ret)
  409. return ret;
  410. }
  411. /* initialise dma tracking parameters */
  412. switch (chan->user.oclass & 0x00ff) {
  413. case 0x006b:
  414. case 0x006e:
  415. chan->user_put = 0x40;
  416. chan->user_get = 0x44;
  417. chan->dma.max = (0x10000 / 4) - 2;
  418. break;
  419. default:
  420. chan->user_put = 0x40;
  421. chan->user_get = 0x44;
  422. chan->user_get_hi = 0x60;
  423. chan->dma.ib_base = 0x10000 / 4;
  424. chan->dma.ib_max = (0x02000 / 8) - 1;
  425. chan->dma.ib_put = 0;
  426. chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
  427. chan->dma.max = chan->dma.ib_base;
  428. break;
  429. }
  430. chan->dma.put = 0;
  431. chan->dma.cur = chan->dma.put;
  432. chan->dma.free = chan->dma.max - chan->dma.cur;
  433. ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS);
  434. if (ret)
  435. return ret;
  436. for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
  437. PUSH_DATA(chan->chan.push, 0x00000000);
  438. /* allocate software object class (used for fences on <= nv05) */
  439. if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
  440. ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e,
  441. NVIF_CLASS_SW_NV04,
  442. NULL, 0, &chan->nvsw);
  443. if (ret)
  444. return ret;
  445. ret = PUSH_WAIT(chan->chan.push, 2);
  446. if (ret)
  447. return ret;
  448. PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle);
  449. PUSH_KICK(chan->chan.push);
  450. }
  451. /* initialise synchronisation */
  452. return nouveau_fence(chan->drm)->context_new(chan);
  453. }
  454. int
  455. nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
  456. u32 arg0, u32 arg1, bool priv,
  457. struct nouveau_channel **pchan)
  458. {
  459. struct nouveau_cli *cli = (void *)device->object.client;
  460. bool super;
  461. int ret;
  462. /* hack until fencenv50 is fixed, and agp access relaxed */
  463. super = cli->base.super;
  464. cli->base.super = true;
  465. ret = nouveau_channel_ind(drm, device, arg0, priv, pchan);
  466. if (ret) {
  467. NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
  468. ret = nouveau_channel_dma(drm, device, pchan);
  469. if (ret) {
  470. NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
  471. goto done;
  472. }
  473. }
  474. ret = nouveau_channel_init(*pchan, arg0, arg1);
  475. if (ret) {
  476. NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
  477. nouveau_channel_del(pchan);
  478. goto done;
  479. }
  480. ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst);
  481. if (ret)
  482. nouveau_channel_del(pchan);
  483. done:
  484. cli->base.super = super;
  485. return ret;
  486. }
  487. int
  488. nouveau_channels_init(struct nouveau_drm *drm)
  489. {
  490. struct {
  491. struct nv_device_info_v1 m;
  492. struct {
  493. struct nv_device_info_v1_data channels;
  494. } v;
  495. } args = {
  496. .m.version = 1,
  497. .m.count = sizeof(args.v) / sizeof(args.v.channels),
  498. .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS,
  499. };
  500. struct nvif_object *device = &drm->client.device.object;
  501. int ret;
  502. ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
  503. if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
  504. return -ENODEV;
  505. drm->chan.nr = args.v.channels.data;
  506. drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr);
  507. return 0;
  508. }