mga_drv.h 19 KB

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  1. /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All rights reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25. * OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors:
  28. * Gareth Hughes <gareth@valinux.com>
  29. */
  30. #ifndef __MGA_DRV_H__
  31. #define __MGA_DRV_H__
  32. #include <linux/irqreturn.h>
  33. #include <linux/pci.h>
  34. #include <linux/slab.h>
  35. #include <drm/drm_agpsupport.h>
  36. #include <drm/drm_device.h>
  37. #include <drm/drm_file.h>
  38. #include <drm/drm_ioctl.h>
  39. #include <drm/drm_irq.h>
  40. #include <drm/drm_legacy.h>
  41. #include <drm/drm_print.h>
  42. #include <drm/drm_sarea.h>
  43. #include <drm/drm_vblank.h>
  44. #include <drm/mga_drm.h>
  45. /* General customization:
  46. */
  47. #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
  48. #define DRIVER_NAME "mga"
  49. #define DRIVER_DESC "Matrox G200/G400"
  50. #define DRIVER_DATE "20051102"
  51. #define DRIVER_MAJOR 3
  52. #define DRIVER_MINOR 2
  53. #define DRIVER_PATCHLEVEL 1
  54. typedef struct drm_mga_primary_buffer {
  55. u8 *start;
  56. u8 *end;
  57. int size;
  58. u32 tail;
  59. int space;
  60. volatile long wrapped;
  61. volatile u32 *status;
  62. u32 last_flush;
  63. u32 last_wrap;
  64. u32 high_mark;
  65. } drm_mga_primary_buffer_t;
  66. typedef struct drm_mga_freelist {
  67. struct drm_mga_freelist *next;
  68. struct drm_mga_freelist *prev;
  69. drm_mga_age_t age;
  70. struct drm_buf *buf;
  71. } drm_mga_freelist_t;
  72. typedef struct {
  73. drm_mga_freelist_t *list_entry;
  74. int discard;
  75. int dispatched;
  76. } drm_mga_buf_priv_t;
  77. typedef struct drm_mga_private {
  78. drm_mga_primary_buffer_t prim;
  79. drm_mga_sarea_t *sarea_priv;
  80. drm_mga_freelist_t *head;
  81. drm_mga_freelist_t *tail;
  82. unsigned int warp_pipe;
  83. unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
  84. int chipset;
  85. int usec_timeout;
  86. /**
  87. * If set, the new DMA initialization sequence was used. This is
  88. * primarilly used to select how the driver should uninitialized its
  89. * internal DMA structures.
  90. */
  91. int used_new_dma_init;
  92. /**
  93. * If AGP memory is used for DMA buffers, this will be the value
  94. * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer).
  95. */
  96. u32 dma_access;
  97. /**
  98. * If AGP memory is used for DMA buffers, this will be the value
  99. * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI
  100. * transfer).
  101. */
  102. u32 wagp_enable;
  103. /**
  104. * \name MMIO region parameters.
  105. *
  106. * \sa drm_mga_private_t::mmio
  107. */
  108. /*@{ */
  109. resource_size_t mmio_base; /**< Bus address of base of MMIO. */
  110. resource_size_t mmio_size; /**< Size of the MMIO region. */
  111. /*@} */
  112. u32 clear_cmd;
  113. u32 maccess;
  114. atomic_t vbl_received; /**< Number of vblanks received. */
  115. wait_queue_head_t fence_queue;
  116. atomic_t last_fence_retired;
  117. u32 next_fence_to_post;
  118. unsigned int fb_cpp;
  119. unsigned int front_offset;
  120. unsigned int front_pitch;
  121. unsigned int back_offset;
  122. unsigned int back_pitch;
  123. unsigned int depth_cpp;
  124. unsigned int depth_offset;
  125. unsigned int depth_pitch;
  126. unsigned int texture_offset;
  127. unsigned int texture_size;
  128. drm_local_map_t *sarea;
  129. drm_local_map_t *mmio;
  130. drm_local_map_t *status;
  131. drm_local_map_t *warp;
  132. drm_local_map_t *primary;
  133. drm_local_map_t *agp_textures;
  134. unsigned long agp_handle;
  135. unsigned int agp_size;
  136. } drm_mga_private_t;
  137. extern const struct drm_ioctl_desc mga_ioctls[];
  138. extern int mga_max_ioctl;
  139. /* mga_dma.c */
  140. extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
  141. struct drm_file *file_priv);
  142. extern int mga_dma_init(struct drm_device *dev, void *data,
  143. struct drm_file *file_priv);
  144. extern int mga_getparam(struct drm_device *dev, void *data,
  145. struct drm_file *file_priv);
  146. extern int mga_dma_flush(struct drm_device *dev, void *data,
  147. struct drm_file *file_priv);
  148. extern int mga_dma_reset(struct drm_device *dev, void *data,
  149. struct drm_file *file_priv);
  150. extern int mga_dma_buffers(struct drm_device *dev, void *data,
  151. struct drm_file *file_priv);
  152. extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
  153. extern void mga_driver_unload(struct drm_device *dev);
  154. extern void mga_driver_lastclose(struct drm_device *dev);
  155. extern int mga_driver_dma_quiescent(struct drm_device *dev);
  156. extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
  157. extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
  158. extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
  159. extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
  160. extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
  161. /* mga_warp.c */
  162. extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
  163. extern int mga_warp_init(drm_mga_private_t *dev_priv);
  164. /* mga_irq.c */
  165. extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
  166. extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
  167. extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
  168. extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
  169. extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
  170. extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
  171. extern void mga_driver_irq_preinstall(struct drm_device *dev);
  172. extern int mga_driver_irq_postinstall(struct drm_device *dev);
  173. extern void mga_driver_irq_uninstall(struct drm_device *dev);
  174. extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
  175. unsigned long arg);
  176. #define mga_flush_write_combine() wmb()
  177. #define MGA_READ8(reg) \
  178. readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
  179. #define MGA_READ(reg) \
  180. readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
  181. #define MGA_WRITE8(reg, val) \
  182. writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
  183. #define MGA_WRITE(reg, val) \
  184. writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
  185. #define DWGREG0 0x1c00
  186. #define DWGREG0_END 0x1dff
  187. #define DWGREG1 0x2c00
  188. #define DWGREG1_END 0x2dff
  189. #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
  190. #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
  191. #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
  192. #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
  193. /* ================================================================
  194. * Helper macross...
  195. */
  196. #define MGA_EMIT_STATE(dev_priv, dirty) \
  197. do { \
  198. if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
  199. if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
  200. mga_g400_emit_state(dev_priv); \
  201. else \
  202. mga_g200_emit_state(dev_priv); \
  203. } \
  204. } while (0)
  205. #define WRAP_TEST_WITH_RETURN(dev_priv) \
  206. do { \
  207. if (test_bit(0, &dev_priv->prim.wrapped)) { \
  208. if (mga_is_idle(dev_priv)) { \
  209. mga_do_dma_wrap_end(dev_priv); \
  210. } else if (dev_priv->prim.space < \
  211. dev_priv->prim.high_mark) { \
  212. if (MGA_DMA_DEBUG) \
  213. DRM_INFO("wrap...\n"); \
  214. return -EBUSY; \
  215. } \
  216. } \
  217. } while (0)
  218. #define WRAP_WAIT_WITH_RETURN(dev_priv) \
  219. do { \
  220. if (test_bit(0, &dev_priv->prim.wrapped)) { \
  221. if (mga_do_wait_for_idle(dev_priv) < 0) { \
  222. if (MGA_DMA_DEBUG) \
  223. DRM_INFO("wrap...\n"); \
  224. return -EBUSY; \
  225. } \
  226. mga_do_dma_wrap_end(dev_priv); \
  227. } \
  228. } while (0)
  229. /* ================================================================
  230. * Primary DMA command stream
  231. */
  232. #define MGA_VERBOSE 0
  233. #define DMA_LOCALS unsigned int write; volatile u8 *prim;
  234. #define DMA_BLOCK_SIZE (5 * sizeof(u32))
  235. #define BEGIN_DMA(n) \
  236. do { \
  237. if (MGA_VERBOSE) { \
  238. DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
  239. DRM_INFO(" space=0x%x req=0x%zx\n", \
  240. dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
  241. } \
  242. prim = dev_priv->prim.start; \
  243. write = dev_priv->prim.tail; \
  244. } while (0)
  245. #define BEGIN_DMA_WRAP() \
  246. do { \
  247. if (MGA_VERBOSE) { \
  248. DRM_INFO("BEGIN_DMA()\n"); \
  249. DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
  250. } \
  251. prim = dev_priv->prim.start; \
  252. write = dev_priv->prim.tail; \
  253. } while (0)
  254. #define ADVANCE_DMA() \
  255. do { \
  256. dev_priv->prim.tail = write; \
  257. if (MGA_VERBOSE) \
  258. DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
  259. write, dev_priv->prim.space); \
  260. } while (0)
  261. #define FLUSH_DMA() \
  262. do { \
  263. if (0) { \
  264. DRM_INFO("\n"); \
  265. DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
  266. dev_priv->prim.tail, \
  267. (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
  268. dev_priv->primary->offset)); \
  269. } \
  270. if (!test_bit(0, &dev_priv->prim.wrapped)) { \
  271. if (dev_priv->prim.space < dev_priv->prim.high_mark) \
  272. mga_do_dma_wrap_start(dev_priv); \
  273. else \
  274. mga_do_dma_flush(dev_priv); \
  275. } \
  276. } while (0)
  277. /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
  278. */
  279. #define DMA_WRITE(offset, val) \
  280. do { \
  281. if (MGA_VERBOSE) \
  282. DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04zx\n", \
  283. (u32)(val), write + (offset) * sizeof(u32)); \
  284. *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
  285. } while (0)
  286. #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
  287. do { \
  288. DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
  289. (DMAREG(reg1) << 8) | \
  290. (DMAREG(reg2) << 16) | \
  291. (DMAREG(reg3) << 24))); \
  292. DMA_WRITE(1, val0); \
  293. DMA_WRITE(2, val1); \
  294. DMA_WRITE(3, val2); \
  295. DMA_WRITE(4, val3); \
  296. write += DMA_BLOCK_SIZE; \
  297. } while (0)
  298. /* Buffer aging via primary DMA stream head pointer.
  299. */
  300. #define SET_AGE(age, h, w) \
  301. do { \
  302. (age)->head = h; \
  303. (age)->wrap = w; \
  304. } while (0)
  305. #define TEST_AGE(age, h, w) ((age)->wrap < w || \
  306. ((age)->wrap == w && \
  307. (age)->head < h))
  308. #define AGE_BUFFER(buf_priv) \
  309. do { \
  310. drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
  311. if ((buf_priv)->dispatched) { \
  312. entry->age.head = (dev_priv->prim.tail + \
  313. dev_priv->primary->offset); \
  314. entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
  315. } else { \
  316. entry->age.head = 0; \
  317. entry->age.wrap = 0; \
  318. } \
  319. } while (0)
  320. #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
  321. MGA_DWGENGSTS | \
  322. MGA_ENDPRDMASTS)
  323. #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
  324. MGA_ENDPRDMASTS)
  325. #define MGA_DMA_DEBUG 0
  326. /* A reduced set of the mga registers.
  327. */
  328. #define MGA_CRTC_INDEX 0x1fd4
  329. #define MGA_CRTC_DATA 0x1fd5
  330. /* CRTC11 */
  331. #define MGA_VINTCLR (1 << 4)
  332. #define MGA_VINTEN (1 << 5)
  333. #define MGA_ALPHACTRL 0x2c7c
  334. #define MGA_AR0 0x1c60
  335. #define MGA_AR1 0x1c64
  336. #define MGA_AR2 0x1c68
  337. #define MGA_AR3 0x1c6c
  338. #define MGA_AR4 0x1c70
  339. #define MGA_AR5 0x1c74
  340. #define MGA_AR6 0x1c78
  341. #define MGA_CXBNDRY 0x1c80
  342. #define MGA_CXLEFT 0x1ca0
  343. #define MGA_CXRIGHT 0x1ca4
  344. #define MGA_DMAPAD 0x1c54
  345. #define MGA_DSTORG 0x2cb8
  346. #define MGA_DWGCTL 0x1c00
  347. # define MGA_OPCOD_MASK (15 << 0)
  348. # define MGA_OPCOD_TRAP (4 << 0)
  349. # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
  350. # define MGA_OPCOD_BITBLT (8 << 0)
  351. # define MGA_OPCOD_ILOAD (9 << 0)
  352. # define MGA_ATYPE_MASK (7 << 4)
  353. # define MGA_ATYPE_RPL (0 << 4)
  354. # define MGA_ATYPE_RSTR (1 << 4)
  355. # define MGA_ATYPE_ZI (3 << 4)
  356. # define MGA_ATYPE_BLK (4 << 4)
  357. # define MGA_ATYPE_I (7 << 4)
  358. # define MGA_LINEAR (1 << 7)
  359. # define MGA_ZMODE_MASK (7 << 8)
  360. # define MGA_ZMODE_NOZCMP (0 << 8)
  361. # define MGA_ZMODE_ZE (2 << 8)
  362. # define MGA_ZMODE_ZNE (3 << 8)
  363. # define MGA_ZMODE_ZLT (4 << 8)
  364. # define MGA_ZMODE_ZLTE (5 << 8)
  365. # define MGA_ZMODE_ZGT (6 << 8)
  366. # define MGA_ZMODE_ZGTE (7 << 8)
  367. # define MGA_SOLID (1 << 11)
  368. # define MGA_ARZERO (1 << 12)
  369. # define MGA_SGNZERO (1 << 13)
  370. # define MGA_SHIFTZERO (1 << 14)
  371. # define MGA_BOP_MASK (15 << 16)
  372. # define MGA_BOP_ZERO (0 << 16)
  373. # define MGA_BOP_DST (10 << 16)
  374. # define MGA_BOP_SRC (12 << 16)
  375. # define MGA_BOP_ONE (15 << 16)
  376. # define MGA_TRANS_SHIFT 20
  377. # define MGA_TRANS_MASK (15 << 20)
  378. # define MGA_BLTMOD_MASK (15 << 25)
  379. # define MGA_BLTMOD_BMONOLEF (0 << 25)
  380. # define MGA_BLTMOD_BMONOWF (4 << 25)
  381. # define MGA_BLTMOD_PLAN (1 << 25)
  382. # define MGA_BLTMOD_BFCOL (2 << 25)
  383. # define MGA_BLTMOD_BU32BGR (3 << 25)
  384. # define MGA_BLTMOD_BU32RGB (7 << 25)
  385. # define MGA_BLTMOD_BU24BGR (11 << 25)
  386. # define MGA_BLTMOD_BU24RGB (15 << 25)
  387. # define MGA_PATTERN (1 << 29)
  388. # define MGA_TRANSC (1 << 30)
  389. # define MGA_CLIPDIS (1 << 31)
  390. #define MGA_DWGSYNC 0x2c4c
  391. #define MGA_FCOL 0x1c24
  392. #define MGA_FIFOSTATUS 0x1e10
  393. #define MGA_FOGCOL 0x1cf4
  394. #define MGA_FXBNDRY 0x1c84
  395. #define MGA_FXLEFT 0x1ca8
  396. #define MGA_FXRIGHT 0x1cac
  397. #define MGA_ICLEAR 0x1e18
  398. # define MGA_SOFTRAPICLR (1 << 0)
  399. # define MGA_VLINEICLR (1 << 5)
  400. #define MGA_IEN 0x1e1c
  401. # define MGA_SOFTRAPIEN (1 << 0)
  402. # define MGA_VLINEIEN (1 << 5)
  403. #define MGA_LEN 0x1c5c
  404. #define MGA_MACCESS 0x1c04
  405. #define MGA_PITCH 0x1c8c
  406. #define MGA_PLNWT 0x1c1c
  407. #define MGA_PRIMADDRESS 0x1e58
  408. # define MGA_DMA_GENERAL (0 << 0)
  409. # define MGA_DMA_BLIT (1 << 0)
  410. # define MGA_DMA_VECTOR (2 << 0)
  411. # define MGA_DMA_VERTEX (3 << 0)
  412. #define MGA_PRIMEND 0x1e5c
  413. # define MGA_PRIMNOSTART (1 << 0)
  414. # define MGA_PAGPXFER (1 << 1)
  415. #define MGA_PRIMPTR 0x1e50
  416. # define MGA_PRIMPTREN0 (1 << 0)
  417. # define MGA_PRIMPTREN1 (1 << 1)
  418. #define MGA_RST 0x1e40
  419. # define MGA_SOFTRESET (1 << 0)
  420. # define MGA_SOFTEXTRST (1 << 1)
  421. #define MGA_SECADDRESS 0x2c40
  422. #define MGA_SECEND 0x2c44
  423. #define MGA_SETUPADDRESS 0x2cd0
  424. #define MGA_SETUPEND 0x2cd4
  425. #define MGA_SGN 0x1c58
  426. #define MGA_SOFTRAP 0x2c48
  427. #define MGA_SRCORG 0x2cb4
  428. # define MGA_SRMMAP_MASK (1 << 0)
  429. # define MGA_SRCMAP_FB (0 << 0)
  430. # define MGA_SRCMAP_SYSMEM (1 << 0)
  431. # define MGA_SRCACC_MASK (1 << 1)
  432. # define MGA_SRCACC_PCI (0 << 1)
  433. # define MGA_SRCACC_AGP (1 << 1)
  434. #define MGA_STATUS 0x1e14
  435. # define MGA_SOFTRAPEN (1 << 0)
  436. # define MGA_VSYNCPEN (1 << 4)
  437. # define MGA_VLINEPEN (1 << 5)
  438. # define MGA_DWGENGSTS (1 << 16)
  439. # define MGA_ENDPRDMASTS (1 << 17)
  440. #define MGA_STENCIL 0x2cc8
  441. #define MGA_STENCILCTL 0x2ccc
  442. #define MGA_TDUALSTAGE0 0x2cf8
  443. #define MGA_TDUALSTAGE1 0x2cfc
  444. #define MGA_TEXBORDERCOL 0x2c5c
  445. #define MGA_TEXCTL 0x2c30
  446. #define MGA_TEXCTL2 0x2c3c
  447. # define MGA_DUALTEX (1 << 7)
  448. # define MGA_G400_TC2_MAGIC (1 << 15)
  449. # define MGA_MAP1_ENABLE (1 << 31)
  450. #define MGA_TEXFILTER 0x2c58
  451. #define MGA_TEXHEIGHT 0x2c2c
  452. #define MGA_TEXORG 0x2c24
  453. # define MGA_TEXORGMAP_MASK (1 << 0)
  454. # define MGA_TEXORGMAP_FB (0 << 0)
  455. # define MGA_TEXORGMAP_SYSMEM (1 << 0)
  456. # define MGA_TEXORGACC_MASK (1 << 1)
  457. # define MGA_TEXORGACC_PCI (0 << 1)
  458. # define MGA_TEXORGACC_AGP (1 << 1)
  459. #define MGA_TEXORG1 0x2ca4
  460. #define MGA_TEXORG2 0x2ca8
  461. #define MGA_TEXORG3 0x2cac
  462. #define MGA_TEXORG4 0x2cb0
  463. #define MGA_TEXTRANS 0x2c34
  464. #define MGA_TEXTRANSHIGH 0x2c38
  465. #define MGA_TEXWIDTH 0x2c28
  466. #define MGA_WACCEPTSEQ 0x1dd4
  467. #define MGA_WCODEADDR 0x1e6c
  468. #define MGA_WFLAG 0x1dc4
  469. #define MGA_WFLAG1 0x1de0
  470. #define MGA_WFLAGNB 0x1e64
  471. #define MGA_WFLAGNB1 0x1e08
  472. #define MGA_WGETMSB 0x1dc8
  473. #define MGA_WIADDR 0x1dc0
  474. #define MGA_WIADDR2 0x1dd8
  475. # define MGA_WMODE_SUSPEND (0 << 0)
  476. # define MGA_WMODE_RESUME (1 << 0)
  477. # define MGA_WMODE_JUMP (2 << 0)
  478. # define MGA_WMODE_START (3 << 0)
  479. # define MGA_WAGP_ENABLE (1 << 2)
  480. #define MGA_WMISC 0x1e70
  481. # define MGA_WUCODECACHE_ENABLE (1 << 0)
  482. # define MGA_WMASTER_ENABLE (1 << 1)
  483. # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
  484. #define MGA_WVRTXSZ 0x1dcc
  485. #define MGA_YBOT 0x1c9c
  486. #define MGA_YDST 0x1c90
  487. #define MGA_YDSTLEN 0x1c88
  488. #define MGA_YDSTORG 0x1c94
  489. #define MGA_YTOP 0x1c98
  490. #define MGA_ZORG 0x1c0c
  491. /* This finishes the current batch of commands
  492. */
  493. #define MGA_EXEC 0x0100
  494. /* AGP PLL encoding (for G200 only).
  495. */
  496. #define MGA_AGP_PLL 0x1e4c
  497. # define MGA_AGP2XPLL_DISABLE (0 << 0)
  498. # define MGA_AGP2XPLL_ENABLE (1 << 0)
  499. /* Warp registers
  500. */
  501. #define MGA_WR0 0x2d00
  502. #define MGA_WR1 0x2d04
  503. #define MGA_WR2 0x2d08
  504. #define MGA_WR3 0x2d0c
  505. #define MGA_WR4 0x2d10
  506. #define MGA_WR5 0x2d14
  507. #define MGA_WR6 0x2d18
  508. #define MGA_WR7 0x2d1c
  509. #define MGA_WR8 0x2d20
  510. #define MGA_WR9 0x2d24
  511. #define MGA_WR10 0x2d28
  512. #define MGA_WR11 0x2d2c
  513. #define MGA_WR12 0x2d30
  514. #define MGA_WR13 0x2d34
  515. #define MGA_WR14 0x2d38
  516. #define MGA_WR15 0x2d3c
  517. #define MGA_WR16 0x2d40
  518. #define MGA_WR17 0x2d44
  519. #define MGA_WR18 0x2d48
  520. #define MGA_WR19 0x2d4c
  521. #define MGA_WR20 0x2d50
  522. #define MGA_WR21 0x2d54
  523. #define MGA_WR22 0x2d58
  524. #define MGA_WR23 0x2d5c
  525. #define MGA_WR24 0x2d60
  526. #define MGA_WR25 0x2d64
  527. #define MGA_WR26 0x2d68
  528. #define MGA_WR27 0x2d6c
  529. #define MGA_WR28 0x2d70
  530. #define MGA_WR29 0x2d74
  531. #define MGA_WR30 0x2d78
  532. #define MGA_WR31 0x2d7c
  533. #define MGA_WR32 0x2d80
  534. #define MGA_WR33 0x2d84
  535. #define MGA_WR34 0x2d88
  536. #define MGA_WR35 0x2d8c
  537. #define MGA_WR36 0x2d90
  538. #define MGA_WR37 0x2d94
  539. #define MGA_WR38 0x2d98
  540. #define MGA_WR39 0x2d9c
  541. #define MGA_WR40 0x2da0
  542. #define MGA_WR41 0x2da4
  543. #define MGA_WR42 0x2da8
  544. #define MGA_WR43 0x2dac
  545. #define MGA_WR44 0x2db0
  546. #define MGA_WR45 0x2db4
  547. #define MGA_WR46 0x2db8
  548. #define MGA_WR47 0x2dbc
  549. #define MGA_WR48 0x2dc0
  550. #define MGA_WR49 0x2dc4
  551. #define MGA_WR50 0x2dc8
  552. #define MGA_WR51 0x2dcc
  553. #define MGA_WR52 0x2dd0
  554. #define MGA_WR53 0x2dd4
  555. #define MGA_WR54 0x2dd8
  556. #define MGA_WR55 0x2ddc
  557. #define MGA_WR56 0x2de0
  558. #define MGA_WR57 0x2de4
  559. #define MGA_WR58 0x2de8
  560. #define MGA_WR59 0x2dec
  561. #define MGA_WR60 0x2df0
  562. #define MGA_WR61 0x2df4
  563. #define MGA_WR62 0x2df8
  564. #define MGA_WR63 0x2dfc
  565. # define MGA_G400_WR_MAGIC (1 << 6)
  566. # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
  567. #define MGA_ILOAD_ALIGN 64
  568. #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
  569. #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
  570. MGA_ATYPE_I | \
  571. MGA_ZMODE_NOZCMP | \
  572. MGA_ARZERO | \
  573. MGA_SGNZERO | \
  574. MGA_BOP_SRC | \
  575. (15 << MGA_TRANS_SHIFT))
  576. #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
  577. MGA_ZMODE_NOZCMP | \
  578. MGA_SOLID | \
  579. MGA_ARZERO | \
  580. MGA_SGNZERO | \
  581. MGA_SHIFTZERO | \
  582. MGA_BOP_SRC | \
  583. (0 << MGA_TRANS_SHIFT) | \
  584. MGA_BLTMOD_BMONOLEF | \
  585. MGA_TRANSC | \
  586. MGA_CLIPDIS)
  587. #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
  588. MGA_ATYPE_RPL | \
  589. MGA_SGNZERO | \
  590. MGA_SHIFTZERO | \
  591. MGA_BOP_SRC | \
  592. (0 << MGA_TRANS_SHIFT) | \
  593. MGA_BLTMOD_BFCOL | \
  594. MGA_CLIPDIS)
  595. /* Simple idle test.
  596. */
  597. static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
  598. {
  599. u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
  600. return (status == MGA_ENDPRDMASTS);
  601. }
  602. #endif