meson_vpp.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  6. * Copyright (C) 2014 Endless Mobile
  7. */
  8. #include <linux/export.h>
  9. #include "meson_drv.h"
  10. #include "meson_registers.h"
  11. #include "meson_vpp.h"
  12. /**
  13. * DOC: Video Post Processing
  14. *
  15. * VPP Handles all the Post Processing after the Scanout from the VIU
  16. * We handle the following post processings :
  17. *
  18. * - Postblend, Blends the OSD1 only
  19. * We exclude OSD2, VS1, VS1 and Preblend output
  20. * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
  21. * use it only for interlace scanout
  22. * - Intermediate FIFO with default Amlogic values
  23. *
  24. * What is missing :
  25. *
  26. * - Preblend for video overlay pre-scaling
  27. * - OSD2 support for cursor framebuffer
  28. * - Video pre-scaling before postblend
  29. * - Full Vertical/Horizontal OSD scaling to support TV overscan
  30. * - HDR conversion
  31. */
  32. void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
  33. {
  34. writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
  35. }
  36. static unsigned int vpp_filter_coefs_4point_bspline[] = {
  37. 0x15561500, 0x14561600, 0x13561700, 0x12561800,
  38. 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
  39. 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
  40. 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
  41. 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
  42. 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
  43. 0x05473301, 0x05463401, 0x04453601, 0x04433702,
  44. 0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
  45. 0x033d3d03
  46. };
  47. static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
  48. const unsigned int *coefs,
  49. bool is_horizontal)
  50. {
  51. int i;
  52. writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
  53. priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
  54. for (i = 0; i < 33; i++)
  55. writel_relaxed(coefs[i],
  56. priv->io_base + _REG(VPP_OSD_SCALE_COEF));
  57. }
  58. static const uint32_t vpp_filter_coefs_bicubic[] = {
  59. 0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
  60. 0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
  61. 0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
  62. 0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
  63. 0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
  64. 0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
  65. 0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
  66. 0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
  67. 0xf84848f8
  68. };
  69. static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
  70. const unsigned int *coefs,
  71. bool is_horizontal)
  72. {
  73. int i;
  74. writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
  75. priv->io_base + _REG(VPP_SCALE_COEF_IDX));
  76. for (i = 0; i < 33; i++)
  77. writel_relaxed(coefs[i],
  78. priv->io_base + _REG(VPP_SCALE_COEF));
  79. }
  80. void meson_vpp_init(struct meson_drm *priv)
  81. {
  82. /* set dummy data default YUV black */
  83. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  84. writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
  85. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
  86. writel_bits_relaxed(0xff << 16, 0xff << 16,
  87. priv->io_base + _REG(VIU_MISC_CTRL1));
  88. writel_relaxed(VPP_PPS_DUMMY_DATA_MODE,
  89. priv->io_base + _REG(VPP_DOLBY_CTRL));
  90. writel_relaxed(0x1020080,
  91. priv->io_base + _REG(VPP_DUMMY_DATA1));
  92. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  93. writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
  94. /* Initialize vpu fifo control registers */
  95. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  96. writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
  97. priv->io_base + _REG(VPP_OFIFO_SIZE));
  98. else
  99. writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f,
  100. priv->io_base + _REG(VPP_OFIFO_SIZE));
  101. writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
  102. priv->io_base + _REG(VPP_HOLD_LINES));
  103. if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  104. /* Turn off preblend */
  105. writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
  106. priv->io_base + _REG(VPP_MISC));
  107. /* Turn off POSTBLEND */
  108. writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
  109. priv->io_base + _REG(VPP_MISC));
  110. /* Force all planes off */
  111. writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
  112. VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
  113. VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
  114. priv->io_base + _REG(VPP_MISC));
  115. /* Setup default VD settings */
  116. writel_relaxed(4096,
  117. priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
  118. writel_relaxed(4096,
  119. priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
  120. }
  121. /* Disable Scalers */
  122. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  123. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  124. writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  125. /* Set horizontal/vertical bank length and enable video scale out */
  126. writel_relaxed(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) |
  127. VPP_SC_VD_EN_ENABLE,
  128. priv->io_base + _REG(VPP_SC_MISC));
  129. /* Enable minus black level for vadj1 */
  130. writel_relaxed(VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,
  131. priv->io_base + _REG(VPP_VADJ_CTRL));
  132. /* Write in the proper filter coefficients. */
  133. meson_vpp_write_scaling_filter_coefs(priv,
  134. vpp_filter_coefs_4point_bspline, false);
  135. meson_vpp_write_scaling_filter_coefs(priv,
  136. vpp_filter_coefs_4point_bspline, true);
  137. /* Write the VD proper filter coefficients. */
  138. meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
  139. false);
  140. meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
  141. true);
  142. }