meson_viu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  6. * Copyright (C) 2014 Endless Mobile
  7. */
  8. #include <linux/export.h>
  9. #include <linux/bitfield.h>
  10. #include <drm/drm_fourcc.h>
  11. #include "meson_drv.h"
  12. #include "meson_viu.h"
  13. #include "meson_registers.h"
  14. /**
  15. * DOC: Video Input Unit
  16. *
  17. * VIU Handles the Pixel scanout and the basic Colorspace conversions
  18. * We handle the following features :
  19. *
  20. * - OSD1 RGB565/RGB888/xRGB8888 scanout
  21. * - RGB conversion to x/cb/cr
  22. * - Progressive or Interlace buffer scanout
  23. * - OSD1 Commit on Vsync
  24. * - HDR OSD matrix for GXL/GXM
  25. *
  26. * What is missing :
  27. *
  28. * - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
  29. * - YUV4:2:2 Y0CbY1Cr scanout
  30. * - Conversion to YUV 4:4:4 from 4:2:2 input
  31. * - Colorkey Alpha matching
  32. * - Big endian scanout
  33. * - X/Y reverse scanout
  34. * - Global alpha setup
  35. * - OSD2 support, would need interlace switching on vsync
  36. * - OSD1 full scaling to support TV overscan
  37. */
  38. /* OSD csc defines */
  39. enum viu_matrix_sel_e {
  40. VIU_MATRIX_OSD_EOTF = 0,
  41. VIU_MATRIX_OSD,
  42. };
  43. enum viu_lut_sel_e {
  44. VIU_LUT_OSD_EOTF = 0,
  45. VIU_LUT_OSD_OETF,
  46. };
  47. #define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2))
  48. #define MATRIX_5X3_COEF_SIZE 24
  49. #define EOTF_COEFF_NORM(a) ((int)((((a) * 4096.0) + 1) / 2))
  50. #define EOTF_COEFF_SIZE 10
  51. #define EOTF_COEFF_RIGHTSHIFT 1
  52. static int RGB709_to_YUV709l_coeff[MATRIX_5X3_COEF_SIZE] = {
  53. 0, 0, 0, /* pre offset */
  54. COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
  55. COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
  56. COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
  57. 0, 0, 0, /* 10'/11'/12' */
  58. 0, 0, 0, /* 20'/21'/22' */
  59. 64, 512, 512, /* offset */
  60. 0, 0, 0 /* mode, right_shift, clip_en */
  61. };
  62. /* eotf matrix: bypass */
  63. static int eotf_bypass_coeff[EOTF_COEFF_SIZE] = {
  64. EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0),
  65. EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0),
  66. EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0),
  67. EOTF_COEFF_RIGHTSHIFT /* right shift */
  68. };
  69. static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv,
  70. int *m, bool csc_on)
  71. {
  72. /* VPP WRAP OSD1 matrix */
  73. writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
  74. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1));
  75. writel(m[2] & 0xfff,
  76. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2));
  77. writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
  78. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01));
  79. writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
  80. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10));
  81. writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
  82. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
  83. writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
  84. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
  85. writel((m[11] & 0x1fff) << 16,
  86. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22));
  87. writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
  88. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1));
  89. writel(m[20] & 0xfff,
  90. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2));
  91. writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
  92. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
  93. }
  94. static void meson_viu_set_osd_matrix(struct meson_drm *priv,
  95. enum viu_matrix_sel_e m_select,
  96. int *m, bool csc_on)
  97. {
  98. if (m_select == VIU_MATRIX_OSD) {
  99. /* osd matrix, VIU_MATRIX_0 */
  100. writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
  101. priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1));
  102. writel(m[2] & 0xfff,
  103. priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2));
  104. writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
  105. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01));
  106. writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
  107. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10));
  108. writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
  109. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12));
  110. writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
  111. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21));
  112. if (m[21]) {
  113. writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff),
  114. priv->io_base +
  115. _REG(VIU_OSD1_MATRIX_COEF22_30));
  116. writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff),
  117. priv->io_base +
  118. _REG(VIU_OSD1_MATRIX_COEF31_32));
  119. writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff),
  120. priv->io_base +
  121. _REG(VIU_OSD1_MATRIX_COEF40_41));
  122. writel(m[17] & 0x1fff, priv->io_base +
  123. _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
  124. } else
  125. writel((m[11] & 0x1fff) << 16, priv->io_base +
  126. _REG(VIU_OSD1_MATRIX_COEF22_30));
  127. writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
  128. priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1));
  129. writel(m[20] & 0xfff,
  130. priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2));
  131. writel_bits_relaxed(3 << 30, m[21] << 30,
  132. priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
  133. writel_bits_relaxed(7 << 16, m[22] << 16,
  134. priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
  135. /* 23 reserved for clipping control */
  136. writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
  137. priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
  138. writel_bits_relaxed(BIT(1), 0,
  139. priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
  140. } else if (m_select == VIU_MATRIX_OSD_EOTF) {
  141. int i;
  142. /* osd eotf matrix, VIU_MATRIX_OSD_EOTF */
  143. for (i = 0; i < 5; i++)
  144. writel(((m[i * 2] & 0x1fff) << 16) |
  145. (m[i * 2 + 1] & 0x1fff), priv->io_base +
  146. _REG(VIU_OSD1_EOTF_CTL + i + 1));
  147. writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0,
  148. priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
  149. writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0,
  150. priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
  151. }
  152. }
  153. #define OSD_EOTF_LUT_SIZE 33
  154. #define OSD_OETF_LUT_SIZE 41
  155. static void
  156. meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel,
  157. unsigned int *r_map, unsigned int *g_map,
  158. unsigned int *b_map, bool csc_on)
  159. {
  160. unsigned int addr_port;
  161. unsigned int data_port;
  162. unsigned int ctrl_port;
  163. int i;
  164. if (lut_sel == VIU_LUT_OSD_EOTF) {
  165. addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT;
  166. data_port = VIU_OSD1_EOTF_LUT_DATA_PORT;
  167. ctrl_port = VIU_OSD1_EOTF_CTL;
  168. } else if (lut_sel == VIU_LUT_OSD_OETF) {
  169. addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT;
  170. data_port = VIU_OSD1_OETF_LUT_DATA_PORT;
  171. ctrl_port = VIU_OSD1_OETF_CTL;
  172. } else
  173. return;
  174. if (lut_sel == VIU_LUT_OSD_OETF) {
  175. writel(0, priv->io_base + _REG(addr_port));
  176. for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++)
  177. writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
  178. priv->io_base + _REG(data_port));
  179. writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16),
  180. priv->io_base + _REG(data_port));
  181. for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++)
  182. writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
  183. priv->io_base + _REG(data_port));
  184. for (i = 0; i < (OSD_OETF_LUT_SIZE / 2); i++)
  185. writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
  186. priv->io_base + _REG(data_port));
  187. writel(b_map[OSD_OETF_LUT_SIZE - 1],
  188. priv->io_base + _REG(data_port));
  189. if (csc_on)
  190. writel_bits_relaxed(0x7 << 29, 7 << 29,
  191. priv->io_base + _REG(ctrl_port));
  192. else
  193. writel_bits_relaxed(0x7 << 29, 0,
  194. priv->io_base + _REG(ctrl_port));
  195. } else if (lut_sel == VIU_LUT_OSD_EOTF) {
  196. writel(0, priv->io_base + _REG(addr_port));
  197. for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++)
  198. writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
  199. priv->io_base + _REG(data_port));
  200. writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16),
  201. priv->io_base + _REG(data_port));
  202. for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++)
  203. writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
  204. priv->io_base + _REG(data_port));
  205. for (i = 0; i < (OSD_EOTF_LUT_SIZE / 2); i++)
  206. writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
  207. priv->io_base + _REG(data_port));
  208. writel(b_map[OSD_EOTF_LUT_SIZE - 1],
  209. priv->io_base + _REG(data_port));
  210. if (csc_on)
  211. writel_bits_relaxed(7 << 27, 7 << 27,
  212. priv->io_base + _REG(ctrl_port));
  213. else
  214. writel_bits_relaxed(7 << 27, 0,
  215. priv->io_base + _REG(ctrl_port));
  216. writel_bits_relaxed(BIT(31), BIT(31),
  217. priv->io_base + _REG(ctrl_port));
  218. }
  219. }
  220. /* eotf lut: linear */
  221. static unsigned int eotf_33_linear_mapping[OSD_EOTF_LUT_SIZE] = {
  222. 0x0000, 0x0200, 0x0400, 0x0600,
  223. 0x0800, 0x0a00, 0x0c00, 0x0e00,
  224. 0x1000, 0x1200, 0x1400, 0x1600,
  225. 0x1800, 0x1a00, 0x1c00, 0x1e00,
  226. 0x2000, 0x2200, 0x2400, 0x2600,
  227. 0x2800, 0x2a00, 0x2c00, 0x2e00,
  228. 0x3000, 0x3200, 0x3400, 0x3600,
  229. 0x3800, 0x3a00, 0x3c00, 0x3e00,
  230. 0x4000
  231. };
  232. /* osd oetf lut: linear */
  233. static unsigned int oetf_41_linear_mapping[OSD_OETF_LUT_SIZE] = {
  234. 0, 0, 0, 0,
  235. 0, 32, 64, 96,
  236. 128, 160, 196, 224,
  237. 256, 288, 320, 352,
  238. 384, 416, 448, 480,
  239. 512, 544, 576, 608,
  240. 640, 672, 704, 736,
  241. 768, 800, 832, 864,
  242. 896, 928, 960, 992,
  243. 1023, 1023, 1023, 1023,
  244. 1023
  245. };
  246. static void meson_viu_load_matrix(struct meson_drm *priv)
  247. {
  248. /* eotf lut bypass */
  249. meson_viu_set_osd_lut(priv, VIU_LUT_OSD_EOTF,
  250. eotf_33_linear_mapping, /* R */
  251. eotf_33_linear_mapping, /* G */
  252. eotf_33_linear_mapping, /* B */
  253. false);
  254. /* eotf matrix bypass */
  255. meson_viu_set_osd_matrix(priv, VIU_MATRIX_OSD_EOTF,
  256. eotf_bypass_coeff,
  257. false);
  258. /* oetf lut bypass */
  259. meson_viu_set_osd_lut(priv, VIU_LUT_OSD_OETF,
  260. oetf_41_linear_mapping, /* R */
  261. oetf_41_linear_mapping, /* G */
  262. oetf_41_linear_mapping, /* B */
  263. false);
  264. /* osd matrix RGB709 to YUV709 limit */
  265. meson_viu_set_osd_matrix(priv, VIU_MATRIX_OSD,
  266. RGB709_to_YUV709l_coeff,
  267. true);
  268. }
  269. /* VIU OSD1 Reset as workaround for GXL+ Alpha OSD Bug */
  270. void meson_viu_osd1_reset(struct meson_drm *priv)
  271. {
  272. uint32_t osd1_fifo_ctrl_stat, osd1_ctrl_stat2;
  273. /* Save these 2 registers state */
  274. osd1_fifo_ctrl_stat = readl_relaxed(
  275. priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
  276. osd1_ctrl_stat2 = readl_relaxed(
  277. priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
  278. /* Reset OSD1 */
  279. writel_bits_relaxed(VIU_SW_RESET_OSD1, VIU_SW_RESET_OSD1,
  280. priv->io_base + _REG(VIU_SW_RESET));
  281. writel_bits_relaxed(VIU_SW_RESET_OSD1, 0,
  282. priv->io_base + _REG(VIU_SW_RESET));
  283. /* Rewrite these registers state lost in the reset */
  284. writel_relaxed(osd1_fifo_ctrl_stat,
  285. priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
  286. writel_relaxed(osd1_ctrl_stat2,
  287. priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
  288. /* Reload the conversion matrix */
  289. meson_viu_load_matrix(priv);
  290. }
  291. #define OSD1_MALI_ORDER_ABGR \
  292. (FIELD_PREP(VIU_OSD1_MALI_AFBCD_A_REORDER, \
  293. VIU_OSD1_MALI_REORDER_A) | \
  294. FIELD_PREP(VIU_OSD1_MALI_AFBCD_B_REORDER, \
  295. VIU_OSD1_MALI_REORDER_B) | \
  296. FIELD_PREP(VIU_OSD1_MALI_AFBCD_G_REORDER, \
  297. VIU_OSD1_MALI_REORDER_G) | \
  298. FIELD_PREP(VIU_OSD1_MALI_AFBCD_R_REORDER, \
  299. VIU_OSD1_MALI_REORDER_R))
  300. #define OSD1_MALI_ORDER_ARGB \
  301. (FIELD_PREP(VIU_OSD1_MALI_AFBCD_A_REORDER, \
  302. VIU_OSD1_MALI_REORDER_A) | \
  303. FIELD_PREP(VIU_OSD1_MALI_AFBCD_B_REORDER, \
  304. VIU_OSD1_MALI_REORDER_R) | \
  305. FIELD_PREP(VIU_OSD1_MALI_AFBCD_G_REORDER, \
  306. VIU_OSD1_MALI_REORDER_G) | \
  307. FIELD_PREP(VIU_OSD1_MALI_AFBCD_R_REORDER, \
  308. VIU_OSD1_MALI_REORDER_B))
  309. void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv)
  310. {
  311. u32 afbc_order = OSD1_MALI_ORDER_ARGB;
  312. /* Enable Mali AFBC Unpack */
  313. writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN,
  314. VIU_OSD1_MALI_UNPACK_EN,
  315. priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL));
  316. switch (priv->afbcd.format) {
  317. case DRM_FORMAT_XBGR8888:
  318. case DRM_FORMAT_ABGR8888:
  319. afbc_order = OSD1_MALI_ORDER_ABGR;
  320. break;
  321. }
  322. /* Setup RGBA Reordering */
  323. writel_bits_relaxed(VIU_OSD1_MALI_AFBCD_A_REORDER |
  324. VIU_OSD1_MALI_AFBCD_B_REORDER |
  325. VIU_OSD1_MALI_AFBCD_G_REORDER |
  326. VIU_OSD1_MALI_AFBCD_R_REORDER,
  327. afbc_order,
  328. priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL));
  329. /* Select AFBCD path for OSD1 */
  330. writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD,
  331. OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD,
  332. priv->io_base + _REG(OSD_PATH_MISC_CTRL));
  333. }
  334. void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv)
  335. {
  336. /* Disable AFBCD path for OSD1 */
  337. writel_bits_relaxed(OSD_PATH_OSD_AXI_SEL_OSD1_AFBCD, 0,
  338. priv->io_base + _REG(OSD_PATH_MISC_CTRL));
  339. /* Disable AFBCD unpack */
  340. writel_bits_relaxed(VIU_OSD1_MALI_UNPACK_EN, 0,
  341. priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL));
  342. }
  343. void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv)
  344. {
  345. writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x90),
  346. priv->io_base + _REG(VIU_MISC_CTRL1));
  347. }
  348. void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv)
  349. {
  350. writel_bits_relaxed(MALI_AFBC_MISC, FIELD_PREP(MALI_AFBC_MISC, 0x00),
  351. priv->io_base + _REG(VIU_MISC_CTRL1));
  352. }
  353. void meson_viu_init(struct meson_drm *priv)
  354. {
  355. uint32_t reg;
  356. /* Disable OSDs */
  357. writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
  358. priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  359. writel_bits_relaxed(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
  360. priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
  361. /* On GXL/GXM, Use the 10bit HDR conversion matrix */
  362. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  363. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  364. meson_viu_load_matrix(priv);
  365. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  366. meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
  367. true);
  368. /* fix green/pink color distortion from vendor u-boot */
  369. writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
  370. OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
  371. priv->io_base + _REG(OSD1_HDR2_CTRL));
  372. }
  373. /* Initialize OSD1 fifo control register */
  374. reg = VIU_OSD_DDR_PRIORITY_URGENT |
  375. VIU_OSD_HOLD_FIFO_LINES(31) |
  376. VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
  377. VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
  378. VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
  379. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  380. reg |= VIU_OSD_BURST_LENGTH_32;
  381. else
  382. reg |= VIU_OSD_BURST_LENGTH_64;
  383. writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
  384. writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
  385. /* Set OSD alpha replace value */
  386. writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
  387. 0xff << OSD_REPLACE_SHIFT,
  388. priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
  389. writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
  390. 0xff << OSD_REPLACE_SHIFT,
  391. priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
  392. /* Disable VD1 AFBC */
  393. /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/
  394. writel_bits_relaxed(VIU_CTRL0_VD1_AFBC_MASK, 0,
  395. priv->io_base + _REG(VIU_MISC_CTRL0));
  396. writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
  397. writel_relaxed(0x00FF00C0,
  398. priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE));
  399. writel_relaxed(0x00FF00C0,
  400. priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
  401. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  402. writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
  403. VIU_OSD_BLEND_REORDER(1, 0) |
  404. VIU_OSD_BLEND_REORDER(2, 0) |
  405. VIU_OSD_BLEND_REORDER(3, 0) |
  406. VIU_OSD_BLEND_DIN_EN(1) |
  407. VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
  408. VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
  409. VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
  410. VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
  411. VIU_OSD_BLEND_HOLD_LINES(4),
  412. priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
  413. writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
  414. priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
  415. writel_relaxed(OSD_BLEND_PATH_SEL_ENABLE,
  416. priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));
  417. writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
  418. writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
  419. writel_relaxed(0,
  420. priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0));
  421. writel_relaxed(0,
  422. priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA));
  423. writel_bits_relaxed(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc),
  424. priv->io_base + _REG(DOLBY_PATH_CTRL));
  425. meson_viu_g12a_disable_osd1_afbc(priv);
  426. }
  427. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
  428. meson_viu_gxm_disable_osd1_afbc(priv);
  429. priv->viu.osd1_enabled = false;
  430. priv->viu.osd1_commit = false;
  431. priv->viu.osd1_interlace = false;
  432. }