meson_vclk.h 886 B

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. /* Video Clock */
  7. #ifndef __MESON_VCLK_H
  8. #define __MESON_VCLK_H
  9. #include <drm/drm_modes.h>
  10. struct meson_drm;
  11. enum {
  12. MESON_VCLK_TARGET_CVBS = 0,
  13. MESON_VCLK_TARGET_HDMI = 1,
  14. MESON_VCLK_TARGET_DMT = 2,
  15. };
  16. /* 27MHz is the CVBS Pixel Clock */
  17. #define MESON_VCLK_CVBS 27000
  18. enum drm_mode_status
  19. meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
  20. enum drm_mode_status
  21. meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq,
  22. unsigned int vclk_freq);
  23. void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
  24. unsigned int phy_freq, unsigned int vclk_freq,
  25. unsigned int venc_freq, unsigned int dac_freq,
  26. bool hdmi_use_enci);
  27. #endif /* __MESON_VCLK_H */