meson_plane.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  6. * Copyright (C) 2014 Endless Mobile
  7. *
  8. * Written by:
  9. * Jasper St. Pierre <jstpierre@mecheye.net>
  10. */
  11. #include <linux/bitfield.h>
  12. #include <drm/drm_atomic.h>
  13. #include <drm/drm_atomic_helper.h>
  14. #include <drm/drm_device.h>
  15. #include <drm/drm_fb_cma_helper.h>
  16. #include <drm/drm_fourcc.h>
  17. #include <drm/drm_gem_cma_helper.h>
  18. #include <drm/drm_gem_framebuffer_helper.h>
  19. #include <drm/drm_plane_helper.h>
  20. #include "meson_plane.h"
  21. #include "meson_registers.h"
  22. #include "meson_viu.h"
  23. #include "meson_osd_afbcd.h"
  24. /* OSD_SCI_WH_M1 */
  25. #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w)
  26. #define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h)
  27. /* OSD_SCO_H_START_END */
  28. /* OSD_SCO_V_START_END */
  29. #define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start)
  30. #define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end)
  31. /* OSD_SC_CTRL0 */
  32. #define SC_CTRL0_PATH_EN BIT(3)
  33. #define SC_CTRL0_SEL_OSD1 BIT(2)
  34. /* OSD_VSC_CTRL0 */
  35. #define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value)
  36. #define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value)
  37. #define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value)
  38. #define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value)
  39. #define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value)
  40. #define VSC_PROG_INTERLACE BIT(23)
  41. #define VSC_VERTICAL_SCALER_EN BIT(24)
  42. /* OSD_VSC_INI_PHASE */
  43. #define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom)
  44. #define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top)
  45. /* OSD_HSC_CTRL0 */
  46. #define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value)
  47. #define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value)
  48. #define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value)
  49. #define HSC_HORIZ_SCALER_EN BIT(22)
  50. /* VPP_OSD_VSC_PHASE_STEP */
  51. /* VPP_OSD_HSC_PHASE_STEP */
  52. #define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value)
  53. struct meson_plane {
  54. struct drm_plane base;
  55. struct meson_drm *priv;
  56. bool enabled;
  57. };
  58. #define to_meson_plane(x) container_of(x, struct meson_plane, base)
  59. #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
  60. static int meson_plane_atomic_check(struct drm_plane *plane,
  61. struct drm_plane_state *state)
  62. {
  63. struct drm_crtc_state *crtc_state;
  64. if (!state->crtc)
  65. return 0;
  66. crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
  67. if (IS_ERR(crtc_state))
  68. return PTR_ERR(crtc_state);
  69. /*
  70. * Only allow :
  71. * - Upscaling up to 5x, vertical and horizontal
  72. * - Final coordinates must match crtc size
  73. */
  74. return drm_atomic_helper_check_plane_state(state, crtc_state,
  75. FRAC_16_16(1, 5),
  76. DRM_PLANE_HELPER_NO_SCALING,
  77. false, true);
  78. }
  79. #define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \
  80. AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \
  81. AFBC_FORMAT_MOD_YTR | \
  82. AFBC_FORMAT_MOD_SPARSE | \
  83. AFBC_FORMAT_MOD_SPLIT)
  84. /* Takes a fixed 16.16 number and converts it to integer. */
  85. static inline int64_t fixed16_to_int(int64_t value)
  86. {
  87. return value >> 16;
  88. }
  89. static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv)
  90. {
  91. u32 line_stride = 0;
  92. switch (priv->afbcd.format) {
  93. case DRM_FORMAT_RGB565:
  94. line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7;
  95. break;
  96. case DRM_FORMAT_RGB888:
  97. case DRM_FORMAT_XRGB8888:
  98. case DRM_FORMAT_ARGB8888:
  99. case DRM_FORMAT_XBGR8888:
  100. case DRM_FORMAT_ABGR8888:
  101. line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7;
  102. break;
  103. }
  104. return ((line_stride + 1) >> 1) << 1;
  105. }
  106. static void meson_plane_atomic_update(struct drm_plane *plane,
  107. struct drm_plane_state *old_state)
  108. {
  109. struct meson_plane *meson_plane = to_meson_plane(plane);
  110. struct drm_plane_state *state = plane->state;
  111. struct drm_rect dest = drm_plane_state_dest(state);
  112. struct meson_drm *priv = meson_plane->priv;
  113. struct drm_framebuffer *fb = state->fb;
  114. struct drm_gem_cma_object *gem;
  115. unsigned long flags;
  116. int vsc_ini_rcv_num, vsc_ini_rpt_p0_num;
  117. int vsc_bot_rcv_num, vsc_bot_rpt_p0_num;
  118. int hsc_ini_rcv_num, hsc_ini_rpt_p0_num;
  119. int hf_phase_step, vf_phase_step;
  120. int src_w, src_h, dst_w, dst_h;
  121. int bot_ini_phase;
  122. int hf_bank_len;
  123. int vf_bank_len;
  124. u8 canvas_id_osd1;
  125. /*
  126. * Update Coordinates
  127. * Update Formats
  128. * Update Buffer
  129. * Enable Plane
  130. */
  131. spin_lock_irqsave(&priv->drm->event_lock, flags);
  132. /* Check if AFBC decoder is required for this buffer */
  133. if ((meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  134. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) &&
  135. fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS))
  136. priv->viu.osd1_afbcd = true;
  137. else
  138. priv->viu.osd1_afbcd = false;
  139. /* Enable OSD and BLK0, set max global alpha */
  140. priv->viu.osd1_ctrl_stat = OSD_ENABLE |
  141. (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
  142. OSD_BLK0_ENABLE;
  143. priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
  144. _REG(VIU_OSD1_CTRL_STAT2));
  145. canvas_id_osd1 = priv->canvas_id_osd1;
  146. /* Set up BLK0 to point to the right canvas */
  147. priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL;
  148. if (priv->viu.osd1_afbcd) {
  149. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  150. /* This is the internal decoding memory address */
  151. priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR;
  152. priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE;
  153. priv->viu.osd1_ctrl_stat2 |= OSD_PENDING_STAT_CLEAN;
  154. priv->viu.osd1_ctrl_stat |= VIU_OSD1_CFG_SYN_EN;
  155. }
  156. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
  157. priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
  158. priv->viu.osd1_ctrl_stat2 |= OSD_DPATH_MALI_AFBCD;
  159. }
  160. } else {
  161. priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
  162. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
  163. priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD;
  164. }
  165. /* On GXBB, Use the old non-HDR RGB2YUV converter */
  166. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  167. priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
  168. if (priv->viu.osd1_afbcd &&
  169. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  170. priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN |
  171. priv->afbcd.ops->fmt_to_blk_mode(fb->modifier,
  172. fb->format->format);
  173. } else {
  174. switch (fb->format->format) {
  175. case DRM_FORMAT_XRGB8888:
  176. case DRM_FORMAT_ARGB8888:
  177. priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
  178. OSD_COLOR_MATRIX_32_ARGB;
  179. break;
  180. case DRM_FORMAT_XBGR8888:
  181. case DRM_FORMAT_ABGR8888:
  182. priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
  183. OSD_COLOR_MATRIX_32_ABGR;
  184. break;
  185. case DRM_FORMAT_RGB888:
  186. priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
  187. OSD_COLOR_MATRIX_24_RGB;
  188. break;
  189. case DRM_FORMAT_RGB565:
  190. priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
  191. OSD_COLOR_MATRIX_16_RGB565;
  192. break;
  193. }
  194. }
  195. switch (fb->format->format) {
  196. case DRM_FORMAT_XRGB8888:
  197. case DRM_FORMAT_XBGR8888:
  198. /* For XRGB, replace the pixel's alpha by 0xFF */
  199. priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN;
  200. break;
  201. case DRM_FORMAT_ARGB8888:
  202. case DRM_FORMAT_ABGR8888:
  203. /* For ARGB, use the pixel's alpha */
  204. priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN;
  205. break;
  206. }
  207. /* Default scaler parameters */
  208. vsc_bot_rcv_num = 0;
  209. vsc_bot_rpt_p0_num = 0;
  210. hf_bank_len = 4;
  211. vf_bank_len = 4;
  212. if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
  213. vsc_bot_rcv_num = 6;
  214. vsc_bot_rpt_p0_num = 2;
  215. }
  216. hsc_ini_rcv_num = hf_bank_len;
  217. vsc_ini_rcv_num = vf_bank_len;
  218. hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1;
  219. vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1;
  220. src_w = fixed16_to_int(state->src_w);
  221. src_h = fixed16_to_int(state->src_h);
  222. dst_w = state->crtc_w;
  223. dst_h = state->crtc_h;
  224. /*
  225. * When the output is interlaced, the OSD must switch between
  226. * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
  227. * at each vsync.
  228. * But the vertical scaler can provide such funtionnality if
  229. * is configured for 2:1 scaling with interlace options enabled.
  230. */
  231. if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
  232. dest.y1 /= 2;
  233. dest.y2 /= 2;
  234. dst_h /= 2;
  235. }
  236. hf_phase_step = ((src_w << 18) / dst_w) << 6;
  237. vf_phase_step = (src_h << 20) / dst_h;
  238. if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
  239. bot_ini_phase = ((vf_phase_step / 2) >> 4);
  240. else
  241. bot_ini_phase = 0;
  242. vf_phase_step = (vf_phase_step << 4);
  243. /* In interlaced mode, scaler is always active */
  244. if (src_h != dst_h || src_w != dst_w) {
  245. priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
  246. SCI_WH_M1_H(src_h - 1);
  247. priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
  248. SCO_HV_END(dest.x2 - 1);
  249. priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
  250. SCO_HV_END(dest.y2 - 1);
  251. /* Enable OSD Scaler */
  252. priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
  253. } else {
  254. priv->viu.osd_sc_i_wh_m1 = 0;
  255. priv->viu.osd_sc_o_h_start_end = 0;
  256. priv->viu.osd_sc_o_v_start_end = 0;
  257. priv->viu.osd_sc_ctrl0 = 0;
  258. }
  259. /* In interlaced mode, vertical scaler is always active */
  260. if (src_h != dst_h) {
  261. priv->viu.osd_sc_v_ctrl0 =
  262. VSC_BANK_LEN(vf_bank_len) |
  263. VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) |
  264. VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) |
  265. VSC_VERTICAL_SCALER_EN;
  266. if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
  267. priv->viu.osd_sc_v_ctrl0 |=
  268. VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) |
  269. VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) |
  270. VSC_PROG_INTERLACE;
  271. priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
  272. priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
  273. } else {
  274. priv->viu.osd_sc_v_ctrl0 = 0;
  275. priv->viu.osd_sc_v_phase_step = 0;
  276. priv->viu.osd_sc_v_ini_phase = 0;
  277. }
  278. /* Horizontal scaler is only used if width does not match */
  279. if (src_w != dst_w) {
  280. priv->viu.osd_sc_h_ctrl0 =
  281. HSC_BANK_LENGTH(hf_bank_len) |
  282. HSC_INI_RCV_NUM0(hsc_ini_rcv_num) |
  283. HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) |
  284. HSC_HORIZ_SCALER_EN;
  285. priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
  286. priv->viu.osd_sc_h_ini_phase = 0;
  287. } else {
  288. priv->viu.osd_sc_h_ctrl0 = 0;
  289. priv->viu.osd_sc_h_phase_step = 0;
  290. priv->viu.osd_sc_h_ini_phase = 0;
  291. }
  292. /*
  293. * The format of these registers is (x2 << 16 | x1),
  294. * where x2 is exclusive.
  295. * e.g. +30x1920 would be (1919 << 16) | 30
  296. */
  297. priv->viu.osd1_blk0_cfg[1] =
  298. ((fixed16_to_int(state->src.x2) - 1) << 16) |
  299. fixed16_to_int(state->src.x1);
  300. priv->viu.osd1_blk0_cfg[2] =
  301. ((fixed16_to_int(state->src.y2) - 1) << 16) |
  302. fixed16_to_int(state->src.y1);
  303. priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
  304. priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
  305. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  306. priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
  307. priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
  308. priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
  309. priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
  310. }
  311. /* Update Canvas with buffer address */
  312. gem = drm_fb_cma_get_gem_obj(fb, 0);
  313. priv->viu.osd1_addr = gem->paddr;
  314. priv->viu.osd1_stride = fb->pitches[0];
  315. priv->viu.osd1_height = fb->height;
  316. priv->viu.osd1_width = fb->width;
  317. if (priv->viu.osd1_afbcd) {
  318. priv->afbcd.modifier = fb->modifier;
  319. priv->afbcd.format = fb->format->format;
  320. /* Calculate decoder write stride */
  321. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  322. priv->viu.osd1_blk2_cfg4 =
  323. meson_g12a_afbcd_line_stride(priv);
  324. }
  325. if (!meson_plane->enabled) {
  326. /* Reset OSD1 before enabling it on GXL+ SoCs */
  327. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  328. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  329. meson_viu_osd1_reset(priv);
  330. meson_plane->enabled = true;
  331. }
  332. priv->viu.osd1_enabled = true;
  333. spin_unlock_irqrestore(&priv->drm->event_lock, flags);
  334. }
  335. static void meson_plane_atomic_disable(struct drm_plane *plane,
  336. struct drm_plane_state *old_state)
  337. {
  338. struct meson_plane *meson_plane = to_meson_plane(plane);
  339. struct meson_drm *priv = meson_plane->priv;
  340. if (priv->afbcd.ops) {
  341. priv->afbcd.ops->reset(priv);
  342. priv->afbcd.ops->disable(priv);
  343. }
  344. /* Disable OSD1 */
  345. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  346. writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0,
  347. priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
  348. else
  349. writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
  350. priv->io_base + _REG(VPP_MISC));
  351. meson_plane->enabled = false;
  352. priv->viu.osd1_enabled = false;
  353. }
  354. static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
  355. .atomic_check = meson_plane_atomic_check,
  356. .atomic_disable = meson_plane_atomic_disable,
  357. .atomic_update = meson_plane_atomic_update,
  358. .prepare_fb = drm_gem_fb_prepare_fb,
  359. };
  360. static bool meson_plane_format_mod_supported(struct drm_plane *plane,
  361. u32 format, u64 modifier)
  362. {
  363. struct meson_plane *meson_plane = to_meson_plane(plane);
  364. struct meson_drm *priv = meson_plane->priv;
  365. int i;
  366. if (modifier == DRM_FORMAT_MOD_INVALID)
  367. return false;
  368. if (modifier == DRM_FORMAT_MOD_LINEAR)
  369. return true;
  370. if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) &&
  371. !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  372. return false;
  373. if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS))
  374. return false;
  375. for (i = 0 ; i < plane->modifier_count ; ++i)
  376. if (plane->modifiers[i] == modifier)
  377. break;
  378. if (i == plane->modifier_count) {
  379. DRM_DEBUG_KMS("Unsupported modifier\n");
  380. return false;
  381. }
  382. if (priv->afbcd.ops && priv->afbcd.ops->supported_fmt)
  383. return priv->afbcd.ops->supported_fmt(modifier, format);
  384. DRM_DEBUG_KMS("AFBC Unsupported\n");
  385. return false;
  386. }
  387. static const struct drm_plane_funcs meson_plane_funcs = {
  388. .update_plane = drm_atomic_helper_update_plane,
  389. .disable_plane = drm_atomic_helper_disable_plane,
  390. .destroy = drm_plane_cleanup,
  391. .reset = drm_atomic_helper_plane_reset,
  392. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  393. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  394. .format_mod_supported = meson_plane_format_mod_supported,
  395. };
  396. static const uint32_t supported_drm_formats[] = {
  397. DRM_FORMAT_ARGB8888,
  398. DRM_FORMAT_ABGR8888,
  399. DRM_FORMAT_XRGB8888,
  400. DRM_FORMAT_XBGR8888,
  401. DRM_FORMAT_RGB888,
  402. DRM_FORMAT_RGB565,
  403. };
  404. static const uint64_t format_modifiers_afbc_gxm[] = {
  405. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
  406. AFBC_FORMAT_MOD_SPARSE |
  407. AFBC_FORMAT_MOD_YTR),
  408. /* SPLIT mandates SPARSE, RGB modes mandates YTR */
  409. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
  410. AFBC_FORMAT_MOD_YTR |
  411. AFBC_FORMAT_MOD_SPARSE |
  412. AFBC_FORMAT_MOD_SPLIT),
  413. DRM_FORMAT_MOD_LINEAR,
  414. DRM_FORMAT_MOD_INVALID,
  415. };
  416. static const uint64_t format_modifiers_afbc_g12a[] = {
  417. /*
  418. * - TOFIX Support AFBC modifiers for YUV formats (16x16 + TILED)
  419. * - SPLIT is mandatory for performances reasons when in 16x16
  420. * block size
  421. * - 32x8 block size + SPLIT is mandatory with 4K frame size
  422. * for performances reasons
  423. */
  424. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
  425. AFBC_FORMAT_MOD_SPARSE |
  426. AFBC_FORMAT_MOD_SPLIT),
  427. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
  428. AFBC_FORMAT_MOD_YTR |
  429. AFBC_FORMAT_MOD_SPARSE |
  430. AFBC_FORMAT_MOD_SPLIT),
  431. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
  432. AFBC_FORMAT_MOD_SPARSE),
  433. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
  434. AFBC_FORMAT_MOD_YTR |
  435. AFBC_FORMAT_MOD_SPARSE),
  436. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
  437. AFBC_FORMAT_MOD_SPARSE |
  438. AFBC_FORMAT_MOD_SPLIT),
  439. DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 |
  440. AFBC_FORMAT_MOD_YTR |
  441. AFBC_FORMAT_MOD_SPARSE |
  442. AFBC_FORMAT_MOD_SPLIT),
  443. DRM_FORMAT_MOD_LINEAR,
  444. DRM_FORMAT_MOD_INVALID,
  445. };
  446. static const uint64_t format_modifiers_default[] = {
  447. DRM_FORMAT_MOD_LINEAR,
  448. DRM_FORMAT_MOD_INVALID,
  449. };
  450. int meson_plane_create(struct meson_drm *priv)
  451. {
  452. struct meson_plane *meson_plane;
  453. struct drm_plane *plane;
  454. const uint64_t *format_modifiers = format_modifiers_default;
  455. meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
  456. GFP_KERNEL);
  457. if (!meson_plane)
  458. return -ENOMEM;
  459. meson_plane->priv = priv;
  460. plane = &meson_plane->base;
  461. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
  462. format_modifiers = format_modifiers_afbc_gxm;
  463. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  464. format_modifiers = format_modifiers_afbc_g12a;
  465. drm_universal_plane_init(priv->drm, plane, 0xFF,
  466. &meson_plane_funcs,
  467. supported_drm_formats,
  468. ARRAY_SIZE(supported_drm_formats),
  469. format_modifiers,
  470. DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
  471. drm_plane_helper_add(plane, &meson_plane_helper_funcs);
  472. /* For now, OSD Primary plane is always on the front */
  473. drm_plane_create_zpos_immutable_property(plane, 1);
  474. priv->primary_plane = plane;
  475. return 0;
  476. }