meson_overlay.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <drm/drm_atomic.h>
  9. #include <drm/drm_atomic_helper.h>
  10. #include <drm/drm_device.h>
  11. #include <drm/drm_fourcc.h>
  12. #include <drm/drm_plane_helper.h>
  13. #include <drm/drm_gem_cma_helper.h>
  14. #include <drm/drm_fb_cma_helper.h>
  15. #include <drm/drm_gem_framebuffer_helper.h>
  16. #include "meson_overlay.h"
  17. #include "meson_registers.h"
  18. #include "meson_viu.h"
  19. #include "meson_vpp.h"
  20. /* VD1_IF0_GEN_REG */
  21. #define VD_URGENT_CHROMA BIT(28)
  22. #define VD_URGENT_LUMA BIT(27)
  23. #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)
  24. #define VD_DEMUX_MODE_RGB BIT(16)
  25. #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)
  26. #define VD_CHRO_RPT_LASTL_CTRL BIT(6)
  27. #define VD_LITTLE_ENDIAN BIT(4)
  28. #define VD_SEPARATE_EN BIT(1)
  29. #define VD_ENABLE BIT(0)
  30. /* VD1_IF0_CANVAS0 */
  31. #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
  32. #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
  33. #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
  34. /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */
  35. #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
  36. #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
  37. /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */
  38. #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
  39. #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
  40. /* VD1_IF0_GEN_REG2 */
  41. #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)
  42. /* VIU_VD1_FMT_CTRL */
  43. #define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)
  44. #define VD_HORZ_FMT_EN BIT(20)
  45. #define VD_VERT_RPT_LINE0 BIT(16)
  46. #define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)
  47. #define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
  48. #define VD_VERT_FMT_EN BIT(0)
  49. /* VPP_POSTBLEND_VD1_H_START_END */
  50. #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value)
  51. #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \
  52. ((value) & GENMASK(13, 0)))
  53. /* VPP_POSTBLEND_VD1_V_START_END */
  54. #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
  55. #define VD_V_START(value) FIELD_PREP(GENMASK(27, 16), value)
  56. /* VPP_BLEND_VD2_V_START_END */
  57. #define VD2_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
  58. #define VD2_V_START(value) FIELD_PREP(GENMASK(27, 16), value)
  59. /* VIU_VD1_FMT_W */
  60. #define VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)
  61. #define VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)
  62. /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */
  63. #define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value)
  64. #define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value)
  65. /* AFBC_ENABLE */
  66. #define AFBC_DEC_ENABLE BIT(8)
  67. #define AFBC_FRM_START BIT(0)
  68. /* AFBC_MODE */
  69. #define AFBC_HORZ_SKIP_UV(value) FIELD_PREP(GENMASK(1, 0), value)
  70. #define AFBC_VERT_SKIP_UV(value) FIELD_PREP(GENMASK(3, 2), value)
  71. #define AFBC_HORZ_SKIP_Y(value) FIELD_PREP(GENMASK(5, 4), value)
  72. #define AFBC_VERT_SKIP_Y(value) FIELD_PREP(GENMASK(7, 6), value)
  73. #define AFBC_COMPBITS_YUV(value) FIELD_PREP(GENMASK(13, 8), value)
  74. #define AFBC_COMPBITS_8BIT 0
  75. #define AFBC_COMPBITS_10BIT (2 | (2 << 2) | (2 << 4))
  76. #define AFBC_BURST_LEN(value) FIELD_PREP(GENMASK(15, 14), value)
  77. #define AFBC_HOLD_LINE_NUM(value) FIELD_PREP(GENMASK(22, 16), value)
  78. #define AFBC_MIF_URGENT(value) FIELD_PREP(GENMASK(25, 24), value)
  79. #define AFBC_REV_MODE(value) FIELD_PREP(GENMASK(27, 26), value)
  80. #define AFBC_BLK_MEM_MODE BIT(28)
  81. #define AFBC_SCATTER_MODE BIT(29)
  82. #define AFBC_SOFT_RESET BIT(31)
  83. /* AFBC_SIZE_IN */
  84. #define AFBC_HSIZE_IN(value) FIELD_PREP(GENMASK(28, 16), value)
  85. #define AFBC_VSIZE_IN(value) FIELD_PREP(GENMASK(12, 0), value)
  86. /* AFBC_DEC_DEF_COLOR */
  87. #define AFBC_DEF_COLOR_Y(value) FIELD_PREP(GENMASK(29, 20), value)
  88. #define AFBC_DEF_COLOR_U(value) FIELD_PREP(GENMASK(19, 10), value)
  89. #define AFBC_DEF_COLOR_V(value) FIELD_PREP(GENMASK(9, 0), value)
  90. /* AFBC_CONV_CTRL */
  91. #define AFBC_CONV_LBUF_LEN(value) FIELD_PREP(GENMASK(11, 0), value)
  92. /* AFBC_LBUF_DEPTH */
  93. #define AFBC_DEC_LBUF_DEPTH(value) FIELD_PREP(GENMASK(27, 16), value)
  94. #define AFBC_MIF_LBUF_DEPTH(value) FIELD_PREP(GENMASK(11, 0), value)
  95. /* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */
  96. #define AFBC_HSIZE_OUT(value) FIELD_PREP(GENMASK(28, 16), value)
  97. #define AFBC_VSIZE_OUT(value) FIELD_PREP(GENMASK(12, 0), value)
  98. #define AFBC_OUT_HORZ_BGN(value) FIELD_PREP(GENMASK(28, 16), value)
  99. #define AFBC_OUT_HORZ_END(value) FIELD_PREP(GENMASK(12, 0), value)
  100. /* AFBC_OUT_YSCOPE */
  101. #define AFBC_OUT_VERT_BGN(value) FIELD_PREP(GENMASK(28, 16), value)
  102. #define AFBC_OUT_VERT_END(value) FIELD_PREP(GENMASK(12, 0), value)
  103. /* AFBC_VD_CFMT_CTRL */
  104. #define AFBC_HORZ_RPT_PIXEL0 BIT(23)
  105. #define AFBC_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)
  106. #define AFBC_HORZ_FMT_EN BIT(20)
  107. #define AFBC_VERT_RPT_LINE0 BIT(16)
  108. #define AFBC_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)
  109. #define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
  110. #define AFBC_VERT_FMT_EN BIT(0)
  111. /* AFBC_VD_CFMT_W */
  112. #define AFBC_VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)
  113. #define AFBC_VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)
  114. /* AFBC_MIF_HOR_SCOPE */
  115. #define AFBC_MIF_BLK_BGN_H(value) FIELD_PREP(GENMASK(25, 16), value)
  116. #define AFBC_MIF_BLK_END_H(value) FIELD_PREP(GENMASK(9, 0), value)
  117. /* AFBC_MIF_VER_SCOPE */
  118. #define AFBC_MIF_BLK_BGN_V(value) FIELD_PREP(GENMASK(27, 16), value)
  119. #define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value)
  120. /* AFBC_PIXEL_HOR_SCOPE */
  121. #define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), \
  122. ((value) & GENMASK(12, 0)))
  123. #define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value)
  124. /* AFBC_PIXEL_VER_SCOPE */
  125. #define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value)
  126. #define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value)
  127. /* AFBC_VD_CFMT_H */
  128. #define AFBC_VD_HEIGHT(value) FIELD_PREP(GENMASK(12, 0), value)
  129. struct meson_overlay {
  130. struct drm_plane base;
  131. struct meson_drm *priv;
  132. };
  133. #define to_meson_overlay(x) container_of(x, struct meson_overlay, base)
  134. #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
  135. static int meson_overlay_atomic_check(struct drm_plane *plane,
  136. struct drm_plane_state *state)
  137. {
  138. struct drm_crtc_state *crtc_state;
  139. if (!state->crtc)
  140. return 0;
  141. crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
  142. if (IS_ERR(crtc_state))
  143. return PTR_ERR(crtc_state);
  144. return drm_atomic_helper_check_plane_state(state, crtc_state,
  145. FRAC_16_16(1, 5),
  146. FRAC_16_16(5, 1),
  147. true, true);
  148. }
  149. /* Takes a fixed 16.16 number and converts it to integer. */
  150. static inline int64_t fixed16_to_int(int64_t value)
  151. {
  152. return value >> 16;
  153. }
  154. static const uint8_t skip_tab[6] = {
  155. 0x24, 0x04, 0x68, 0x48, 0x28, 0x08,
  156. };
  157. static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
  158. int *repeat, bool interlace)
  159. {
  160. int offset_in = 0;
  161. int offset_out = 0;
  162. int repeat_skip = 0;
  163. if (!interlace && ratio_y > (1 << 18))
  164. offset_out = (1 * ratio_y) >> 10;
  165. while ((offset_in + (4 << 8)) <= offset_out) {
  166. repeat_skip++;
  167. offset_in += 4 << 8;
  168. }
  169. *phase = (offset_out - offset_in) >> 2;
  170. if (*phase > 0x100)
  171. repeat_skip++;
  172. *phase = *phase & 0xff;
  173. if (repeat_skip > 5)
  174. repeat_skip = 5;
  175. *repeat = skip_tab[repeat_skip];
  176. }
  177. static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
  178. struct drm_plane *plane,
  179. bool interlace_mode)
  180. {
  181. struct drm_crtc_state *crtc_state = priv->crtc->state;
  182. int video_top, video_left, video_width, video_height;
  183. struct drm_plane_state *state = plane->state;
  184. unsigned int vd_start_lines, vd_end_lines;
  185. unsigned int hd_start_lines, hd_end_lines;
  186. unsigned int crtc_height, crtc_width;
  187. unsigned int vsc_startp, vsc_endp;
  188. unsigned int hsc_startp, hsc_endp;
  189. unsigned int crop_top, crop_left;
  190. int vphase, vphase_repeat_skip;
  191. unsigned int ratio_x, ratio_y;
  192. int temp_height, temp_width;
  193. unsigned int w_in, h_in;
  194. int afbc_left, afbc_right;
  195. int afbc_top_src, afbc_bottom_src;
  196. int afbc_top, afbc_bottom;
  197. int temp, start, end;
  198. if (!crtc_state) {
  199. DRM_ERROR("Invalid crtc_state\n");
  200. return;
  201. }
  202. crtc_height = crtc_state->mode.vdisplay;
  203. crtc_width = crtc_state->mode.hdisplay;
  204. w_in = fixed16_to_int(state->src_w);
  205. h_in = fixed16_to_int(state->src_h);
  206. crop_top = fixed16_to_int(state->src_y);
  207. crop_left = fixed16_to_int(state->src_x);
  208. video_top = state->crtc_y;
  209. video_left = state->crtc_x;
  210. video_width = state->crtc_w;
  211. video_height = state->crtc_h;
  212. DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n",
  213. crtc_width, crtc_height, interlace_mode);
  214. DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n",
  215. w_in, h_in, crop_top, crop_left);
  216. DRM_DEBUG("video top %d left %d width %d height %d\n",
  217. video_top, video_left, video_width, video_height);
  218. ratio_x = (w_in << 18) / video_width;
  219. ratio_y = (h_in << 18) / video_height;
  220. if (ratio_x * video_width < (w_in << 18))
  221. ratio_x++;
  222. DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y);
  223. meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip,
  224. interlace_mode);
  225. DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip);
  226. /* Vertical */
  227. start = video_top + video_height / 2 - ((h_in << 17) / ratio_y);
  228. end = (h_in << 18) / ratio_y + start - 1;
  229. if (video_top < 0 && start < 0)
  230. vd_start_lines = (-(start) * ratio_y) >> 18;
  231. else if (start < video_top)
  232. vd_start_lines = ((video_top - start) * ratio_y) >> 18;
  233. else
  234. vd_start_lines = 0;
  235. if (video_top < 0)
  236. temp_height = min_t(unsigned int,
  237. video_top + video_height - 1,
  238. crtc_height - 1);
  239. else
  240. temp_height = min_t(unsigned int,
  241. video_top + video_height - 1,
  242. crtc_height - 1) - video_top + 1;
  243. temp = vd_start_lines + (temp_height * ratio_y >> 18);
  244. vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1);
  245. vd_start_lines += crop_left;
  246. vd_end_lines += crop_left;
  247. /*
  248. * TOFIX: Input frames are handled and scaled like progressive frames,
  249. * proper handling of interlaced field input frames need to be figured
  250. * out using the proper framebuffer flags set by userspace.
  251. */
  252. if (interlace_mode) {
  253. start >>= 1;
  254. end >>= 1;
  255. }
  256. vsc_startp = max_t(int, start,
  257. max_t(int, 0, video_top));
  258. vsc_endp = min_t(int, end,
  259. min_t(int, crtc_height - 1,
  260. video_top + video_height - 1));
  261. DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
  262. vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
  263. afbc_top = round_down(vd_start_lines, 4);
  264. afbc_bottom = round_up(vd_end_lines + 1, 4);
  265. afbc_top_src = 0;
  266. afbc_bottom_src = round_up(h_in + 1, 4);
  267. DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n",
  268. afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src);
  269. /* Horizontal */
  270. start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
  271. end = (w_in << 18) / ratio_x + start - 1;
  272. if (video_left < 0 && start < 0)
  273. hd_start_lines = (-(start) * ratio_x) >> 18;
  274. else if (start < video_left)
  275. hd_start_lines = ((video_left - start) * ratio_x) >> 18;
  276. else
  277. hd_start_lines = 0;
  278. if (video_left < 0)
  279. temp_width = min_t(unsigned int,
  280. video_left + video_width - 1,
  281. crtc_width - 1);
  282. else
  283. temp_width = min_t(unsigned int,
  284. video_left + video_width - 1,
  285. crtc_width - 1) - video_left + 1;
  286. temp = hd_start_lines + (temp_width * ratio_x >> 18);
  287. hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1);
  288. priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
  289. hsc_startp = max_t(int, start, max_t(int, 0, video_left));
  290. hsc_endp = min_t(int, end, min_t(int, crtc_width - 1,
  291. video_left + video_width - 1));
  292. hd_start_lines += crop_top;
  293. hd_end_lines += crop_top;
  294. DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
  295. hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
  296. if (hd_start_lines > 0 || (hd_end_lines < w_in)) {
  297. afbc_left = 0;
  298. afbc_right = round_up(w_in, 32);
  299. } else {
  300. afbc_left = round_down(hd_start_lines, 32);
  301. afbc_right = round_up(hd_end_lines + 1, 32);
  302. }
  303. DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right);
  304. priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
  305. priv->viu.vpp_vsc_ini_phase = vphase << 8;
  306. priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) |
  307. vphase_repeat_skip;
  308. priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) |
  309. VD_X_END(hd_end_lines);
  310. priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) |
  311. VD_X_END(hd_end_lines >> 1);
  312. priv->viu.viu_vd1_fmt_w =
  313. VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
  314. VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
  315. priv->viu.vd1_afbc_vd_cfmt_w =
  316. AFBC_VD_H_WIDTH(afbc_right - afbc_left) |
  317. AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2);
  318. priv->viu.vd1_afbc_vd_cfmt_h =
  319. AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2);
  320. priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) |
  321. AFBC_MIF_BLK_END_H((afbc_right / 32) - 1);
  322. priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) |
  323. AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1);
  324. priv->viu.vd1_afbc_size_out =
  325. AFBC_HSIZE_OUT(afbc_right - afbc_left) |
  326. AFBC_VSIZE_OUT(afbc_bottom - afbc_top);
  327. priv->viu.vd1_afbc_pixel_hor_scope =
  328. AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) |
  329. AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left);
  330. priv->viu.vd1_afbc_pixel_ver_scope =
  331. AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) |
  332. AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top);
  333. priv->viu.vd1_afbc_size_in =
  334. AFBC_HSIZE_IN(afbc_right - afbc_left) |
  335. AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src);
  336. priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
  337. VD_Y_END(vd_end_lines);
  338. priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) |
  339. VD_Y_END(vd_end_lines >> 1);
  340. priv->viu.vpp_pic_in_height = h_in;
  341. priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) |
  342. VD_H_END(hsc_endp);
  343. priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) |
  344. VD_H_END(hd_end_lines);
  345. priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) |
  346. VD_REGION24_START(hsc_startp);
  347. priv->viu.vpp_hsc_region34_startp =
  348. VD_REGION13_END(hsc_startp) |
  349. VD_REGION24_START(hsc_endp - hsc_startp);
  350. priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp;
  351. priv->viu.vpp_hsc_start_phase_step = ratio_x << 6;
  352. priv->viu.vpp_hsc_region1_phase_slope = 0;
  353. priv->viu.vpp_hsc_region3_phase_slope = 0;
  354. priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);
  355. priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
  356. priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1;
  357. priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) |
  358. VD_V_END(vsc_endp);
  359. priv->viu.vpp_blend_vd2_v_start_end =
  360. VD2_V_START((vd_end_lines + 1) >> 1) |
  361. VD2_V_END(vd_end_lines);
  362. priv->viu.vpp_vsc_region12_startp = 0;
  363. priv->viu.vpp_vsc_region34_startp =
  364. VD_REGION13_END(vsc_endp - vsc_startp) |
  365. VD_REGION24_START(vsc_endp - vsc_startp);
  366. priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp;
  367. priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
  368. }
  369. static void meson_overlay_atomic_update(struct drm_plane *plane,
  370. struct drm_plane_state *old_state)
  371. {
  372. struct meson_overlay *meson_overlay = to_meson_overlay(plane);
  373. struct drm_plane_state *state = plane->state;
  374. struct drm_framebuffer *fb = state->fb;
  375. struct meson_drm *priv = meson_overlay->priv;
  376. struct drm_gem_cma_object *gem;
  377. unsigned long flags;
  378. bool interlace_mode;
  379. DRM_DEBUG_DRIVER("\n");
  380. interlace_mode = state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
  381. spin_lock_irqsave(&priv->drm->event_lock, flags);
  382. if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
  383. DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
  384. priv->viu.vd1_afbc = true;
  385. priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) |
  386. AFBC_HOLD_LINE_NUM(8) |
  387. AFBC_BURST_LEN(2);
  388. if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0,
  389. AMLOGIC_FBC_OPTION_MEM_SAVING))
  390. priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
  391. if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) ==
  392. AMLOGIC_FBC_LAYOUT_SCATTER)
  393. priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
  394. priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE;
  395. priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256);
  396. priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023);
  397. /* 420: horizontal / 2, vertical / 4 */
  398. priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 |
  399. AFBC_HORZ_Y_C_RATIO(1) |
  400. AFBC_HORZ_FMT_EN |
  401. AFBC_VERT_RPT_LINE0 |
  402. AFBC_VERT_INITIAL_PHASE(12) |
  403. AFBC_VERT_PHASE_STEP(8) |
  404. AFBC_VERT_FMT_EN;
  405. switch (fb->format->format) {
  406. /* AFBC Only formats */
  407. case DRM_FORMAT_YUV420_10BIT:
  408. priv->viu.vd1_afbc_mode |=
  409. AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT);
  410. priv->viu.vd1_afbc_dec_def_color |=
  411. AFBC_DEF_COLOR_U(512) |
  412. AFBC_DEF_COLOR_V(512);
  413. break;
  414. case DRM_FORMAT_YUV420_8BIT:
  415. priv->viu.vd1_afbc_dec_def_color |=
  416. AFBC_DEF_COLOR_U(128) |
  417. AFBC_DEF_COLOR_V(128);
  418. break;
  419. }
  420. priv->viu.vd1_if0_gen_reg = 0;
  421. priv->viu.vd1_if0_canvas0 = 0;
  422. priv->viu.viu_vd1_fmt_ctrl = 0;
  423. } else {
  424. priv->viu.vd1_afbc = false;
  425. priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
  426. VD_URGENT_LUMA |
  427. VD_HOLD_LINES(9) |
  428. VD_CHRO_RPT_LASTL_CTRL |
  429. VD_ENABLE;
  430. }
  431. /* Setup scaler params */
  432. meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
  433. priv->viu.vd1_if0_repeat_loop = 0;
  434. priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0;
  435. priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0;
  436. priv->viu.vd1_range_map_y = 0;
  437. priv->viu.vd1_range_map_cb = 0;
  438. priv->viu.vd1_range_map_cr = 0;
  439. /* Default values for RGB888/YUV444 */
  440. priv->viu.vd1_if0_gen_reg2 = 0;
  441. priv->viu.viu_vd1_fmt_ctrl = 0;
  442. /* None will match for AFBC Only formats */
  443. switch (fb->format->format) {
  444. /* TOFIX DRM_FORMAT_RGB888 should be supported */
  445. case DRM_FORMAT_YUYV:
  446. priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1);
  447. priv->viu.vd1_if0_canvas0 =
  448. CANVAS_ADDR2(priv->canvas_id_vd1_0) |
  449. CANVAS_ADDR1(priv->canvas_id_vd1_0) |
  450. CANVAS_ADDR0(priv->canvas_id_vd1_0);
  451. priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
  452. VD_HORZ_FMT_EN |
  453. VD_VERT_RPT_LINE0 |
  454. VD_VERT_INITIAL_PHASE(12) |
  455. VD_VERT_PHASE_STEP(16) | /* /2 */
  456. VD_VERT_FMT_EN;
  457. break;
  458. case DRM_FORMAT_NV12:
  459. case DRM_FORMAT_NV21:
  460. priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
  461. priv->viu.vd1_if0_canvas0 =
  462. CANVAS_ADDR2(priv->canvas_id_vd1_1) |
  463. CANVAS_ADDR1(priv->canvas_id_vd1_1) |
  464. CANVAS_ADDR0(priv->canvas_id_vd1_0);
  465. if (fb->format->format == DRM_FORMAT_NV12)
  466. priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1);
  467. else
  468. priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2);
  469. priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
  470. VD_HORZ_FMT_EN |
  471. VD_VERT_RPT_LINE0 |
  472. VD_VERT_INITIAL_PHASE(12) |
  473. VD_VERT_PHASE_STEP(8) | /* /4 */
  474. VD_VERT_FMT_EN;
  475. break;
  476. case DRM_FORMAT_YUV444:
  477. case DRM_FORMAT_YUV422:
  478. case DRM_FORMAT_YUV420:
  479. case DRM_FORMAT_YUV411:
  480. case DRM_FORMAT_YUV410:
  481. priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
  482. priv->viu.vd1_if0_canvas0 =
  483. CANVAS_ADDR2(priv->canvas_id_vd1_2) |
  484. CANVAS_ADDR1(priv->canvas_id_vd1_1) |
  485. CANVAS_ADDR0(priv->canvas_id_vd1_0);
  486. switch (fb->format->format) {
  487. case DRM_FORMAT_YUV422:
  488. priv->viu.viu_vd1_fmt_ctrl =
  489. VD_HORZ_Y_C_RATIO(1) | /* /2 */
  490. VD_HORZ_FMT_EN |
  491. VD_VERT_RPT_LINE0 |
  492. VD_VERT_INITIAL_PHASE(12) |
  493. VD_VERT_PHASE_STEP(16) | /* /2 */
  494. VD_VERT_FMT_EN;
  495. break;
  496. case DRM_FORMAT_YUV420:
  497. priv->viu.viu_vd1_fmt_ctrl =
  498. VD_HORZ_Y_C_RATIO(1) | /* /2 */
  499. VD_HORZ_FMT_EN |
  500. VD_VERT_RPT_LINE0 |
  501. VD_VERT_INITIAL_PHASE(12) |
  502. VD_VERT_PHASE_STEP(8) | /* /4 */
  503. VD_VERT_FMT_EN;
  504. break;
  505. case DRM_FORMAT_YUV411:
  506. priv->viu.viu_vd1_fmt_ctrl =
  507. VD_HORZ_Y_C_RATIO(2) | /* /4 */
  508. VD_HORZ_FMT_EN |
  509. VD_VERT_RPT_LINE0 |
  510. VD_VERT_INITIAL_PHASE(12) |
  511. VD_VERT_PHASE_STEP(16) | /* /2 */
  512. VD_VERT_FMT_EN;
  513. break;
  514. case DRM_FORMAT_YUV410:
  515. priv->viu.viu_vd1_fmt_ctrl =
  516. VD_HORZ_Y_C_RATIO(2) | /* /4 */
  517. VD_HORZ_FMT_EN |
  518. VD_VERT_RPT_LINE0 |
  519. VD_VERT_INITIAL_PHASE(12) |
  520. VD_VERT_PHASE_STEP(8) | /* /4 */
  521. VD_VERT_FMT_EN;
  522. break;
  523. }
  524. break;
  525. }
  526. /* Update Canvas with buffer address */
  527. priv->viu.vd1_planes = fb->format->num_planes;
  528. switch (priv->viu.vd1_planes) {
  529. case 3:
  530. gem = drm_fb_cma_get_gem_obj(fb, 2);
  531. priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2];
  532. priv->viu.vd1_stride2 = fb->pitches[2];
  533. priv->viu.vd1_height2 =
  534. drm_format_info_plane_height(fb->format,
  535. fb->height, 2);
  536. DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n",
  537. priv->viu.vd1_addr2,
  538. priv->viu.vd1_stride2,
  539. priv->viu.vd1_height2);
  540. fallthrough;
  541. case 2:
  542. gem = drm_fb_cma_get_gem_obj(fb, 1);
  543. priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
  544. priv->viu.vd1_stride1 = fb->pitches[1];
  545. priv->viu.vd1_height1 =
  546. drm_format_info_plane_height(fb->format,
  547. fb->height, 1);
  548. DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n",
  549. priv->viu.vd1_addr1,
  550. priv->viu.vd1_stride1,
  551. priv->viu.vd1_height1);
  552. fallthrough;
  553. case 1:
  554. gem = drm_fb_cma_get_gem_obj(fb, 0);
  555. priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
  556. priv->viu.vd1_stride0 = fb->pitches[0];
  557. priv->viu.vd1_height0 =
  558. drm_format_info_plane_height(fb->format,
  559. fb->height, 0);
  560. DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
  561. priv->viu.vd1_addr0,
  562. priv->viu.vd1_stride0,
  563. priv->viu.vd1_height0);
  564. }
  565. if (priv->viu.vd1_afbc) {
  566. if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
  567. /*
  568. * In Scatter mode, the header contains the physical
  569. * body content layout, thus the body content
  570. * size isn't needed.
  571. */
  572. priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
  573. priv->viu.vd1_afbc_body_addr = 0;
  574. } else {
  575. /* Default mode is 4k per superblock */
  576. unsigned long block_size = 4096;
  577. unsigned long body_size;
  578. /* 8bit mem saving mode is 3072bytes per superblock */
  579. if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
  580. block_size = 3072;
  581. body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
  582. (ALIGN(priv->viu.vd1_height0, 32) / 32) *
  583. block_size;
  584. priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
  585. /* Header is after body content */
  586. priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
  587. body_size) >> 4;
  588. }
  589. }
  590. priv->viu.vd1_enabled = true;
  591. spin_unlock_irqrestore(&priv->drm->event_lock, flags);
  592. DRM_DEBUG_DRIVER("\n");
  593. }
  594. static void meson_overlay_atomic_disable(struct drm_plane *plane,
  595. struct drm_plane_state *old_state)
  596. {
  597. struct meson_overlay *meson_overlay = to_meson_overlay(plane);
  598. struct meson_drm *priv = meson_overlay->priv;
  599. DRM_DEBUG_DRIVER("\n");
  600. priv->viu.vd1_enabled = false;
  601. /* Disable VD1 */
  602. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  603. writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
  604. writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
  605. writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
  606. writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
  607. } else
  608. writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
  609. priv->io_base + _REG(VPP_MISC));
  610. }
  611. static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
  612. .atomic_check = meson_overlay_atomic_check,
  613. .atomic_disable = meson_overlay_atomic_disable,
  614. .atomic_update = meson_overlay_atomic_update,
  615. .prepare_fb = drm_gem_fb_prepare_fb,
  616. };
  617. static bool meson_overlay_format_mod_supported(struct drm_plane *plane,
  618. u32 format, u64 modifier)
  619. {
  620. if (modifier == DRM_FORMAT_MOD_LINEAR &&
  621. format != DRM_FORMAT_YUV420_8BIT &&
  622. format != DRM_FORMAT_YUV420_10BIT)
  623. return true;
  624. if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
  625. DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
  626. unsigned int layout = modifier &
  627. DRM_FORMAT_MOD_AMLOGIC_FBC(
  628. __fourcc_mod_amlogic_layout_mask, 0);
  629. unsigned int options =
  630. (modifier >> __fourcc_mod_amlogic_options_shift) &
  631. __fourcc_mod_amlogic_options_mask;
  632. if (format != DRM_FORMAT_YUV420_8BIT &&
  633. format != DRM_FORMAT_YUV420_10BIT) {
  634. DRM_DEBUG_KMS("%llx invalid format 0x%08x\n",
  635. modifier, format);
  636. return false;
  637. }
  638. if (layout != AMLOGIC_FBC_LAYOUT_BASIC &&
  639. layout != AMLOGIC_FBC_LAYOUT_SCATTER) {
  640. DRM_DEBUG_KMS("%llx invalid layout %x\n",
  641. modifier, layout);
  642. return false;
  643. }
  644. if (options &&
  645. options != AMLOGIC_FBC_OPTION_MEM_SAVING) {
  646. DRM_DEBUG_KMS("%llx invalid layout %x\n",
  647. modifier, layout);
  648. return false;
  649. }
  650. return true;
  651. }
  652. DRM_DEBUG_KMS("invalid modifier %llx for format 0x%08x\n",
  653. modifier, format);
  654. return false;
  655. }
  656. static const struct drm_plane_funcs meson_overlay_funcs = {
  657. .update_plane = drm_atomic_helper_update_plane,
  658. .disable_plane = drm_atomic_helper_disable_plane,
  659. .destroy = drm_plane_cleanup,
  660. .reset = drm_atomic_helper_plane_reset,
  661. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  662. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  663. .format_mod_supported = meson_overlay_format_mod_supported,
  664. };
  665. static const uint32_t supported_drm_formats[] = {
  666. DRM_FORMAT_YUYV,
  667. DRM_FORMAT_NV12,
  668. DRM_FORMAT_NV21,
  669. DRM_FORMAT_YUV444,
  670. DRM_FORMAT_YUV422,
  671. DRM_FORMAT_YUV420,
  672. DRM_FORMAT_YUV411,
  673. DRM_FORMAT_YUV410,
  674. DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */
  675. DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */
  676. };
  677. static const uint64_t format_modifiers[] = {
  678. DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,
  679. AMLOGIC_FBC_OPTION_MEM_SAVING),
  680. DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC,
  681. AMLOGIC_FBC_OPTION_MEM_SAVING),
  682. DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0),
  683. DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0),
  684. DRM_FORMAT_MOD_LINEAR,
  685. DRM_FORMAT_MOD_INVALID,
  686. };
  687. int meson_overlay_create(struct meson_drm *priv)
  688. {
  689. struct meson_overlay *meson_overlay;
  690. struct drm_plane *plane;
  691. DRM_DEBUG_DRIVER("\n");
  692. meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay),
  693. GFP_KERNEL);
  694. if (!meson_overlay)
  695. return -ENOMEM;
  696. meson_overlay->priv = priv;
  697. plane = &meson_overlay->base;
  698. drm_universal_plane_init(priv->drm, plane, 0xFF,
  699. &meson_overlay_funcs,
  700. supported_drm_formats,
  701. ARRAY_SIZE(supported_drm_formats),
  702. format_modifiers,
  703. DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
  704. drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
  705. /* For now, VD Overlay plane is always on the back */
  706. drm_plane_create_zpos_immutable_property(plane, 0);
  707. priv->overlay_plane = plane;
  708. DRM_DEBUG_DRIVER("\n");
  709. return 0;
  710. }