meson_drv.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #ifndef __MESON_DRV_H
  7. #define __MESON_DRV_H
  8. #include <linux/device.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/regmap.h>
  12. struct drm_crtc;
  13. struct drm_device;
  14. struct drm_plane;
  15. struct meson_drm;
  16. struct meson_afbcd_ops;
  17. enum vpu_compatible {
  18. VPU_COMPATIBLE_GXBB = 0,
  19. VPU_COMPATIBLE_GXL = 1,
  20. VPU_COMPATIBLE_GXM = 2,
  21. VPU_COMPATIBLE_G12A = 3,
  22. };
  23. struct meson_drm_match_data {
  24. enum vpu_compatible compat;
  25. struct meson_afbcd_ops *afbcd_ops;
  26. };
  27. struct meson_drm_soc_limits {
  28. unsigned int max_hdmi_phy_freq;
  29. };
  30. struct meson_drm {
  31. struct device *dev;
  32. enum vpu_compatible compat;
  33. void __iomem *io_base;
  34. struct regmap *hhi;
  35. int vsync_irq;
  36. struct meson_canvas *canvas;
  37. u8 canvas_id_osd1;
  38. u8 canvas_id_vd1_0;
  39. u8 canvas_id_vd1_1;
  40. u8 canvas_id_vd1_2;
  41. struct drm_device *drm;
  42. struct drm_crtc *crtc;
  43. struct drm_plane *primary_plane;
  44. struct drm_plane *overlay_plane;
  45. const struct meson_drm_soc_limits *limits;
  46. /* Components Data */
  47. struct {
  48. bool osd1_enabled;
  49. bool osd1_interlace;
  50. bool osd1_commit;
  51. bool osd1_afbcd;
  52. uint32_t osd1_ctrl_stat;
  53. uint32_t osd1_ctrl_stat2;
  54. uint32_t osd1_blk0_cfg[5];
  55. uint32_t osd1_blk1_cfg4;
  56. uint32_t osd1_blk2_cfg4;
  57. uint32_t osd1_addr;
  58. uint32_t osd1_stride;
  59. uint32_t osd1_height;
  60. uint32_t osd1_width;
  61. uint32_t osd_sc_ctrl0;
  62. uint32_t osd_sc_i_wh_m1;
  63. uint32_t osd_sc_o_h_start_end;
  64. uint32_t osd_sc_o_v_start_end;
  65. uint32_t osd_sc_v_ini_phase;
  66. uint32_t osd_sc_v_phase_step;
  67. uint32_t osd_sc_h_ini_phase;
  68. uint32_t osd_sc_h_phase_step;
  69. uint32_t osd_sc_h_ctrl0;
  70. uint32_t osd_sc_v_ctrl0;
  71. uint32_t osd_blend_din0_scope_h;
  72. uint32_t osd_blend_din0_scope_v;
  73. uint32_t osb_blend0_size;
  74. uint32_t osb_blend1_size;
  75. bool vd1_enabled;
  76. bool vd1_commit;
  77. bool vd1_afbc;
  78. unsigned int vd1_planes;
  79. uint32_t vd1_if0_gen_reg;
  80. uint32_t vd1_if0_luma_x0;
  81. uint32_t vd1_if0_luma_y0;
  82. uint32_t vd1_if0_chroma_x0;
  83. uint32_t vd1_if0_chroma_y0;
  84. uint32_t vd1_if0_repeat_loop;
  85. uint32_t vd1_if0_luma0_rpt_pat;
  86. uint32_t vd1_if0_chroma0_rpt_pat;
  87. uint32_t vd1_range_map_y;
  88. uint32_t vd1_range_map_cb;
  89. uint32_t vd1_range_map_cr;
  90. uint32_t viu_vd1_fmt_w;
  91. uint32_t vd1_if0_canvas0;
  92. uint32_t vd1_if0_gen_reg2;
  93. uint32_t viu_vd1_fmt_ctrl;
  94. uint32_t vd1_addr0;
  95. uint32_t vd1_addr1;
  96. uint32_t vd1_addr2;
  97. uint32_t vd1_stride0;
  98. uint32_t vd1_stride1;
  99. uint32_t vd1_stride2;
  100. uint32_t vd1_height0;
  101. uint32_t vd1_height1;
  102. uint32_t vd1_height2;
  103. uint32_t vd1_afbc_mode;
  104. uint32_t vd1_afbc_en;
  105. uint32_t vd1_afbc_head_addr;
  106. uint32_t vd1_afbc_body_addr;
  107. uint32_t vd1_afbc_conv_ctrl;
  108. uint32_t vd1_afbc_dec_def_color;
  109. uint32_t vd1_afbc_vd_cfmt_ctrl;
  110. uint32_t vd1_afbc_vd_cfmt_w;
  111. uint32_t vd1_afbc_vd_cfmt_h;
  112. uint32_t vd1_afbc_mif_hor_scope;
  113. uint32_t vd1_afbc_mif_ver_scope;
  114. uint32_t vd1_afbc_size_out;
  115. uint32_t vd1_afbc_pixel_hor_scope;
  116. uint32_t vd1_afbc_pixel_ver_scope;
  117. uint32_t vd1_afbc_size_in;
  118. uint32_t vpp_pic_in_height;
  119. uint32_t vpp_postblend_vd1_h_start_end;
  120. uint32_t vpp_postblend_vd1_v_start_end;
  121. uint32_t vpp_hsc_region12_startp;
  122. uint32_t vpp_hsc_region34_startp;
  123. uint32_t vpp_hsc_region4_endp;
  124. uint32_t vpp_hsc_start_phase_step;
  125. uint32_t vpp_hsc_region1_phase_slope;
  126. uint32_t vpp_hsc_region3_phase_slope;
  127. uint32_t vpp_line_in_length;
  128. uint32_t vpp_preblend_h_size;
  129. uint32_t vpp_vsc_region12_startp;
  130. uint32_t vpp_vsc_region34_startp;
  131. uint32_t vpp_vsc_region4_endp;
  132. uint32_t vpp_vsc_start_phase_step;
  133. uint32_t vpp_vsc_ini_phase;
  134. uint32_t vpp_vsc_phase_ctrl;
  135. uint32_t vpp_hsc_phase_ctrl;
  136. uint32_t vpp_blend_vd2_h_start_end;
  137. uint32_t vpp_blend_vd2_v_start_end;
  138. } viu;
  139. struct {
  140. unsigned int current_mode;
  141. bool hdmi_repeat;
  142. bool venc_repeat;
  143. bool hdmi_use_enci;
  144. } venc;
  145. struct {
  146. dma_addr_t addr_dma;
  147. uint32_t *addr;
  148. unsigned int offset;
  149. } rdma;
  150. struct {
  151. struct meson_afbcd_ops *ops;
  152. u64 modifier;
  153. u32 format;
  154. } afbcd;
  155. };
  156. static inline int meson_vpu_is_compatible(struct meson_drm *priv,
  157. enum vpu_compatible family)
  158. {
  159. return priv->compat == family;
  160. }
  161. #endif /* __MESON_DRV_H */